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STM32L4: STM32Cube_FW_L4_V1.16.0
source: https://github.com/STMicroelectronics/STM32CubeL4
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‎targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l412xx.h

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‎targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l422xx.h

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‎targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l431xx.h

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‎targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l432xx.h

Lines changed: 25 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
1616
* All rights reserved.</center></h2>
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
18+
* This software component is licensed by ST under Apache License, Version 2.0,
1919
* the "License"; You may not use this file except in compliance with the
2020
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
21+
* opensource.org/licenses/Apache-2.0
2222
*
2323
******************************************************************************
2424
*/
@@ -913,7 +913,9 @@ typedef struct
913913
* @{
914914
*/
915915
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
916-
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
916+
#define FLASH_END (0x0803FFFFUL) /*!< FLASH END address */
917+
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< FLASH END address of bank1 */
918+
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
917919
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */
918920
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
919921
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
@@ -929,6 +931,11 @@ typedef struct
929931
#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
930932
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
931933

934+
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
935+
936+
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
937+
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
938+
932939
/*!< Peripheral memory map */
933940
#define APB1PERIPH_BASE PERIPH_BASE
934941
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -1046,7 +1053,6 @@ typedef struct
10461053
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
10471054
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
10481055
#define CRS ((CRS_TypeDef *) CRS_BASE)
1049-
// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED
10501056
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
10511057
#define USB ((USB_TypeDef *) USB_BASE)
10521058
#define PWR ((PWR_TypeDef *) PWR_BASE)
@@ -5700,6 +5706,13 @@ typedef struct
57005706
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
57015707
#define CRS_CR_TRIM_Pos (8U)
57025708
#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5709+
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
5710+
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
5711+
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
5712+
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
5713+
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
5714+
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
5715+
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
57035716
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
57045717

57055718
/******************* Bit definition for CRS_CFGR register *********************/
@@ -8924,13 +8937,15 @@ typedef struct
89248937

89258938
/*!< HSITRIM configuration */
89268939
#define RCC_ICSCR_HSITRIM_Pos (24U)
8927-
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
8928-
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
8940+
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
8941+
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
89298942
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
89308943
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
89318944
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
89328945
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
89338946
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
8947+
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
8948+
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
89348949

89358950
/******************** Bit definition for RCC_CFGR register ******************/
89368951
/*!< SW configuration */
@@ -9838,8 +9853,12 @@ typedef struct
98389853
* @brief Specific device feature definitions
98399854
*/
98409855
#define RTC_TAMPER2_SUPPORT
9856+
98419857
#define RTC_WAKEUP_SUPPORT
98429858
#define RTC_BACKUP_SUPPORT
9859+
/******************** Number of backup registers ******************************/
9860+
#define RTC_BKP_NUMBER 32U
9861+
98439862

98449863
/******************** Bits definition for RTC_TR register *******************/
98459864
#define RTC_TR_PM_Pos (22U)
@@ -10560,9 +10579,6 @@ typedef struct
1056010579
#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
1056110580
#define RTC_BKP31R RTC_BKP31R_Msk
1056210581

10563-
/******************** Number of backup registers ******************************/
10564-
#define RTC_BKP_NUMBER 32U
10565-
1056610582
/******************************************************************************/
1056710583
/* */
1056810584
/* Serial Audio Interface */
@@ -14732,9 +14748,6 @@ typedef struct
1473214748
((INSTANCE) == TIM15) || \
1473314749
((INSTANCE) == TIM16))
1473414750

14735-
/****************** TIM Instances : supporting synchronization ****************/
14736-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
14737-
1473814751
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1473914752
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1474014753

‎targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l433xx.h

Lines changed: 25 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@
1515
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
1616
* All rights reserved.</center></h2>
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
18+
* This software component is licensed by ST under Apache License, Version 2.0,
1919
* the "License"; You may not use this file except in compliance with the
2020
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
21+
* opensource.org/licenses/Apache-2.0
2222
*
2323
******************************************************************************
2424
*/
@@ -971,7 +971,9 @@ typedef struct
971971
* @{
972972
*/
973973
#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
974-
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
974+
#define FLASH_END (0x0803FFFFUL) /*!< FLASH END address */
975+
#define FLASH_BANK1_END (0x0803FFFFUL) /*!< FLASH END address of bank1 */
976+
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
975977
#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */
976978
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
977979
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
@@ -987,6 +989,11 @@ typedef struct
987989
#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
988990
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
989991

992+
#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
993+
994+
#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
995+
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
996+
990997
/*!< Peripheral memory map */
991998
#define APB1PERIPH_BASE PERIPH_BASE
992999
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
@@ -1116,7 +1123,6 @@ typedef struct
11161123
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
11171124
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
11181125
#define CRS ((CRS_TypeDef *) CRS_BASE)
1119-
// #define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED
11201126
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
11211127
#define USB ((USB_TypeDef *) USB_BASE)
11221128
#define PWR ((PWR_TypeDef *) PWR_BASE)
@@ -5774,6 +5780,13 @@ typedef struct
57745780
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
57755781
#define CRS_CR_TRIM_Pos (8U)
57765782
#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5783+
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
5784+
#define CRS_CR_TRIM_0 (0x01UL << CRS_CR_TRIM_Pos) /*!< 0x00000100 */
5785+
#define CRS_CR_TRIM_1 (0x02UL << CRS_CR_TRIM_Pos) /*!< 0x00000200 */
5786+
#define CRS_CR_TRIM_2 (0x04UL << CRS_CR_TRIM_Pos) /*!< 0x00000400 */
5787+
#define CRS_CR_TRIM_3 (0x08UL << CRS_CR_TRIM_Pos) /*!< 0x00000800 */
5788+
#define CRS_CR_TRIM_4 (0x10UL << CRS_CR_TRIM_Pos) /*!< 0x00001000 */
5789+
#define CRS_CR_TRIM_5 (0x20UL << CRS_CR_TRIM_Pos) /*!< 0x00002000 */
57775790
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
57785791

57795792
/******************* Bit definition for CRS_CFGR register *********************/
@@ -9355,13 +9368,15 @@ typedef struct
93559368

93569369
/*!< HSITRIM configuration */
93579370
#define RCC_ICSCR_HSITRIM_Pos (24U)
9358-
#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
9359-
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[4:0] bits */
9371+
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
9372+
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
93609373
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
93619374
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
93629375
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
93639376
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
93649377
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
9378+
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
9379+
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
93659380

93669381
/******************** Bit definition for RCC_CFGR register ******************/
93679382
/*!< SW configuration */
@@ -10346,8 +10361,12 @@ typedef struct
1034610361
#define RTC_TAMPER1_SUPPORT
1034710362
#define RTC_TAMPER2_SUPPORT
1034810363
#define RTC_TAMPER3_SUPPORT
10364+
1034910365
#define RTC_WAKEUP_SUPPORT
1035010366
#define RTC_BACKUP_SUPPORT
10367+
/******************** Number of backup registers ******************************/
10368+
#define RTC_BKP_NUMBER 32U
10369+
1035110370

1035210371
/******************** Bits definition for RTC_TR register *******************/
1035310372
#define RTC_TR_PM_Pos (22U)
@@ -11104,9 +11123,6 @@ typedef struct
1110411123
#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
1110511124
#define RTC_BKP31R RTC_BKP31R_Msk
1110611125

11107-
/******************** Number of backup registers ******************************/
11108-
#define RTC_BKP_NUMBER 32U
11109-
1111011126
/******************************************************************************/
1111111127
/* */
1111211128
/* Serial Audio Interface */
@@ -15826,9 +15842,6 @@ typedef struct
1582615842
((INSTANCE) == TIM15) || \
1582715843
((INSTANCE) == TIM16))
1582815844

15829-
/****************** TIM Instances : supporting synchronization ****************/
15830-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
15831-
1583215845
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1583315846
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1583415847

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