diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103x8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103x8/PeripheralNames.h
index 6bfba03fcbd..41bd9444832 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103x8/PeripheralNames.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103x8/PeripheralNames.h
@@ -68,6 +68,10 @@ typedef enum {
     CAN_1 = (int)CAN1_BASE
 } CANName;
 
+typedef enum {
+    USB_FS = (int)USB_BASE,
+} USBName;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103x8/system_clock.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103x8/system_clock.c
index 4b45d3670b8..431e3cf5640 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103x8/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_STM32F103x8/system_clock.c
@@ -16,23 +16,20 @@
 
 /**
   * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 8 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 36                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 72                     | 64
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | NO                     | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
+  *-------------------------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC  / DEVICE_USBDEVICE   | 3- PLL_HSI / DEVICE_USBDEVICE
+  *                                    | (external 8 MHz clock)                | (internal 8 MHz)
+  *                                    | 2- PLL_HSE_XTAL / DEVICE_USBDEVICE    |
+  *                                    | (external 8 MHz xtal)                 |
+  *-------------------------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 72 / 72                               | 64 / 48
+  *-------------------------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 72 / 72                               | 64 / 48
+  *-------------------------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 36 / 36                               | 32 / 24
+  *-------------------------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 72 / 72                               | 64 / 48
+  *-------------------------------------------------------------------------------------------
   */
 
 #include "stm32f1xx.h"
@@ -95,6 +92,14 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 {
     RCC_ClkInitTypeDef RCC_ClkInitStruct;
     RCC_OscInitTypeDef RCC_OscInitStruct;
+#if (DEVICE_USBDEVICE)
+    RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;
+#endif /* DEVICE_USBDEVICE */
+
+    // Select HSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
 
     /* Enable HSE oscillator and activate PLL with HSE as source */
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
@@ -121,6 +126,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
         return 0; // FAIL
     }
 
+#if (DEVICE_USBDEVICE)
+    /* USB clock selection */
+    RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);
+#endif /* DEVICE_USBDEVICE */
+
     /* Output clock on MCO1 pin(PA8) for debugging purpose */
     //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
 
@@ -136,6 +148,9 @@ uint8_t SetSysClock_PLL_HSI(void)
 {
     RCC_ClkInitTypeDef RCC_ClkInitStruct;
     RCC_OscInitTypeDef RCC_OscInitStruct;
+#if (DEVICE_USBDEVICE)
+    RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;
+#endif /* DEVICE_USBDEVICE */
 
     /* Enable HSI oscillator and activate PLL with HSI as source */
     RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
@@ -144,11 +159,22 @@ uint8_t SetSysClock_PLL_HSI(void)
     RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
     RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
+#if (DEVICE_USBDEVICE)
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL12; // 48 MHz (8 MHz/2 * 12)
+#else /* DEVICE_USBDEVICE */
     RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
+#endif /* DEVICE_USBDEVICE */
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         return 0; // FAIL
     }
 
+#if (DEVICE_USBDEVICE)
+    /* USB clock selection */
+    RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+    HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);
+#endif /* DEVICE_USBDEVICE */
+
     /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
     RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
     RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
diff --git a/targets/TARGET_STM/USBPhyHw.h b/targets/TARGET_STM/USBPhyHw.h
index 57597fad3d8..a7eca4adb83 100644
--- a/targets/TARGET_STM/USBPhyHw.h
+++ b/targets/TARGET_STM/USBPhyHw.h
@@ -36,7 +36,7 @@
 
 #if MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG
 
-#if defined(TARGET_STM32F3) || defined(TARGET_STM32WB)
+#if defined(TARGET_STM32F1) || defined(TARGET_STM32F3) || defined(TARGET_STM32WB)
 #define USBHAL_IRQn  USB_LP_IRQn
 #else
 #define USBHAL_IRQn  USB_IRQn