STM32L4 update drivers version to CUBE V1.16.0

targets/TARGET_STM/README.md

@@ -72,7 +72,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br
 | H7          |    1.7.0     | https://github.com/STMicroelectronics/STM32CubeH7 |
 | L0          |    1.11.3    | https://github.com/STMicroelectronics/STM32CubeL0 |
 | L1          |    1.8.1     | https://github.com/STMicroelectronics/STM32CubeL1 |
-| L4          |    1.14.0    | https://github.com/STMicroelectronics/STM32CubeL4 |
+| L4          |    1.16.0    | https://github.com/STMicroelectronics/STM32CubeL4 |
 | L5          |    1.3.0     | https://github.com/STMicroelectronics/STM32CubeL5 |
 | WB          |    1.8.0     | https://github.com/STMicroelectronics/STM32CubeWB |
 

targets/TARGET_STM/TARGET_STM32L4/PeripheralNames.h

@@ -0,0 +1,149 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016-2020 STMicroelectronics
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+#if defined ADC2_BASE
+    ADC_2 = (int)ADC2_BASE,
+#endif
+#if defined ADC3_BASE
+    ADC_3 = (int)ADC3_BASE,
+#endif
+} ADCName;
+
+#if defined DAC_BASE
+typedef enum {
+    DAC_1 = (int)DAC_BASE,
+} DACName;
+#endif
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+#if defined USART3_BASE
+    UART_3 = (int)USART3_BASE,
+#endif
+#if defined UART4_BASE
+    UART_4 = (int)UART4_BASE,
+#endif
+#if defined UART5_BASE
+    UART_5 = (int)UART5_BASE,
+#endif
+    LPUART_1 = (int)LPUART1_BASE,
+} UARTName;
+
+#define DEVICE_SPI_COUNT 3
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+#if defined SPI2_BASE
+    SPI_2 = (int)SPI2_BASE,
+#endif
+#if defined SPI3_BASE
+    SPI_3 = (int)SPI3_BASE,
+#endif
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+#if defined I2C2_BASE
+    I2C_2 = (int)I2C2_BASE,
+#endif
+    I2C_3 = (int)I2C3_BASE,
+#if defined I2C4_BASE
+    I2C_4 = (int)I2C4_BASE,
+#endif
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+#if defined TIM3_BASE
+    PWM_3  = (int)TIM3_BASE,
+#endif
+#if defined TIM4_BASE
+    PWM_4  = (int)TIM4_BASE,
+#endif
+#if defined TIM5_BASE
+    PWM_5  = (int)TIM5_BASE,
+#endif
+#if defined TIM8_BASE
+    PWM_8  = (int)TIM8_BASE,
+#endif
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+#if defined TIM17_BASE
+    PWM_17 = (int)TIM17_BASE,
+#endif
+} PWMName;
+
+#if defined CAN1_BASE
+typedef enum {
+    CAN_1 = (int)CAN1_BASE,
+#if defined CAN2_BASE
+    CAN_2 = (int)CAN2_BASE,
+#endif
+} CANName;
+#endif
+
+#if defined QSPI_R_BASE || defined OCTOSPI1_R_BASE
+typedef enum {
+#if defined QSPI_R_BASE
+    QSPI_1 = (int)QSPI_R_BASE,
+#endif
+#if defined OCTOSPI1_R_BASE
+    QSPI_1 = (int)OCTOSPI1_R_BASE,
+#endif
+#if defined OCTOSPI2_R_BASE
+    QSPI_2 = (int)OCTOSPI2_R_BASE,
+#endif
+} QSPIName;
+#endif
+
+#if defined OCTOSPI1_R_BASE
+typedef enum {
+    OSPI_1 = (int)OCTOSPI1_R_BASE,
+#if defined OCTOSPI2_R_BASE
+    OSPI_2 = (int)OCTOSPI2_R_BASE,
+#endif
+} OSPIName;
+#endif
+
+#if defined USB_OTG_FS_PERIPH_BASE || defined USB_BASE
+typedef enum {
+#if defined USB_OTG_FS_PERIPH_BASE
+    USB_FS = (int)USB_OTG_FS_PERIPH_BASE,
+#endif
+#if defined USB_BASE
+    USB_FS = (int)USB_BASE,
+#endif
+} USBName;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/stm32l432xx.h → targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l432xx.h

@@ -15,10 +15,10 @@
   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -913,7 +913,9 @@ typedef struct
   * @{
   */
 #define FLASH_BASE            (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
-#define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
+#define FLASH_END             (0x0803FFFFUL) /*!< FLASH END address                */
+#define FLASH_BANK1_END       (0x0803FFFFUL) /*!< FLASH END address of bank1       */
+#define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 48 KB) base address  */
 #define SRAM2_BASE            (0x10000000UL) /*!< SRAM2(16 KB) base address */
 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
 #define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
@@ -929,6 +931,11 @@ typedef struct
 #define SRAM1_SIZE_MAX        (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
 #define SRAM2_SIZE            (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
 
+#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
+
+#define FLASH_SIZE               (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
+                                  (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
+
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE        PERIPH_BASE
 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
@@ -1046,7 +1053,6 @@ typedef struct
 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
-// #define CAN                 ((CAN_TypeDef *) CAN1_BASE) // MBED
 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
 #define USB                 ((USB_TypeDef *) USB_BASE)
 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
@@ -5700,6 +5706,13 @@ typedef struct
 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
 #define CRS_CR_TRIM_Pos           (8U)
 #define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
+#define CRS_CR_TRIM_0             (0x01UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000100 */
+#define CRS_CR_TRIM_1             (0x02UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000200 */
+#define CRS_CR_TRIM_2             (0x04UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000400 */
+#define CRS_CR_TRIM_3             (0x08UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000800 */
+#define CRS_CR_TRIM_4             (0x10UL << CRS_CR_TRIM_Pos)                  /*!< 0x00001000 */
+#define CRS_CR_TRIM_5             (0x20UL << CRS_CR_TRIM_Pos)                  /*!< 0x00002000 */
 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
 
 /*******************  Bit definition for CRS_CFGR register  *********************/
@@ -8924,13 +8937,15 @@ typedef struct
 
 /*!< HSITRIM configuration */
 #define RCC_ICSCR_HSITRIM_Pos                (24U)
-#define RCC_ICSCR_HSITRIM_Msk                (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
-#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */
+#define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
@@ -9838,8 +9853,12 @@ typedef struct
 * @brief Specific device feature definitions
 */
 #define RTC_TAMPER2_SUPPORT
+
 #define RTC_WAKEUP_SUPPORT
 #define RTC_BACKUP_SUPPORT
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                32U
+
 
 /********************  Bits definition for RTC_TR register  *******************/
 #define RTC_TR_PM_Pos                  (22U)
@@ -10560,9 +10579,6 @@ typedef struct
 #define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */
 #define RTC_BKP31R                     RTC_BKP31R_Msk
 
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       32U
-
 /******************************************************************************/
 /*                                                                            */
 /*                          Serial Audio Interface                            */
@@ -14732,9 +14748,6 @@ typedef struct
                                                        ((INSTANCE) == TIM15) || \
                                                        ((INSTANCE) == TIM16))
 
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
-
 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
 

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h → targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l433xx.h

@@ -15,10 +15,10 @@
   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -971,7 +971,9 @@ typedef struct
   * @{
   */
 #define FLASH_BASE            (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
-#define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
+#define FLASH_END             (0x0803FFFFUL) /*!< FLASH END address                */
+#define FLASH_BANK1_END       (0x0803FFFFUL) /*!< FLASH END address of bank1       */
+#define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 48 KB) base address  */
 #define SRAM2_BASE            (0x10000000UL) /*!< SRAM2(16 KB) base address */
 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
 #define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
@@ -987,6 +989,11 @@ typedef struct
 #define SRAM1_SIZE_MAX        (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
 #define SRAM2_SIZE            (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
 
+#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
+
+#define FLASH_SIZE               (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
+                                  (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
+
 /*!< Peripheral memory map */
 #define APB1PERIPH_BASE        PERIPH_BASE
 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
@@ -1116,7 +1123,6 @@ typedef struct
 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
-// #define CAN                 ((CAN_TypeDef *) CAN1_BASE) // MBED
 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
 #define USB                 ((USB_TypeDef *) USB_BASE)
 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
@@ -5774,6 +5780,13 @@ typedef struct
 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
 #define CRS_CR_TRIM_Pos           (8U)
 #define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
+#define CRS_CR_TRIM_0             (0x01UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000100 */
+#define CRS_CR_TRIM_1             (0x02UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000200 */
+#define CRS_CR_TRIM_2             (0x04UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000400 */
+#define CRS_CR_TRIM_3             (0x08UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000800 */
+#define CRS_CR_TRIM_4             (0x10UL << CRS_CR_TRIM_Pos)                  /*!< 0x00001000 */
+#define CRS_CR_TRIM_5             (0x20UL << CRS_CR_TRIM_Pos)                  /*!< 0x00002000 */
 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
 
 /*******************  Bit definition for CRS_CFGR register  *********************/
@@ -9355,13 +9368,15 @@ typedef struct
 
 /*!< HSITRIM configuration */
 #define RCC_ICSCR_HSITRIM_Pos                (24U)
-#define RCC_ICSCR_HSITRIM_Msk                (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
-#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */
+#define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
 
 /********************  Bit definition for RCC_CFGR register  ******************/
 /*!< SW configuration */
@@ -10346,8 +10361,12 @@ typedef struct
 #define RTC_TAMPER1_SUPPORT
 #define RTC_TAMPER2_SUPPORT
 #define RTC_TAMPER3_SUPPORT
+
 #define RTC_WAKEUP_SUPPORT
 #define RTC_BACKUP_SUPPORT
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                32U
+
 
 /********************  Bits definition for RTC_TR register  *******************/
 #define RTC_TR_PM_Pos                  (22U)
@@ -11104,9 +11123,6 @@ typedef struct
 #define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */
 #define RTC_BKP31R                     RTC_BKP31R_Msk
 
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       32U
-
 /******************************************************************************/
 /*                                                                            */
 /*                          Serial Audio Interface                            */
@@ -15826,9 +15842,6 @@ typedef struct
                                                        ((INSTANCE) == TIM15) || \
                                                        ((INSTANCE) == TIM16))
 
-/****************** TIM Instances : supporting synchronization ****************/
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
-
 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)