diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32G4/PeripheralNames.h similarity index 60% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/PeripheralNames.h rename to targets/TARGET_STM/TARGET_STM32G4/PeripheralNames.h index 48358111648..348507996bd 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32G4/PeripheralNames.h @@ -1,19 +1,18 @@ /* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ + #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H @@ -26,17 +25,26 @@ extern "C" { typedef enum { ADC_1 = (int)ADC1_BASE, ADC_2 = (int)ADC2_BASE, +#if defined ADC3_BASE ADC_3 = (int)ADC3_BASE, +#endif +#if defined ADC4_BASE ADC_4 = (int)ADC4_BASE, - ADC_5 = (int)ADC5_BASE +#endif +#if defined ADC5_BASE + ADC_5 = (int)ADC5_BASE, +#endif } ADCName; typedef enum { DAC_1 = (int)DAC1_BASE, +#if defined DAC2_BASE DAC_2 = (int)DAC2_BASE, +#endif DAC_3 = (int)DAC3_BASE, +#if defined DAC4_BASE DAC_4 = (int)DAC4_BASE, - +#endif } DACName; typedef enum { @@ -44,7 +52,9 @@ typedef enum { UART_2 = (int)USART2_BASE, UART_3 = (int)USART3_BASE, UART_4 = (int)UART4_BASE, +#if defined UART5_BASE UART_5 = (int)UART5_BASE, +#endif LPUART_1 = (int)LPUART1_BASE } UARTName; @@ -53,14 +63,18 @@ typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, SPI_3 = (int)SPI3_BASE, +#if defined SPI4_BASE SPI_4 = (int)SPI4_BASE, +#endif } SPIName; typedef enum { I2C_1 = (int)I2C1_BASE, I2C_2 = (int)I2C2_BASE, I2C_3 = (int)I2C3_BASE, +#if defined I2C4_BASE I2C_4 = (int)I2C4_BASE +#endif } I2CName; typedef enum { @@ -68,25 +82,35 @@ typedef enum { PWM_2 = (int)TIM2_BASE, PWM_3 = (int)TIM3_BASE, PWM_4 = (int)TIM4_BASE, +#if defined TIM5_BASE PWM_5 = (int)TIM5_BASE, +#endif PWM_6 = (int)TIM6_BASE, PWM_7 = (int)TIM7_BASE, PWM_8 = (int)TIM8_BASE, PWM_15 = (int)TIM15_BASE, PWM_16 = (int)TIM16_BASE, PWM_17 = (int)TIM17_BASE, - PWM_20 = (int)TIM20_BASE +#if defined TIM20_BASE + PWM_20 = (int)TIM20_BASE, +#endif } PWMName; typedef enum { CAN_1 = (int)FDCAN1_BASE, +#if defined FDCAN2_BASE CAN_2 = (int)FDCAN2_BASE, - CAN_3 = (int)FDCAN3_BASE +#endif +#if defined FDCAN3_BASE + CAN_3 = (int)FDCAN3_BASE, +#endif } CANName; +#if defined QSPI_R_BASE typedef enum { QSPI_1 = (int)QSPI_R_BASE, } QSPIName; +#endif typedef enum { USB_FS = (int)USB_BASE diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g431xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g431xx.h index dd24805764f..100406bf348 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g431xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g431xx.h @@ -1438,10 +1438,6 @@ typedef struct #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ -#define ADC_CFGR2_LFTRIG_Pos (29U) -#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ -#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ - /******************** Bit definition for ADC_SMPR1 register *****************/ #define ADC_SMPR1_SMP0_Pos (0U) #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ @@ -2228,11 +2224,11 @@ typedef struct #define COMP_CSR_BRGEN_Pos (22U) #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ -#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ #define COMP_CSR_SCALEN_Pos (23U) #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ -#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ #define COMP_CSR_VALUE_Pos (30U) #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ @@ -2303,7 +2299,6 @@ typedef struct #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ - /******************************************************************************/ /* */ /* CRC calculation unit */ @@ -2452,9 +2447,9 @@ typedef struct /* */ /******************************************************************************/ /* - * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) */ - #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) @@ -2658,7 +2653,6 @@ typedef struct #define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g491xx + * @{ + */ + +#ifndef __STM32G491xx_H +#define __STM32G491xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_IRQn = 65, /*!< COMP4 */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */ + FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ + DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ + DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(16 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00004000UL) /*!< CCMSRAM size (16 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) +#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) +#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g4a1xx + * @{ + */ + +#ifndef __STM32G4A1xx_H +#define __STM32G4A1xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32G4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers ***************************************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB HP Interrupt */ + USB_LP_IRQn = 20, /*!< USB LP Interrupt */ + FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ + FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupts */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ + COMP4_IRQn = 65, /*!< COMP4 */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + AES_IRQn = 85, /*!< AES global interrupt */ + FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */ + FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */ + RNG_IRQn = 90, /*!< RNG global interrupt */ + LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ + I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ + I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ + DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ + DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ + DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ + DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ + DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */ + CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ + FMAC_IRQn = 101 /*!< FMAC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32g4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ + +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ +} FDCAN_Config_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[2]; + __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ + __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ + __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ +} OPAMP_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ + __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +/* +* @brief Specific device feature definitions +*/ +#define RTC_TAMP_INT_6_SUPPORT +#define RTC_TAMP_INT_NB 4u + +#define RTC_TAMP_NB 3u +#define RTC_BACKUP_NB 32u + + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief CORDIC + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief UCPD + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */ +#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ +#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(16 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */ +#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */ +#define CCMSRAM_SIZE (0x00004000UL) /*!< CCMSRAM size (16 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) +#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ +#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) +#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) +#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) +#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) +#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) +#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL) + +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) +#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL) +#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL) + +#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) +#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) +#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP4 ((COMP_TypeDef *) COMP4_BASE) + +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) +#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE) + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC3 ((DAC_TypeDef *) DAC3_BASE) +#define AES ((AES_TypeDef *) AES_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) + +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_GCOMP register *****************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_VSENSESEL_Pos (23U) +#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATSEL_Pos (24U) +#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ + +#define COMP_CSR_BLANKING_Pos (19U) +#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ +#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ + +#define COMP_CSR_BRGEN_Pos (22U) +#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */ + +#define COMP_CSR_SCALEN_Pos (23U) +#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ +#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ + +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ + +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ + +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ + +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_HFSEL_Pos (15U) +#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ +#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! 0U) #elif (CCMSRAM_SIZE == 0x00002800UL) #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU)) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.c index 191cfc8bd7a..1c05daeab9a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.c @@ -3,7 +3,7 @@ * @file stm32g4xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) + * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Initialization and de-initialization functions * ++ Initialization and Configuration of ADC @@ -325,9 +325,9 @@ #define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\ ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ - ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated + ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ - + /* Timeout values for ADC operations (enable settling time, */ /* disable settling time, ...). */ /* Values defined to be higher than worst cases: low clock frequency, */ @@ -2158,7 +2158,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { - /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); /* Disable the DMA channel (in case of DMA in circular mode or stop */ @@ -2972,7 +2972,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". - * @note On this STM32 serie, analog watchdog thresholds can be modified + * @note On this STM32 series, analog watchdog thresholds can be modified * while ADC conversion is on going. * In this case, some constraints must be taken into account: * the programmed threshold values are effective from the next diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.h index d0e4817acfe..30160c3ad74 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.h @@ -113,7 +113,7 @@ typedef struct 0 Gain compensation will be disabled and coefficient set to 0 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value - Note: Gain compensation when enabled is appied to all channels. */ + Note: Gain compensation when enabled is applied to all channels. */ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. @@ -132,8 +132,8 @@ typedef struct This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. - Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag - to free the IRQ vector sequencer. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ @@ -251,7 +251,7 @@ typedef struct Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - uint32_t OffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data. + uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ @@ -357,7 +357,7 @@ typedef struct external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, @@ -499,7 +499,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ @@ -666,17 +666,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ -#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 serie, ADC channel available on all instances but ADC2. */ -#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC1 instance. */ -#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ -#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 serie, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ -#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 serie, ADC channel available only on ADC1 instance. */ -#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 serie, ADC channel available only on ADC2 instance. */ -#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC2 instance. */ -#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ -#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ -#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ -#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 serie, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ +#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ +#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ +#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ +#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ +#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ +#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */ +#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */ /** * @} */ @@ -988,22 +988,22 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32G473xx) || defined(STM32G483xx) @@ -1023,20 +1023,20 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32G471xx) @@ -1053,18 +1053,18 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ ((((__HANDLE__)->Instance == ADC3)) && \ - (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) @@ -1087,6 +1087,39 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \ + ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \ + (((__HANDLE__)->Instance == ADC3) && \ + (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ + ((__REGTRIG__) == ADC_SOFTWARE_START) ) #endif /** @@ -1369,7 +1402,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 @@ -1423,7 +1456,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -1489,7 +1522,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). @@ -1550,7 +1583,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: @@ -1611,7 +1644,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ @@ -1743,7 +1776,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. - * @note On this STM32 serie, calibration data of internal voltage reference + * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. @@ -1790,7 +1823,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 serie, calibration data of temperature sensor + * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.c index d2eb69033eb..65d3983ef7a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.c @@ -3,7 +3,7 @@ * @file stm32g4xx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) + * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Operation functions * ++ Start, stop, get result of conversions of ADC group injected, diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.h index 68e31bee859..d23015b69c2 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.h @@ -114,7 +114,7 @@ typedef struct Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ - uint32_t InjectedOffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data. + uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. @@ -293,7 +293,7 @@ typedef struct /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign * @{ */ -#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is substracted */ +#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ #define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ /** * @} @@ -429,7 +429,7 @@ typedef struct * Usage of this macro is not the Standard way of multimode * configuration and can lead to have HAL ADC handles status * misaligned. Usage of this macro must be limited to cases - * mentionned above. + * mentioned above. * @param __HANDLE__ ADC handle. * @retval None */ @@ -468,9 +468,17 @@ typedef struct #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC5) \ )? \ - SET \ - : \ - RESET \ + SET \ + : \ + RESET \ + ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define ADC_IS_INDEPENDENT(__HANDLE__) \ + ( ( ( ((__HANDLE__)->Instance) == ADC3) \ + )? \ + SET \ + : \ + RESET \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) @@ -624,7 +632,7 @@ typedef struct : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. @@ -648,7 +656,7 @@ typedef struct */ #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif @@ -661,6 +669,8 @@ typedef struct #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif /** @@ -798,6 +808,36 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ ((__CHANNEL__) == ADC_CHANNEL_17) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ + ((__CHANNEL__) == ADC_CHANNEL_2) || \ + ((__CHANNEL__) == ADC_CHANNEL_3) || \ + ((__CHANNEL__) == ADC_CHANNEL_4) || \ + ((__CHANNEL__) == ADC_CHANNEL_5) || \ + ((__CHANNEL__) == ADC_CHANNEL_6) || \ + ((__CHANNEL__) == ADC_CHANNEL_7) || \ + ((__CHANNEL__) == ADC_CHANNEL_8) || \ + ((__CHANNEL__) == ADC_CHANNEL_9) || \ + ((__CHANNEL__) == ADC_CHANNEL_10) || \ + ((__CHANNEL__) == ADC_CHANNEL_11) || \ + ((__CHANNEL__) == ADC_CHANNEL_12) || \ + ((__CHANNEL__) == ADC_CHANNEL_14) || \ + ((__CHANNEL__) == ADC_CHANNEL_15)) || \ + ((((__HANDLE__)->Instance) == ADC1) && \ + (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \ + ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \ + ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \ + ((((__HANDLE__)->Instance) == ADC2) && \ + (((__CHANNEL__) == ADC_CHANNEL_13) || \ + ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \ + ((__CHANNEL__) == ADC_CHANNEL_17) || \ + ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \ + ((((__HANDLE__)->Instance) == ADC3) && \ + (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \ + ((__CHANNEL__) == ADC_CHANNEL_16) || \ + ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ + ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) #endif /** @@ -845,7 +885,7 @@ typedef struct (((__CHANNEL__) == ADC_CHANNEL_12) || \ ((__CHANNEL__) == ADC_CHANNEL_13) || \ ((__CHANNEL__) == ADC_CHANNEL_15))) ) -#elif defined(STM32G471xx) +#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ (((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -949,21 +989,21 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32G473xx) || defined(STM32G483xx) @@ -983,19 +1023,19 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32G471xx) @@ -1013,17 +1053,17 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ ((((__HANDLE__)->Instance == ADC3)) && \ - (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) @@ -1047,6 +1087,38 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \ + ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \ + (((__HANDLE__)->Instance == ADC3) && \ + (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ + ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) #endif /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_comp.c index b31c0dbf03f..3403c7b8369 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_comp.c @@ -86,11 +86,11 @@ The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_COMP_RegisterCallback() + Use Functions HAL_COMP_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks: + Function HAL_COMP_RegisterCallback() allows to register following callbacks: (+) TriggerCallback : callback for COMP trigger. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. @@ -98,11 +98,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default + Use function HAL_COMP_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TriggerCallback : callback for COMP trigger. @@ -110,27 +110,27 @@ (+) MspDeInitCallback : callback for Msp DeInit. [..] - By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET + By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET all callbacks are set to the corresponding weak functions: - example @ref HAL_COMP_TriggerCallback(). + example HAL_COMP_TriggerCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when + reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() + If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state, + in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit() - or @ref HAL_COMP_Init() function. + using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit() + or HAL_COMP_Init() function. [..] When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or @@ -997,7 +997,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) /** * @brief Return the output level (high or low) of the selected comparator. - * On this STM32 serie, comparator 'value' is taken before + * On this STM32 series, comparator 'value' is taken before * polarity and blanking are applied, thus: * - Comparator output is low when the input plus is at a lower * voltage than the input minus diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_comp.h index 70796bc260a..acec600ad86 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_comp.h @@ -1004,7 +1004,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer :((__INSTANCE__) == COMP5) ? COMP_EXTI_LINE_COMP5 \ :((__INSTANCE__) == COMP6) ? COMP_EXTI_LINE_COMP6 \ : COMP_EXTI_LINE_COMP7) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \ :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \ @@ -1014,7 +1014,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @} */ -/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters +/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters * @{ */ #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \ @@ -1055,7 +1055,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \ )) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ @@ -1219,6 +1219,39 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ + || \ + (((__INSTANCE__) == COMP3) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ + || \ + (((__INSTANCE__) == COMP4) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + ) #endif #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.c index 65b063d0c80..5397c4ca454 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.c @@ -139,6 +139,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" +#if defined(CORDIC) #ifdef HAL_CORDIC_MODULE_ENABLED /** @addtogroup STM32G4xx_HAL_Driver @@ -1337,7 +1338,6 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma) * @} */ -#endif /* HAL_CORDIC_MODULE_ENABLED */ /** * @} */ @@ -1346,4 +1346,7 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma) * @} */ +#endif /* HAL_CORDIC_MODULE_ENABLED */ +#endif /* CORDIC */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.h index 64a3543deb5..53eacadab72 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.h @@ -29,6 +29,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" +#if defined(CORDIC) /** @addtogroup STM32G4xx_HAL_Driver * @{ */ @@ -267,7 +268,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data ouput (Q1.31 format), or two 16-bit + 32-bit data output (Q1.31 format), or two 16-bit data output (Q1.15 format) packed in one 32 bits Data */ #define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output (Q1.31 format) */ @@ -587,6 +588,8 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic); * @} */ +#endif /* CORDIC */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_crc_ex.c index 652e78f1ab1..ee994e40d51 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_crc_ex.c @@ -11,7 +11,7 @@ ##### How to use this driver ##### ================================================================================ [..] - (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set() + (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() (+) Configure Input or Output data inversion @endverbatim diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.c index f5bd6af3d17..b815b7086bc 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.c @@ -155,83 +155,24 @@ (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. (#) structure of message construction in GCM is defined as below : (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter - - ICB - +-------------------------------------------------------+ - | Initialization vector (IV) | Counter | - |----------------|----------------|-----------|---------| - 127 95 63 31 0 - - - Bit Number Register Contents - ---------- --------------- ----------- - 127 ...96 CRYP_IV1R[31:0] ICB[127:96] - 95 ...64 CRYP_IV1L[31:0] B0[95:64] - 63 ... 32 CRYP_IV0R[31:0] ICB[63:32] - 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2 - - - (##) The authenticated header A (also knows as Additional Authentication Data AAD) this part of the message is only authenticated, not encrypted. (##) The plaintext message P is both authenticated and encrypted as ciphertext. GCM standard specifies that ciphertext has same bit length as the plaintext. (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext (on 64 bits) - GCM last block definition - +-------------------------------------------------------------------+ - | Bit[0] | Bit[32] | Bit[64] | Bit[96] | - |-----------|--------------------|-----------|----------------------| - | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] | - |-----------|--------------------|-----------|----------------------| + + [..] A more detailed description of the GCM message structure is available below. [..] This section describe The AES Counter with Cipher Block Chaining-Message Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral: (#) Specific parameters for CCM : - (##) B0 block : According to NIST Special Publication 800-38C, - The first block B0 is formatted as follows, where l(m) is encoded in - most-significant-byte first order: - - Octet Number Contents - ------------ --------- - 0 Flags - 1 ... 15-q Nonce N - 16-q ... 15 Q - - the Flags field is formatted as follows: - - Bit Number Contents - ---------- ---------------------- - 7 Reserved (always zero) - 6 Adata - 5 ... 3 (t-2)/2 - 2 ... 0 [q-1]3 - - - Q: a bit string representation of the octet length of P (plaintext) - - q The octet length of the binary representation of the octet length of the payload - - A nonce (N), n The octet length of the where n+q=15. - - Flags: most significant octet containing four flags for control information, - - t The octet length of the MAC. - (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A) - the associated data length expressed in bytes (a) defined as below: - - If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets - - If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets - - If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets + (##) B0 block : follows NIST Special Publication 800-38C, + (##) B1 block (header) (##) CTRx block : control blocks - - Generation of CTR1 from first block B0 information : - equal to B0 with first 5 bits zeroed and most significant bits storing octet - length of P also zeroed, then incremented by one - - Bit Number Register Contents - ---------- --------------- ----------- - 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for - bit 0 that is set to 1 - 95 ...64 CRYP_IV1L[31:0] B0[95:64] - 63 ... 32 CRYP_IV0R[31:0] B0[63:32] - 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0 - - Generation of CTR0: same as CTR1 with bit[0] set to zero. + [..] A detailed description of the CCM message structure is available below. (#) Four phases are performed in CCM for CRYP1 peripheral: (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing @@ -981,11 +922,15 @@ void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp) */ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) { + HAL_CRYP_STATETypeDef state; + /* Request suspension */ HAL_CRYP_ProcessSuspend(hcryp); - while ((HAL_CRYP_GetState(hcryp) != HAL_CRYP_STATE_SUSPENDED) && \ - (HAL_CRYP_GetState(hcryp) != HAL_CRYP_STATE_READY)); + do + { + state = HAL_CRYP_GetState(hcryp); + } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY)); if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY) { @@ -1019,7 +964,8 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) hcryp->CrypOutCount_saved = hcryp->CrypOutCount; hcryp->Phase_saved = hcryp->Phase; hcryp->State_saved = hcryp->State; - hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? hcryp->Size /4 : hcryp->Size); + hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size); + hcryp->SizesSum_saved = hcryp->SizesSum; hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation; hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount; hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; @@ -1049,6 +995,12 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) */ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) { + /* Check the CRYP handle allocation */ + if (hcryp == NULL) + { + return HAL_ERROR; + } + if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED) { /* CRYP was not suspended */ @@ -1075,16 +1027,14 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) hcryp->Init.pInitVect = hcryp->IV_saved; } __HAL_CRYP_DISABLE(hcryp); - if (HAL_CRYP_Init(hcryp) != HAL_OK) - { - return HAL_ERROR; - } + (void) HAL_CRYP_Init(hcryp); } else /* Authentication algorithms case */ { /* Restore low-priority block CRYP handle parameters */ hcryp->Phase = hcryp->Phase_saved; hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved; + hcryp->SizesSum = hcryp->SizesSum_saved; /* Disable AES and write-back SUSPxR registers */; __HAL_CRYP_DISABLE(hcryp); @@ -1094,8 +1044,6 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) hcryp->Instance->CR = hcryp->CR_saved; CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved); - __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE); - __HAL_CRYP_ENABLE(hcryp); /* At the same time, set handle state back to READY to be able to resume the AES calculations without the processing APIs returning HAL_BUSY when called. */ @@ -1157,6 +1105,81 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) * @{ */ +/* GCM message structure additional details + + ICB + +-------------------------------------------------------+ + | Initialization vector (IV) | Counter | + |----------------|----------------|-----------|---------| + 127 95 63 31 0 + + + Bit Number Register Contents + ---------- --------------- ----------- + 127 ...96 CRYP_IV1R[31:0] ICB[127:96] + 95 ...64 CRYP_IV1L[31:0] B0[95:64] + 63 ... 32 CRYP_IV0R[31:0] ICB[63:32] + 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2 + + + + GCM last block definition + +-------------------------------------------------------------------+ + | Bit[0] | Bit[32] | Bit[64] | Bit[96] | + |-----------|--------------------|-----------|----------------------| + | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] | + |-----------|--------------------|-----------|----------------------| + +*/ + +/* CCM message blocks description + + (##) B0 block : According to NIST Special Publication 800-38C, + The first block B0 is formatted as follows, where l(m) is encoded in + most-significant-byte first order: + + Octet Number Contents + ------------ --------- + 0 Flags + 1 ... 15-q Nonce N + 16-q ... 15 Q + + the Flags field is formatted as follows: + + Bit Number Contents + ---------- ---------------------- + 7 Reserved (always zero) + 6 Adata + 5 ... 3 (t-2)/2 + 2 ... 0 [q-1]3 + + - Q: a bit string representation of the octet length of P (plaintext) + - q The octet length of the binary representation of the octet length of the payload + - A nonce (N), n The octet length of the where n+q=15. + - Flags: most significant octet containing four flags for control information, + - t The octet length of the MAC. + (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A) + the associated data length expressed in bytes (a) defined as below: + - If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets + - If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets + - If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets + (##) CTRx block : control blocks + - Generation of CTR1 from first block B0 information : + equal to B0 with first 5 bits zeroed and most significant bits storing octet + length of P also zeroed, then incremented by one + + Bit Number Register Contents + ---------- --------------- ----------- + 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for + bit 0 that is set to 1 + 95 ...64 CRYP_IV1L[31:0] B0[95:64] + 63 ... 32 CRYP_IV0R[31:0] B0[63:32] + 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0 + + - Generation of CTR0: same as CTR1 with bit[0] set to zero. + +*/ + /** * @brief Encryption mode. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -1171,6 +1194,12 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u { uint32_t algo; HAL_StatusTypeDef status; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1265,6 +1294,12 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u { HAL_StatusTypeDef status; uint32_t algo; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1358,6 +1393,12 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input { HAL_StatusTypeDef status; uint32_t algo; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1374,8 +1415,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input hcryp->ResumingFlag = 0U; if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) { - hcryp->CrypInCount = hcryp->CrypInCount_saved; - hcryp->CrypOutCount = hcryp->CrypOutCount_saved; + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; } else { @@ -1462,6 +1503,12 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input { HAL_StatusTypeDef status; uint32_t algo; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1478,8 +1525,8 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input hcryp->ResumingFlag = 0U; if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) { - hcryp->CrypInCount = hcryp->CrypInCount_saved; - hcryp->CrypOutCount = hcryp->CrypOutCount_saved; + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; } else { @@ -1566,6 +1613,12 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu HAL_StatusTypeDef status; uint32_t algo; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1686,6 +1739,12 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu { HAL_StatusTypeDef status; uint32_t algo; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -2684,7 +2743,8 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; /* Write the input block in the IN FIFO */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); @@ -2721,19 +2781,17 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i= 0U; + while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } } /** @@ -2746,24 +2804,23 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) */ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; if (hcryp->State == HAL_CRYP_STATE_BUSY) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i= 0U; + while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } if (hcryp->CrypOutCount == (hcryp->Size / 4U)) { /* Disable Computation Complete flag and errors interrupts */ @@ -2900,7 +2957,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t tickstart; uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ; uint32_t npblb; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t index; uint32_t lastwordsize; uint32_t incount; /* Temporary CrypInCount Value */ @@ -3079,9 +3136,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t for (index = 0U; index < 4U; index++) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; - - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + temp[index] = hcryp->Instance->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; hcryp->CrypOutCount++; } } @@ -3428,7 +3487,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) uint32_t index; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) @@ -3608,9 +3667,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) for (index = 0U; index < 4U; index++) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; - - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + temp[index] = hcryp->Instance->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; hcryp->CrypOutCount++; } @@ -3641,7 +3702,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t loopcounter; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4] ; /* Temporary CrypOutBuff */ uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ @@ -3813,9 +3874,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t for (loopcounter = 0U; loopcounter < 4U; loopcounter++) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; - - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + temp[loopcounter] = hcryp->Instance->DOUTR; + } + for (loopcounter = 0U; loopcounterpCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; hcryp->CrypOutCount++; } } @@ -4138,7 +4201,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) uint32_t index; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) @@ -4317,9 +4380,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) for (index = 0U; index < 4U; index++) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; - - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + temp[index] = hcryp->Instance->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; hcryp->CrypOutCount++; } @@ -4343,29 +4408,28 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { uint32_t loopcounter; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; uint32_t mode; uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t i; /***************************** Payload phase *******************************/ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i= 0U; + while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } incount = hcryp->CrypInCount; outcount = hcryp->CrypOutCount; if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) @@ -4491,10 +4555,21 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t loopcounter; + uint32_t size_in_bytes; + uint32_t tmp; + uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; /***************************** Header phase for GCM/GMAC or CCM *********************************/ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + size_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + size_in_bytes = hcryp->Init.HeaderSize; + } - if ((hcryp->Init.HeaderSize != 0U)) + if ((size_in_bytes != 0U)) { /* Select header phase */ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); @@ -4502,10 +4577,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if ((hcryp->Init.HeaderSize % 4U) == 0U) + /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */ + if ((size_in_bytes % 16U) == 0U) { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + /* No padding */ + for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U) { /* Write the input block in the data input register */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -4536,8 +4612,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + /* Write header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U) { /* Write the input block in the data input register */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -4565,17 +4641,35 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while (loopcounter < 4U) + /* If the header size is a multiple of words */ + if ((size_in_bytes % 4U) == 0U) { - /*Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeroes */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[size_in_bytes % 4U]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) @@ -5006,7 +5100,7 @@ static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Outp __IO uint32_t count = 0U; /* In case of GCM payload phase encryption, check that suspension can be carried out */ - if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0)) + if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U)) { /* Wait for BUSY flag to be cleared */ @@ -5144,21 +5238,21 @@ static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, if (KeySize == CRYP_KEYSIZE_256B) { hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr); - keyaddr+=4; + keyaddr+=4U; } hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr); - keyaddr+=4; + keyaddr+=4U; hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr); } @@ -5170,9 +5264,19 @@ static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input, */ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) { - uint32_t loopcounter = 0U; - uint32_t lastwordsize =0; - uint32_t npblb = 0U ; + uint32_t loopcounter; + uint16_t lastwordsize; + uint16_t npblb; + uint32_t cr_temp; + + + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR | CRYP_CCF_CLEAR); + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); /* Case of header phase resumption =================================================*/ if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) @@ -5183,7 +5287,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) /* Select header phase */ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U)) + if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)) { /* Write the input block in the IN FIFO */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); @@ -5212,73 +5316,77 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) } } /* Case of payload phase resumption =================================================*/ - else if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED) + else { + if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED) + { - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - if ((hcryp->Size/4) - (hcryp->CrypInCount) >= 4U) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U) { - /* Call output transfer complete callback */ + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->CrypInCount++; + if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + { + /* Call output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } - } - else /* Last block of payload < 128bit*/ - { - /* Compute the number of padding bytes in last block of payload */ - npblb = ((hcryp->Size/16U)+1U)*16U- (hcryp->Size); - if((((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || - (((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + else /* Last block of payload < 128bit*/ { - /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb<< 20U); - } + /* Compute the number of padding bytes in last block of payload */ + npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size); + cr_temp = hcryp->Instance->CR; + if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + (((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U); + } - /* Number of valid words (lastwordsize) in last block */ - if (npblb % 4U ==0U) - { - lastwordsize = (16U-npblb)/4U; - } - else - { - lastwordsize = (16U-npblb)/4U +1U; - } + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) ==0U) + { + lastwordsize = (16U-npblb)/4U; + } + else + { + lastwordsize = ((16U-npblb)/4U) +1U; + } - /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - } - while(loopcounter < 4U ) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; + /* Last block optionally pad the data with zeros*/ + for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->CrypInCount++; + } + while(loopcounter < 4U ) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } } } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.h index 0b071c21897..a9f0b2ebba2 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.h @@ -64,9 +64,10 @@ typedef struct uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data. */ - uint32_t HeaderSize; /*!< The size of header buffer in word */ + uint32_t HeaderSize; /*!< The size of header buffer */ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ - uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization Vector only once and to skip configuration for consecutive processings. This parameter can be a value of @ref CRYP_Configuration_Skip */ @@ -182,10 +183,12 @@ typedef struct uint32_t Key_saved[8]; /*!< copy of key registers */ - uint32_t Size_saved; /*!< copy of input buffer size */ + uint16_t Size_saved; /*!< copy of input buffer size */ uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */ + uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */ + uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */ FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */ @@ -259,6 +262,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point #define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ #define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */ +/** + * @} + */ + +/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit + * @{ + */ + +#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */ +#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */ + /** * @} */ @@ -565,6 +579,13 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); #define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) +#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \ + (((((ALGO) == CRYP_AES_CTR)) && \ + ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ + (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ + (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ + ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp_ex.c index 86878892610..100d7b530cf 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp_ex.c @@ -99,10 +99,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) { uint32_t tickstart; + /* Assume first Init.HeaderSize is in words */ uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */ - uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */ + uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */ uint32_t tagaddr = (uint32_t)AuthTag; + /* Correct headerlength if Init.HeaderSize is actually in bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE) + { + headerlength /= 4U; + } + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Process locked */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.c index 377d0b88eb9..1d95fd71a19 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.c @@ -41,7 +41,7 @@ Channel 2 | | YES | NO | YES | YES | DAC_OUT2 | PA5 | - | - | - ---------------------------------------------------------------------------- - Note: On this STM32 serie, all devices do not include each DAC instances listed + Note: On this STM32 series, all devices do not include each DAC instances listed above. Refer to device datasheet for DACx instance availability. *** DAC Triggers *** @@ -70,7 +70,7 @@ (#) HRTimer Step & Reset: HRTIM1 (1) (DAC_TRIGGER_HRTIM_RST_TRG1, DAC_TRIGGER_HRTIM_STEP_TRG1...) - Note: On this STM32 serie, parameter only available if HRTIM feature is + Note: On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) *** DAC Buffer mode feature *** @@ -195,7 +195,7 @@ ---------------------------------------------------------------------------- Channel 2 | | 7 | - | 103 | 105 ---------------------------------------------------------------------------- - Note: On this STM32 serie, all devices do not include each DAC instances listed + Note: On this STM32 series, all devices do not include each DAC instances listed above. Refer to device datasheet for DACx instance availability. *** High frequency interface mode *** @@ -565,7 +565,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ @@ -623,7 +623,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ @@ -653,7 +653,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param pData The destination peripheral Buffer address. * @param Length The length of data to be transferred from memory to DAC peripheral @@ -793,7 +793,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ @@ -920,7 +920,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: @@ -1052,7 +1052,7 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval The selected DAC channel data output value. */ @@ -1087,7 +1087,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ @@ -1467,7 +1467,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.h index 455714a41a0..d6fc8a18045 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.h @@ -221,21 +221,21 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger */ #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */ -#define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */ +#define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ /** * @} @@ -400,7 +400,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -413,7 +413,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -426,7 +426,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval State of interruption (SET or RESET) */ @@ -441,7 +441,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @arg DAC_FLAG_DAC1RDY: DAC channel 1 ready status flag * @arg DAC_FLAG_DAC2RDY: DAC channel 2 ready status flag (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -454,7 +454,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.c index b7672658a5e..550f59c2745 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.c @@ -372,7 +372,7 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: @@ -424,7 +424,7 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: @@ -476,7 +476,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Polarity polarity to be used for wave generation. * This parameter can be one of the following values: @@ -549,7 +549,7 @@ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32 * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ @@ -605,7 +605,7 @@ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint3 * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval HAL status */ @@ -769,7 +769,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming * @retval HAL status @@ -904,7 +904,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param NewTrimmingValue DAC new trimming value * @retval HAL status @@ -950,7 +950,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Trimming value : range: 0->31 * diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dma.c index 94937e65838..72adf332070 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dma.c @@ -826,7 +826,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * @brief Register callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. @@ -879,7 +879,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call * @brief UnRegister callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1057,7 +1057,7 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) else { /* DMA2 */ -#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) +#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) DMAMUX1_ChannelBase = DMAMUX1_Channel8; #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) DMAMUX1_ChannelBase = DMAMUX1_Channel6; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fdcan.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fdcan.c index d4350b447d9..81571de6c15 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fdcan.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fdcan.c @@ -223,13 +223,17 @@ #define SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */ #define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */ -#define SRAMCAN_FLSSA ((uint32_t)0) /* Filter List Standard Start Address */ -#define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start Address */ -#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */ -#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */ -#define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start Address */ -#define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start Address */ -#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */ +#define SRAMCAN_FLSSA ((uint32_t)0) /* Filter List Standard Start + Address */ +#define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start + Address */ +#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */ +#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */ +#define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start + Address */ +#define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start + Address */ +#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */ /** * @} @@ -244,7 +248,8 @@ static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, * @{ */ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex); +static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, + uint32_t BufferIndex); /** * @} */ @@ -255,8 +260,8 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy */ /** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -323,17 +328,22 @@ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) hfdcan->Lock = HAL_UNLOCKED; /* Reset callbacks to legacy functions */ - hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ - hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ - hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ - hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ - hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback */ - hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */ - hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */ - hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */ - hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak TimeoutOccurredCallback */ - hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */ - hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak + TxBufferCompleteCallback */ + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak + TxBufferAbortCallback */ + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak + HighPriorityMessageCallback */ + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak + TimestampWraparoundCallback */ + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak + TimeoutOccurredCallback */ + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */ + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ if (hfdcan->MspInitCallback == NULL) { @@ -684,7 +694,8 @@ HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN)) +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN)) { HAL_StatusTypeDef status = HAL_OK; @@ -871,7 +882,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_ * @param pCallback pointer to the Tx Event Fifo Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxEventFifoCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -931,7 +943,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *h * @param pCallback pointer to the Rx Fifo 0 Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo0CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -991,7 +1004,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdca * @param pCallback pointer to the Rx Fifo 1 Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo1CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1051,7 +1065,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdca * @param pCallback pointer to the Tx Buffer Complete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferCompleteCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1080,7 +1095,8 @@ HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef /** * @brief UnRegister the Tx Buffer Complete FDCAN Callback - * Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback + * Tx Buffer Complete FDCAN Callback is redirected to + * the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback * @param hfdcan FDCAN handle * @retval HAL status */ @@ -1111,7 +1127,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeD * @param pCallback pointer to the Tx Buffer Abort Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferAbortCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1140,7 +1157,8 @@ HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *h /** * @brief UnRegister the Tx Buffer Abort FDCAN Callback - * Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback + * Tx Buffer Abort FDCAN Callback is redirected to + * the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback * @param hfdcan FDCAN handle * @retval HAL status */ @@ -1171,7 +1189,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef * @param pCallback pointer to the Error Status Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ErrorStatusCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1231,8 +1250,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h */ /** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions - * @brief FDCAN Configuration functions. - * + * @brief FDCAN Configuration functions. + * @verbatim ============================================================================== ##### Configuration functions ##### @@ -1377,10 +1396,10 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_RXGFC_ANFE | FDCAN_RXGFC_RRFS | FDCAN_RXGFC_RRFE), - ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) | - (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) | - (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) | - (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos))); + ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) | + (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) | + (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) | + (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos))); /* Return function status */ return HAL_OK; @@ -1631,7 +1650,8 @@ HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) * This parameter must be a number between 0x0000 and 0xFFFF * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod) +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, + uint32_t TimeoutPeriod) { /* Check function parameters */ assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation)); @@ -1640,7 +1660,8 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, ui if (hfdcan->State == HAL_FDCAN_STATE_READY) { /* Select timeout operation and configure period */ - MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos))); + MODIFY_REG(hfdcan->Instance->TOCC, + (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos))); /* Return function status */ return HAL_OK; @@ -1751,7 +1772,8 @@ HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) * This parameter must be a number between 0x00 and 0x7F. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter) +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, + uint32_t TdcFilter) { /* Check function parameters */ assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU)); @@ -1933,8 +1955,8 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) */ /** @defgroup FDCAN_Exported_Functions_Group3 Control functions - * @brief Control functions - * + * @brief Control functions + * @verbatim ============================================================================== ##### Control functions ##### @@ -1942,15 +1964,18 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) [..] This section provides functions allowing to: (+) HAL_FDCAN_Start : Start the FDCAN module (+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers - (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request + (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding + transmission request (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request (+) HAL_FDCAN_AbortTxRequest : Abort transmission request (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx FIFO zone into the message RAM - (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM + (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone + into the message RAM (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status (+) HAL_FDCAN_GetProtocolStatus : Get protocol status (+) HAL_FDCAN_GetErrorCounters : Get error counter values - (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending on the selected Tx buffer + (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending + on the selected Tx buffer (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode @@ -2079,7 +2104,8 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) * @param pTxData pointer to a buffer containing the payload of the Tx frame. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData) +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, + uint8_t *pTxData) { uint32_t PutIndex; @@ -2192,7 +2218,8 @@ HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t * @param pRxData pointer to a buffer where the payload of the Rx frame will be stored. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData) +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, + FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData) { uint32_t *RxAddress; uint8_t *pData; @@ -2403,7 +2430,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus) +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, + FDCAN_HpMsgStatusTypeDef *HpMsgStatus) { HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos); HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos); @@ -2484,7 +2512,7 @@ uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_ /* Check function parameters */ assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex)); - /* Check pending transmittion request on the selected buffer */ + /* Check pending transmission request on the selected buffer */ if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U) { return 0; @@ -2589,8 +2617,8 @@ HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfd */ /** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management - * @brief Interrupts management - * + * @brief Interrupts management + * @verbatim ============================================================================== ##### Interrupts management ##### @@ -2660,7 +2688,8 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, ui * - FDCAN_IT_TX_ABORT_COMPLETE * @retval HAL status */ -HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes) +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, + uint32_t BufferIndexes) { HAL_FDCAN_StateTypeDef state = hfdcan->State; uint32_t ITs_lines_selection; @@ -2678,24 +2707,38 @@ HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, ui ITs_lines_selection = hfdcan->Instance->ILS; /* Enable Interrupt lines */ - if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) + if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) { /* Enable Interrupt line 0 */ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); } - if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \ - (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) + if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \ + (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) { /* Enable Interrupt line 1 */ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); @@ -2704,14 +2747,14 @@ HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, ui if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U) { /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register, - but interrupt will only occure if TC is enabled in IE register */ + but interrupt will only occur if TC is enabled in IE register */ SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes); } if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) { /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register, - but interrupt will only occure if TCF is enabled in IE register */ + but interrupt will only occur if TCF is enabled in IE register */ SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes); } @@ -2769,13 +2812,20 @@ HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, ITs_lines_selection = hfdcan->Instance->ILS; /* Check if some interrupts are still enabled on interrupt line 0 */ - if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) + if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U))) { /* Do nothing */ } @@ -2786,13 +2836,20 @@ HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, } /* Check if some interrupts are still enabled on interrupt line 1 */ - if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \ - (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) + if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \ + (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) + && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U))) { /* Do nothing */ } @@ -3022,11 +3079,11 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs); #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs); + /* Call registered callback*/ + hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs); #else - /* Error Status Callback */ - HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs); + /* Error Status Callback */ + HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs); #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } @@ -3057,8 +3114,8 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) */ /** @defgroup FDCAN_Exported_Functions_Group5 Callback functions - * @brief FDCAN Callback functions - * + * @brief FDCAN Callback functions + * @verbatim ============================================================================== ##### Callback functions ##### @@ -3280,8 +3337,8 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t */ /** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions - * @brief FDCAN Peripheral State functions - * + * @brief FDCAN Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -3394,7 +3451,8 @@ static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) * @param BufferIndex index of the buffer to be configured. * @retval none */ -static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex) +static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, + uint32_t BufferIndex) { uint32_t TxElementW1; uint32_t TxElementW2; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fdcan.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fdcan.h index 4311f11d76a..ee64c99f24c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fdcan.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fdcan.h @@ -316,52 +316,53 @@ typedef struct typedef struct { uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. - This parameter can be a value of @ref FDCAN_protocol_error_code */ + This parameter can be a value of @ref FDCAN_protocol_error_code */ - uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format - frame with its BRS flag set. - This parameter can be a value of @ref FDCAN_protocol_error_code */ + uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase + of a CAN FD format frame with its BRS flag set. + This parameter can be a value of @ref FDCAN_protocol_error_code */ uint32_t Activity; /*!< Specifies the FDCAN module communication state. - This parameter can be a value of @ref FDCAN_communication_state */ + This parameter can be a value of @ref FDCAN_communication_state */ uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. This parameter can be: - 0 : The FDCAN is in Error_Active state - - 1 : The FDCAN is in Error_Passive state */ + - 1 : The FDCAN is in Error_Passive state */ uint32_t Warning; /*!< Specifies the FDCAN module warning status. This parameter can be: - - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96 - - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ + - 0 : error counters (RxErrorCnt and TxErrorCnt) + are below the Error_Warning limit of 96 + - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. This parameter can be: - 0 : The FDCAN is not in Bus_Off state - - 1 : The FDCAN is in Bus_Off state */ + - 1 : The FDCAN is in Bus_Off state */ uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. This parameter can be: - 0 : Last received CAN FD message did not have its ESI flag set - - 1 : Last received CAN FD message had its ESI flag set */ + - 1 : Last received CAN FD message had its ESI flag set */ uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. This parameter can be: - 0 : Last received CAN FD message did not have its BRS flag set - - 1 : Last received CAN FD message had its BRS flag set */ + - 1 : Last received CAN FD message had its BRS flag set */ - uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status - This parameter can be: + uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received + since last protocol status.This parameter can be: - 0 : No CAN FD message received - - 1 : CAN FD message received */ + - 1 : CAN FD message received */ uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. This parameter can be: - 0 : No protocol exception event occurred since last read access - - 1 : Protocol exception event occurred */ + - 1 : Protocol exception event occurred */ uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. - This parameter can be a number between 0 and 127 */ + This parameter can be a number between 0 and 127 */ } FDCAN_ProtocolStatusTypeDef; @@ -371,21 +372,22 @@ typedef struct typedef struct { uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. - This parameter can be a number between 0 and 255 */ + This parameter can be a number between 0 and 255 */ uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. - This parameter can be a number between 0 and 127 */ + This parameter can be a number between 0 and 127 */ uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. This parameter can be: - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 - - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */ + - 1 : The Receive Error Counter (RxErrorCnt) + has reached the error passive level of 128 */ uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. This parameter can be a number between 0 and 255. This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of - TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ + TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ } FDCAN_ErrorCountersTypeDef; @@ -795,21 +797,21 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, * @{ */ #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ -#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */ -#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */ -#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */ -#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */ -#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */ -#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */ -#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */ -#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */ -#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */ -#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */ -#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */ -#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */ -#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */ -#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */ -#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */ +#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ +#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ +#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ +#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ +#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ +#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ +#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ +#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ +#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ +#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ +#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ +#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ +#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ +#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ +#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ /** * @} */ @@ -1037,9 +1039,9 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, */ #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) @@ -1133,19 +1135,26 @@ HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, + pFDCAN_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxEventFifoCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo0CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_RxFifo1CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_TxBufferAbortCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, + pFDCAN_ErrorStatusCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ /** @@ -1157,7 +1166,9 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h */ /* Configuration functions ****************************************************/ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); -HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt); +HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, + uint32_t NonMatchingExt, uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt); HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); @@ -1166,12 +1177,14 @@ HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod); +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, + uint32_t TimeoutPeriod); HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter); +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, + uint32_t TdcFilter); HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); @@ -1188,12 +1201,15 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); /* Control functions **********************************************************/ HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); -HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, + uint8_t *pTxData); uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); -HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, + FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); -HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus); +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, + FDCAN_HpMsgStatusTypeDef *HpMsgStatus); HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); @@ -1210,7 +1226,8 @@ HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfd */ /* Interrupts management ******************************************************/ HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); -HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes); +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, + uint32_t BufferIndexes); HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash.h index 6578358a06f..d4f381baadd 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash.h @@ -558,14 +558,22 @@ typedef struct * @brief Set the FLASH Latency. * @param __LATENCY__ FLASH Latency. * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states - * @arg FLASH_LATENCY_3: FLASH Three wait states - * @arg FLASH_LATENCY_4: FLASH Four wait states - * @arg FLASH_LATENCY_5: FLASH Five wait states - * @arg FLASH_LATENCY_6: FLASH Six wait states - * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait state + * @arg FLASH_LATENCY_11: FLASH Eleven wait state + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states * @retval None */ #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) @@ -574,14 +582,22 @@ typedef struct * @brief Get the FLASH Latency. * @retval FLASH_Latency. * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states - * @arg FLASH_LATENCY_3: FLASH Three wait states - * @arg FLASH_LATENCY_4: FLASH Four wait states - * @arg FLASH_LATENCY_5: FLASH Five wait states - * @arg FLASH_LATENCY_6: FLASH Six wait states - * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_0: FLASH Zero wait state + * @arg FLASH_LATENCY_1: FLASH One wait state + * @arg FLASH_LATENCY_2: FLASH Two wait states + * @arg FLASH_LATENCY_3: FLASH Three wait states + * @arg FLASH_LATENCY_4: FLASH Four wait states + * @arg FLASH_LATENCY_5: FLASH Five wait states + * @arg FLASH_LATENCY_6: FLASH Six wait states + * @arg FLASH_LATENCY_7: FLASH Seven wait states + * @arg FLASH_LATENCY_8: FLASH Eight wait states + * @arg FLASH_LATENCY_9: FLASH Nine wait states + * @arg FLASH_LATENCY_10: FLASH Ten wait state + * @arg FLASH_LATENCY_11: FLASH Eleven wait state + * @arg FLASH_LATENCY_12: FLASH Twelve wait states + * @arg FLASH_LATENCY_13: FLASH Thirteen wait states + * @arg FLASH_LATENCY_14: FLASH Fourteen wait states + * @arg FLASH_LATENCY_15: FLASH Fifteen wait states */ #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) @@ -850,7 +866,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \ (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) #define FLASH_BANK_SIZE (FLASH_SIZE) -#define FLASH_PAGE_NB 64U +#define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : 64U) #endif #define FLASH_PAGE_SIZE 0x800U /* 2 KB */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash_ramfunc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash_ramfunc.c index 2e177aa9742..254947b2be6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash_ramfunc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash_ramfunc.c @@ -130,7 +130,7 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void) */ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) { - register uint32_t count, reg; + uint32_t count, reg; HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.c index f5816bb0db5..988428a6937 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.c @@ -9,7 +9,20 @@ * + Peripheral Control functions * + Callback functions * + IRQ handler management - * + Peripheral State functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** * * @verbatim ================================================================================ @@ -18,17 +31,18 @@ [..] The FMAC HAL driver can be used as follows: - (#) Initialize the FMAC low level resources by implementing the HAL_FMAC_MspInit(): - (++) Enable the FMAC interface clock using __HAL_RCC_FMAC_CLK_ENABLE(). + (#) Initialize the FMAC low level resources by implementing the @ref HAL_FMAC_MspInit(): + (++) Enable the FMAC interface clock using @ref __HAL_RCC_FMAC_CLK_ENABLE(). (++) In case of using interrupts (e.g. access configured as FMAC_BUFFER_ACCESS_IT): - (+++) Configure the FMAC interrupt priority using HAL_NVIC_SetPriority(). - (+++) Enable the FMAC IRQ handler using HAL_NVIC_EnableIRQ(). - (+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler(). + (+++) Configure the FMAC interrupt priority using @ref HAL_NVIC_SetPriority(). + (+++) Enable the FMAC IRQ handler using @ref HAL_NVIC_EnableIRQ(). + (+++) In FMAC IRQ handler, call @ref HAL_FMAC_IRQHandler(). (++) In case of using DMA to control data transfer (e.g. access configured as FMAC_BUFFER_ACCESS_DMA): - (+++) Enable the DMA1 interface clock using __HAL_RCC_DMA1_CLK_ENABLE(). - (+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE(). - (+++) If the initialisation of the internal buffers (coefficients, input, + (+++) Enable the DMA interface clock using @ref __HAL_RCC_DMA1_CLK_ENABLE() + or @ref __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance. + (+++) Enable the DMAMUX1 interface clock using @ref __HAL_RCC_DMAMUX1_CLK_ENABLE(). + (+++) If the initialization of the internal buffers (coefficients, input, output) is done via DMA, configure and enable one DMA channel for managing data transfer from memory to memory (preload channel). (+++) If the input buffer is accessed via DMA, configure and enable one @@ -38,16 +52,16 @@ one DMA channel for managing data transfer from peripheral to memory (output channel). (+++) Associate the initialized DMA handle(s) to the FMAC DMA handle(s) - using __HAL_LINKDMA(). + using @ref __HAL_LINKDMA(). (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the enabled DMA channel(s) using HAL_NVIC_SetPriority() - and HAL_NVIC_EnableIRQ(). + interrupt on the enabled DMA channel(s) using @ref HAL_NVIC_SetPriority() + and @ref HAL_NVIC_EnableIRQ(). - (#) Initialize the FMAC HAL using HAL_FMAC_Init(). This function - resorts to HAL_FMAC_MspInit() for low-level initialization. + (#) Initialize the FMAC HAL using @ref HAL_FMAC_Init(). This function + resorts to @ref HAL_FMAC_MspInit() for low-level initialization. - (#) Configure the FMAC processing (filter) using HAL_FMAC_FilterConfig() - or HAL_FMAC_FilterConfig_DMA(). + (#) Configure the FMAC processing (filter) using @ref HAL_FMAC_FilterConfig() + or @ref HAL_FMAC_FilterConfig_DMA(). This function: (++) Defines the memory area within the FMAC internal memory (input, coefficients, output) and the associated threshold (input, output). @@ -60,61 +74,61 @@ (++) Enable the error interruptions in the input access and/or the output access is done through IT/DMA. If an error occurs, the interruption will be triggered in loop. In order to recover, the user will have - to reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init. - Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT; + to reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init. + Optionally, he can also disable the interrupt using @ref __HAL_FMAC_DISABLE_IT; the error status will be kept, but no more interrupt will be triggered. (++) Write the provided coefficients into the internal memory using polling - mode (HAL_FMAC_FilterConfig()) or DMA (HAL_FMAC_FilterConfig_DMA()). - In the DMA case, HAL_FMAC_FilterConfigCallback() is called when + mode ( @ref HAL_FMAC_FilterConfig() ) or DMA ( @ref HAL_FMAC_FilterConfig_DMA() ). + In the DMA case, @ref HAL_FMAC_FilterConfigCallback() is called when the handling is over. (#) Optionally, the user can enable the error interruption related to - saturation by calling __HAL_FMAC_ENABLE_IT. This helps in debugging the + saturation by calling @ref __HAL_FMAC_ENABLE_IT. This helps in debugging the filter. If a saturation occurs, the interruption will be triggered in loop. In order to recover, the user will have to: - (++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if - he wishes to continue all the same. - (++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init. + (++) Disable the interruption by calling @ref __HAL_FMAC_DISABLE_IT if + the user wishes to continue all the same. + (++) Reset the IP with the sequence @ref HAL_FMAC_DeInit / @ref HAL_FMAC_Init. (#) Optionally, preload input (FIR, IIR) and output (IIR) data using - HAL_FMAC_FilterPreload() or HAL_FMAC_FilterPreload_DMA(). - In the DMA case, HAL_FMAC_FilterPreloadCallback() is called when + @ref HAL_FMAC_FilterPreload() or @ref HAL_FMAC_FilterPreload_DMA(). + In the DMA case, @ref HAL_FMAC_FilterPreloadCallback() is called when the handling is over. This step is optional as the filter can be started without preloaded data. - (#) Start the FMAC processing (filter) using HAL_FMAC_FilterStart(). + (#) Start the FMAC processing (filter) using @ref HAL_FMAC_FilterStart(). This function also configures the output buffer that will be filled from the circular internal output buffer. The function returns immediately without updating the provided buffer. The IP processing will be active until - HAL_FMAC_FilterStop() is called. + @ref HAL_FMAC_FilterStop() is called. - (#) If the input internal buffer is accessed via DMA, HAL_FMAC_HalfGetDataCallback() + (#) If the input internal buffer is accessed via DMA, @ref HAL_FMAC_HalfGetDataCallback() will be called to indicate that half of the input buffer has been handled. - (#) If the input internal buffer is accessed via DMA or interrupt, HAL_FMAC_GetDataCallback() + (#) If the input internal buffer is accessed via DMA or interrupt, @ref HAL_FMAC_GetDataCallback() will be called to require new input data. It will be provided through - HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode. + @ref HAL_FMAC_AppendFilterData() if the DMA isn't in circular mode. - (#) If the output internal buffer is accessed via DMA, HAL_FMAC_HalfOutputDataReadyCallback() + (#) If the output internal buffer is accessed via DMA, @ref HAL_FMAC_HalfOutputDataReadyCallback() will be called to indicate that half of the output buffer has been handled. (#) If the output internal buffer is accessed via DMA or interrupt, - HAL_FMAC_OutputDataReadyCallback() will be called to require a new output - buffer. It will be provided through HAL_FMAC_ConfigFilterOutputBuffer() + @ref HAL_FMAC_OutputDataReadyCallback() will be called to require a new output + buffer. It will be provided through @ref HAL_FMAC_ConfigFilterOutputBuffer() if the DMA isn't in circular mode. - (#) In all modes except none, provide new input data to be processed via HAL_FMAC_AppendFilterData(). + (#) In all modes except none, provide new input data to be processed via @ref HAL_FMAC_AppendFilterData(). This function should only be called once the previous input data has been handled (the preloaded input data isn't concerned). (#) In all modes except none, provide a new output buffer to be filled via - HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous + @ref HAL_FMAC_ConfigFilterOutputBuffer(). This function should only be called once the previous user's output buffer has been filled. - (#) In polling mode, handle the input and output data using HAL_FMAC_PollFilterData(). + (#) In polling mode, handle the input and output data using @ref HAL_FMAC_PollFilterData(). This function: - (++) Write the user's input data (provided via HAL_FMAC_AppendFilterData()) + (++) Write the user's input data (provided via @ref HAL_FMAC_AppendFilterData()) into the FMAC input memory area. (++) Read the FMAC output memory area and write it into the user's output buffer. It will return either when: @@ -124,10 +138,10 @@ The user will have to use the updated input and output sizes to keep track of them. - (#) Stop the FMAC processing (filter) using HAL_FMAC_FilterStop(). + (#) Stop the FMAC processing (filter) using @ref HAL_FMAC_FilterStop(). - (#) Call HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function - resorts to HAL_FMAC_MspDeInit() for low-level de-initialization. + (#) Call @ref HAL_FMAC_DeInit() to de-initialize the FMAC peripheral. This function + resorts to @ref HAL_FMAC_MspDeInit() for low-level de-initialization. ##### Callback registration ##### ================================== @@ -170,7 +184,7 @@ [..] By default, after the @ref HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_FMAC_TxCpltCallback(), @ref HAL_FMAC_RxHalfCpltCallback(). + examples @ref GetDataCallback(), @ref OutputDataReadyCallback(). Exception done for MspInit and MspDeInit functions that are respectively reset to the legacy weak (surcharged) functions in the @ref HAL_FMAC_Init() and @ref HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand). @@ -194,18 +208,6 @@ @endverbatim * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -218,11 +220,10 @@ */ /** @defgroup FMAC FMAC - * @brief FMAC HAL driver modules + * @brief FMAC HAL driver module * @{ */ -/* External variables --------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup FMAC_Private_Constants FMAC Private Constants @@ -230,12 +231,28 @@ */ #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU) +#define MAX_PRELOAD_INDEX 0xFFU #define PRELOAD_ACCESS_DMA 0x00U #define PRELOAD_ACCESS_POLLING 0x01U #define POLLING_DISABLED 0U #define POLLING_ENABLED 1U #define POLLING_NOT_STOPPED 0U #define POLLING_STOPPED 1U +/* FMAC polling-based communications time-out value */ +#define HAL_FMAC_TIMEOUT_VALUE 1000U +/* FMAC reset time-out value */ +#define HAL_FMAC_RESET_TIMEOUT_VALUE 500U +/* DMA Read Requests Enable */ +#define FMAC_DMA_REN FMAC_CR_DMAREN +/* DMA Write Channel Enable */ +#define FMAC_DMA_WEN FMAC_CR_DMAWEN +/* FMAC Execution Enable */ +#define FMAC_START FMAC_PARAM_START + +/** + * @} + */ + /** * @} @@ -295,40 +312,27 @@ ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos)) /** - * @brief Get the threshold matching the watermak. + * @brief Get the threshold matching the watermark. * @param __WM__ Watermark value. * @retval THRESHOLD */ -#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) ((__WM__ == FMAC_THRESHOLD_1)? 1U: \ - (__WM__ == FMAC_THRESHOLD_2)? 2U: \ - (__WM__ == FMAC_THRESHOLD_4)? 4U:8U) - -/** - * @brief Check whether the threshold is applicable. - * @param __SIZE__ Size of the matching buffer. - * @param __WM__ Watermark value. - * @param __ACCESS__ Access to the buffer (polling, it, dma, none). - * @retval THRESHOLD - */ -#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \ - ((__WM__) == FMAC_THRESHOLD_2)? 2U: \ - ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \ - ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \ - ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA))) +#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) (((__WM__) == FMAC_THRESHOLD_1)? 1U: \ + ((__WM__) == FMAC_THRESHOLD_2)? 2U: \ + ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U) /** * @} */ /* Private variables ---------------------------------------------------------*/ - +/* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); -static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig, +static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig, uint8_t PreloadAccess); static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess); @@ -348,7 +352,7 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma); static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma); static void FMAC_DMAError(DMA_HandleTypeDef *hdma); -/* Private functions ---------------------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ /** @defgroup FMAC_Exported_Functions FMAC Exported Functions * @{ @@ -366,6 +370,8 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma); (+) DeInitialize the FMAC peripheral (+) Initialize the FMAC MSP (MCU Specific Package) (+) De-Initialize the FMAC MSP + (+) Register a User FMAC Callback + (+) Unregister a FMAC CallBack [..] @@ -376,10 +382,12 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initialize the FMAC peripheral and the associated handle. * @param hfmac pointer to a FMAC_HandleTypeDef structure. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac) { + HAL_StatusTypeDef status; + /* Check the FMAC handle allocation */ if (hfmac == NULL) { @@ -391,7 +399,7 @@ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac) if (hfmac->State == HAL_FMAC_STATE_RESET) { - /* Allocate lock resource and initialize it */ + /* Initialize lock resource */ hfmac->Lock = HAL_UNLOCKED; #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) @@ -418,36 +426,36 @@ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac) } /* Reset pInput and pOutput */ - hfmac->FilterParam = 0UL; + hfmac->FilterParam = 0U; FMAC_ResetDataPointers(hfmac); /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_TIMEOUT) { /* Update FMAC error code and FMAC peripheral state */ - hfmac->ErrorCode = HAL_FMAC_ERROR_RESET; + hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET; hfmac->State = HAL_FMAC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hfmac); - - return HAL_TIMEOUT; + status = HAL_TIMEOUT; } + else + { + /* Update FMAC error code and FMAC peripheral state */ + hfmac->ErrorCode = HAL_FMAC_ERROR_NONE; + hfmac->State = HAL_FMAC_STATE_READY; - /* Update FMAC error code and FMAC peripheral state */ - hfmac->ErrorCode = HAL_FMAC_ERROR_NONE; - hfmac->State = HAL_FMAC_STATE_READY; + status = HAL_OK; + } - /* Process Unlocked */ __HAL_UNLOCK(hfmac); - return HAL_OK; + return status; } /** * @brief De-initialize the FMAC peripheral. * @param hfmac pointer to a FMAC structure. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac) { @@ -467,7 +475,7 @@ HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac) hfmac->ErrorCode = HAL_FMAC_ERROR_NONE; /* Reset pInput and pOutput */ - hfmac->FilterParam = 0UL; + hfmac->FilterParam = 0U; FMAC_ResetDataPointers(hfmac); #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) @@ -485,10 +493,9 @@ HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac) /* Change FMAC peripheral state */ hfmac->State = HAL_FMAC_STATE_RESET; - /* Release Lock */ + /* Always release Lock in case of de-initialization */ __HAL_UNLOCK(hfmac); - /* Return function status */ return HAL_OK; } @@ -524,8 +531,8 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac) #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) /** - * @brief Register a User FMAC Callback - * to be used instead of the weak predefined callback. + * @brief Register a User FMAC Callback. + * @note The User FMAC Callback is to be used instead of the weak predefined callback. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param CallbackID ID of the callback to be registered. @@ -540,13 +547,19 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac) * @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID * @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID * @param pCallback pointer to the Callback function. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID, pFMAC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; + /* Check the FMAC handle allocation */ + if (hfmac == NULL) + { + return HAL_ERROR; + } + if (pCallback == NULL) { /* Update the error code */ @@ -554,10 +567,9 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ return HAL_ERROR; } - /* Process locked */ __HAL_LOCK(hfmac); - if (HAL_FMAC_STATE_READY == hfmac->State) + if (hfmac->State == HAL_FMAC_STATE_READY) { switch (CallbackID) { @@ -606,7 +618,7 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ break; } } - else if (HAL_FMAC_STATE_RESET == hfmac->State) + else if (hfmac->State == HAL_FMAC_STATE_RESET) { switch (CallbackID) { @@ -636,7 +648,6 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(hfmac); return status; @@ -644,7 +655,7 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ /** * @brief Unregister a FMAC CallBack. - * FMAC callback is redirected to the weak predefined callback. + * @note The FMAC callback is redirected to the weak predefined callback. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module * @param CallbackID ID of the callback to be unregistered. @@ -658,16 +669,21 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ * @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID * @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID * @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ + /* Check the FMAC handle allocation */ + if (hfmac == NULL) + { + return HAL_ERROR; + } + __HAL_LOCK(hfmac); - if (HAL_FMAC_STATE_READY == hfmac->State) + if (hfmac->State == HAL_FMAC_STATE_READY) { switch (CallbackID) { @@ -716,7 +732,7 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA break; } } - else if (HAL_FMAC_STATE_RESET == hfmac->State) + else if (hfmac->State == HAL_FMAC_STATE_RESET) { switch (CallbackID) { @@ -746,7 +762,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(hfmac); return status; @@ -777,38 +792,40 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA */ /** - * @brief Configure the FMAC filter according to the parameters + * @brief Configure the FMAC filter. + * @note The configuration is done according to the parameters * specified in the FMAC_FilterConfigTypeDef structure. * The provided data will be loaded using polling mode. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that + * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that * contains the FMAC configuration information. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ -HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig) +HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig) { - return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_POLLING)); + return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_POLLING)); } /** - * @brief Configure the FMAC filter according to the parameters + * @brief Configure the FMAC filter. + * @note The configuration is done according to the parameters * specified in the FMAC_FilterConfigTypeDef structure. * The provided data will be loaded using DMA. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that + * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that * contains the FMAC configuration information. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ -HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig) +HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig) { - return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_DMA)); + return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_DMA)); } /** * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter. - * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called. + * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called. * The provided data will be loaded using polling mode. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. @@ -820,10 +837,10 @@ HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_Filt * If not needed, it should be set to NULL. * @param OutputSize Size of the output vector. * As pOutput is used for preloading data, it cannot be bigger than the output memory area. - * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload + * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload * (each call filling partly the buffers). In case of overflow (too much data provided through * all these calls), an error will be returned. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize) @@ -833,7 +850,7 @@ HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pIn /** * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter. - * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called. + * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called. * The provided data will be loaded using DMA. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. @@ -845,10 +862,10 @@ HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pIn * If not needed, it should be set to NULL. * @param OutputSize Size of the output vector. * As pOutput is used for preloading data, it cannot be bigger than the output memory area. - * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload + * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload * (each call filling partly the buffers). In case of overflow (too much data provided through * all these calls), an error will be returned. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize) @@ -866,21 +883,21 @@ HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t * If it is set to NULL, the output will not be read and it will be up to * an external IP to empty the output buffer. * @param pOutputSize pointer to the size of the output buffer. The number of read data will be written here. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize) { - uint32_t tmpcr = 0UL; + uint32_t tmpcr = 0U; HAL_StatusTypeDef status; /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) != 0UL) + if (FMAC_GET_START_BIT(hfmac) != 0U) { return HAL_ERROR; } /* Check that a valid configuration was done previously */ - if (hfmac->FilterParam == 0UL) + if (hfmac->FilterParam == 0U) { return HAL_ERROR; } @@ -935,34 +952,27 @@ HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutp /* Reset the busy flag (do not overwrite the possible write and read flag) */ hfmac->State = HAL_FMAC_STATE_READY; - - /* Return function status */ - return status; } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_BUSY; } + + return status; } /** - * @brief Provide a new input buffer that will be loaded into the FMAC - * input memory area. + * @brief Provide a new input buffer that will be loaded into the FMAC input memory area. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pInput New input vector (additional input data). * @param pInputSize Size of the input vector (if all the data can't be * written, it will be updated with the number of data read from FMAC). - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize) { - /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) == 0UL) - { - return HAL_ERROR; - } + HAL_StatusTypeDef status; /* Check the function parameters */ if ((pInput == NULL) || (pInputSize == NULL)) @@ -974,6 +984,12 @@ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t * return HAL_ERROR; } + /* Check the START bit state */ + if (FMAC_GET_START_BIT(hfmac) == 0U) + { + return HAL_ERROR; + } + /* Check the FMAC configuration */ if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_NONE) { @@ -990,33 +1006,29 @@ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t * if (hfmac->WrState == HAL_FMAC_STATE_READY) { /* Register the new input buffer */ - return (FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize)); + status = FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize); } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_BUSY; } + + return status; } /** - * @brief Provide a new output buffer to be filled with the data - * computed by FMAC unit. + * @brief Provide a new output buffer to be filled with the data computed by FMAC unit. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pOutput New output vector. * @param pOutputSize Size of the output vector (if the vector can't * be entirely filled, pOutputSize will be updated with the number * of data read from FMAC). - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize) { - /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) == 0UL) - { - return HAL_ERROR; - } + HAL_StatusTypeDef status; /* Check the function parameters */ if ((pOutput == NULL) || (pOutputSize == NULL)) @@ -1028,6 +1040,12 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i return HAL_ERROR; } + /* Check the START bit state */ + if (FMAC_GET_START_BIT(hfmac) == 0U) + { + return HAL_ERROR; + } + /* Check the FMAC configuration */ if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE) { @@ -1044,18 +1062,20 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i if (hfmac->RdState == HAL_FMAC_STATE_READY) { /* Register the new output buffer */ - return (FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize)); + status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize); } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_BUSY; } + + return status; } /** - * @brief Write the previously provided user's input data and - * fill the previously provided user's output buffer, + * @brief Handle the input and/or output data in polling mode + * @note This function writes the previously provided user's input data and + * fills the previously provided user's output buffer, * according to the existing FMAC configuration (polling mode only). * The function returns when the input data has been handled or * when the output data is filled. The possible unused data isn't @@ -1065,7 +1085,7 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param Timeout timeout value. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout) { @@ -1074,9 +1094,10 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti uint8_t inpollingover = POLLING_NOT_STOPPED; uint8_t outpolling; uint8_t outpollingover = POLLING_NOT_STOPPED; + HAL_StatusTypeDef status; /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) == 0UL) + if (FMAC_GET_START_BIT(hfmac) == 0U) { return HAL_ERROR; } @@ -1161,41 +1182,40 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti /* Reset the busy flag (do not overwrite the possible write and read flag) */ hfmac->State = HAL_FMAC_STATE_READY; - /* Return function status */ if ((HAL_GetTick() - tickstart) >= Timeout) { - return HAL_TIMEOUT; + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; + status = HAL_TIMEOUT; } else { - return HAL_OK; + status = HAL_OK; } } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_BUSY; } + + return status; } /** * @brief Stop the FMAC processing. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - - /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) == 0UL) - { - return HAL_ERROR; - } + HAL_StatusTypeDef status; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) { + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_BUSY; + /* Set the START bit to 0 (stop the previously configured filter) */ CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START); @@ -1218,20 +1238,25 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) /* Update FMAC error code and FMAC peripheral state */ hfmac->ErrorCode = HAL_FMAC_ERROR_RESET; hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + status = HAL_TIMEOUT; } + else + { + /* Reset the data pointers */ + FMAC_ResetDataPointers(hfmac); - /* Reset the data pointers */ - FMAC_ResetDataPointers(hfmac); + status = HAL_OK; + } - /* Return function status */ - return HAL_OK; + /* Reset the busy flag */ + hfmac->State = HAL_FMAC_STATE_READY; } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_BUSY; } + + return status; } /** @@ -1397,7 +1422,7 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) /* Check if the read interrupt is enabled and if Y buffer empty flag isn't set */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_RIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0U)) { /* Read some data if possible (Y size is used as a pseudo timeout in order to not get stuck too long under IT if FMAC keeps on processing input @@ -1424,7 +1449,7 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) /* Check if the write interrupt is enabled and if X1 buffer full flag isn't set */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_WIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0U)) { /* Write some data if possible (X1 size is used as a pseudo timeout in order to not get stuck too long under IT if FMAC keep on processing input @@ -1451,21 +1476,21 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) /* Check if the overflow error interrupt is enabled and if overflow error flag is raised */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_OVFLIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0U)) { hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL; } /* Check if the underflow error interrupt is enabled and if underflow error flag is raised */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_UNFLIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0U)) { hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL; } /* Check if the saturation error interrupt is enabled and if saturation error flag is raised */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_SATIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0U)) { hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT; } @@ -1486,29 +1511,30 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) * @} */ -/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions. +/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State and Error functions + * @brief Peripheral State and Error functions. * @verbatim ============================================================================== - ##### Peripheral State functions ##### + ##### Peripheral State and Error functions ##### ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. + [..] This subsection provides functions allowing to + (+) Check the FMAC state + (+) Get error code @endverbatim * @{ */ /** - * @brief Return the FMAC handle state. + * @brief Return the FMAC state. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @retval HAL state + * @retval HAL_FMAC_StateTypeDef FMAC state */ HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac) { - /* Return FMAC handle state */ + /* Return FMAC state */ return hfmac->State; } @@ -1517,7 +1543,7 @@ HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac) * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @note The returned error is a bit-map combination of possible errors. - * @retval Error bit-map + * @retval uint32_t Error bit-map based on @ref FMAC_Error_Code */ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac) { @@ -1545,7 +1571,7 @@ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac) /** * @brief Perform a reset of the FMAC unit. * @param hfmac FMAC handle. - * @retval FMAC status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac) { @@ -1558,10 +1584,11 @@ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac) SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET); /* Wait until flag is reset */ - while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0UL) + while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U) { if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE) { + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; return HAL_TIMEOUT; } } @@ -1573,7 +1600,7 @@ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac) /** * @brief Reset the data pointers of the FMAC unit. * @param hfmac FMAC handle. - * @retval FMAC status + * @retval None */ static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac) { @@ -1584,7 +1611,7 @@ static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac) /** * @brief Reset the input data pointers of the FMAC unit. * @param hfmac FMAC handle. - * @retval FMAC status + * @retval None */ static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) { @@ -1597,7 +1624,7 @@ static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) /** * @brief Reset the output data pointers of the FMAC unit. * @param hfmac FMAC handle. - * @retval FMAC status + * @retval None */ static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) { @@ -1608,15 +1635,17 @@ static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) } /** - * @brief Configure the FMAC filter according to the parameters - specified in the FMAC_FilterConfigTypeDef structure. + * @brief Configure the FMAC filter. + * @note The configuration is done according to the parameters + * specified in the FMAC_FilterConfigTypeDef structure. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that + * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that * contains the FMAC configuration information. - * @retval HAL status + * @param PreloadAccess access mode used for the preload (polling or DMA). + * @retval HAL_StatusTypeDef HAL status */ -static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig, +static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig, uint8_t PreloadAccess) { uint32_t tickstart; @@ -1626,193 +1655,190 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte #endif /* USE_FULL_ASSERT */ /* Check the parameters */ - assert_param(IS_FMAC_THRESHOLD(sConfig->InputThreshold)); - assert_param(IS_FMAC_THRESHOLD(sConfig->OutputThreshold)); - assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->InputAccess)); - assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->OutputAccess)); - assert_param(IS_FMAC_CLIP_STATE(sConfig->Clip)); - assert_param(IS_FMAC_FILTER_FUNCTION(sConfig->Filter)); - assert_param(IS_FMAC_PARAM_P(sConfig->Filter, sConfig->P)); - assert_param(IS_FMAC_PARAM_Q(sConfig->Filter, sConfig->Q)); - assert_param(IS_FMAC_PARAM_R(sConfig->Filter, sConfig->R)); + assert_param(IS_FMAC_THRESHOLD(pConfig->InputThreshold)); + assert_param(IS_FMAC_THRESHOLD(pConfig->OutputThreshold)); + assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->InputAccess)); + assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->OutputAccess)); + assert_param(IS_FMAC_CLIP_STATE(pConfig->Clip)); + assert_param(IS_FMAC_FILTER_FUNCTION(pConfig->Filter)); + assert_param(IS_FMAC_PARAM_P(pConfig->Filter, pConfig->P)); + assert_param(IS_FMAC_PARAM_Q(pConfig->Filter, pConfig->Q)); + assert_param(IS_FMAC_PARAM_R(pConfig->Filter, pConfig->R)); /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) != 0UL) + if (FMAC_GET_START_BIT(hfmac) != 0U) { return HAL_ERROR; } /* Check handle state is ready */ - if (hfmac->State == HAL_FMAC_STATE_READY) + if (hfmac->State != HAL_FMAC_STATE_READY) { - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_BUSY; + return HAL_BUSY; + } - /* Get tick */ - tickstart = HAL_GetTick(); + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_BUSY; - /* Indicate that there is no valid configuration done */ - hfmac->FilterParam = 0UL; + /* Get tick */ + tickstart = HAL_GetTick(); - /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */ - if (sConfig->InputBufferSize != 0U) - { - MODIFY_REG(hfmac->Instance->X1BUFCFG, \ - (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \ - (((((uint32_t)(sConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \ - ((((uint32_t)(sConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE))); - } + /* Indicate that there is no valid configuration done */ + hfmac->FilterParam = 0U; - /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */ - if (sConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE) - { - /* Check the parameter */ - assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), sConfig->InputThreshold, sConfig->InputAccess)); + /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */ + if (pConfig->InputBufferSize != 0U) + { + MODIFY_REG(hfmac->Instance->X1BUFCFG, \ + (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \ + (((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \ + ((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE))); + } - MODIFY_REG(hfmac->Instance->X1BUFCFG, \ - FMAC_X1BUFCFG_FULL_WM, \ - ((sConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM)); - } + /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */ + if (pConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE) + { + /* Check the parameter */ + assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), pConfig->InputThreshold, pConfig->InputAccess)); - /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */ - if (sConfig->CoeffBufferSize != 0U) - { - MODIFY_REG(hfmac->Instance->X2BUFCFG, \ - (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \ - (((((uint32_t)(sConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \ - ((((uint32_t)(sConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE))); - } + MODIFY_REG(hfmac->Instance->X1BUFCFG, \ + FMAC_X1BUFCFG_FULL_WM, \ + ((pConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM)); + } - /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */ - if (sConfig->OutputBufferSize != 0U) - { - MODIFY_REG(hfmac->Instance->YBUFCFG, \ - (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \ - (((((uint32_t)(sConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \ - ((((uint32_t)(sConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE))); - } + /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */ + if (pConfig->CoeffBufferSize != 0U) + { + MODIFY_REG(hfmac->Instance->X2BUFCFG, \ + (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \ + (((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \ + ((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE))); + } - /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */ - if (sConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE) - { - /* Check the parameter */ - assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), sConfig->OutputThreshold, sConfig->OutputAccess)); + /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */ + if (pConfig->OutputBufferSize != 0U) + { + MODIFY_REG(hfmac->Instance->YBUFCFG, \ + (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \ + (((((uint32_t)(pConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \ + ((((uint32_t)(pConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE))); + } - MODIFY_REG(hfmac->Instance->YBUFCFG, \ - FMAC_YBUFCFG_EMPTY_WM, \ - ((sConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM)); - } + /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */ + if (pConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE) + { + /* Check the parameter */ + assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), pConfig->OutputThreshold, pConfig->OutputAccess)); - /* CR: Configure the clip feature */ - tmpcr = sConfig->Clip & FMAC_CR_CLIPEN; + MODIFY_REG(hfmac->Instance->YBUFCFG, \ + FMAC_YBUFCFG_EMPTY_WM, \ + ((pConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM)); + } - /* CR: If IT or DMA will be used, enable error interrupts. - * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */ - if ((sConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) || - (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT)) - { - tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN; - } + /* FMAC_CR: Configure the clip feature */ + tmpcr = pConfig->Clip & FMAC_CR_CLIPEN; + + /* FMAC_CR: If IT or DMA will be used, enable error interrupts. + * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */ + if ((pConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) || + (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT)) + { + tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN; + } - /* CR: write the value */ - WRITE_REG(hfmac->Instance->CR, tmpcr); + /* FMAC_CR: write the value */ + WRITE_REG(hfmac->Instance->CR, tmpcr); - /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */ - hfmac->InputAccess = sConfig->InputAccess; - hfmac->OutputAccess = sConfig->OutputAccess; + /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */ + hfmac->InputAccess = pConfig->InputAccess; + hfmac->OutputAccess = pConfig->OutputAccess; - /* Check whether the configured X2 is big enough for the filter */ + /* Check whether the configured X2 is big enough for the filter */ #if defined(USE_FULL_ASSERT) - x2size = FMAC_GET_X2_SIZE(hfmac); + x2size = FMAC_GET_X2_SIZE(hfmac); #endif /* USE_FULL_ASSERT */ - assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= sConfig->P)) || \ - ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)sConfig->P + (uint32_t)sConfig->Q)))); + assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \ + ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q)))); + + /* Build the PARAM value that will be used when starting the filter */ + hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter | \ + ((((uint32_t)(pConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \ + ((((uint32_t)(pConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \ + ((((uint32_t)(pConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R)); + + /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */ + if ((pConfig->pCoeffB != NULL) && (pConfig->CoeffBSize != 0U)) + { + /* FIR/IIR: The provided coefficients should match X2 size */ + assert_param(((uint32_t)pConfig->CoeffASize + (uint32_t)pConfig->CoeffBSize) <= x2size); + /* FIR/IIR: The size of pCoeffB should match the parameter P */ + assert_param(pConfig->CoeffBSize >= pConfig->P); + /* pCoeffA should be provided for IIR but not for FIR */ + /* IIR : if pCoeffB is provided, pCoeffA should also be there */ + /* IIR: The size of pCoeffA should match the parameter Q */ + assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && + (pConfig->pCoeffA == NULL) && (pConfig->CoeffASize == 0U)) || + ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && + (pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U) && + (pConfig->CoeffASize >= pConfig->Q))); - /* Build the PARAM value that will be used when starting the filter */ - hfmac->FilterParam = (FMAC_PARAM_START | sConfig->Filter | \ - ((((uint32_t)(sConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \ - ((((uint32_t)(sConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \ - ((((uint32_t)(sConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R)); + /* Write number of values to be loaded, the data load function and start the operation */ + WRITE_REG(hfmac->Instance->PARAM, \ + (((uint32_t)(pConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \ + ((uint32_t)(pConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \ + FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START)); - /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */ - if ((sConfig->pCoeffB != NULL) && (sConfig->CoeffBSize != 0U)) + if (PreloadAccess == PRELOAD_ACCESS_POLLING) { - /* FIR/IIR: The provided coefficients should match X2 size */ - assert_param(((uint32_t)sConfig->CoeffASize + (uint32_t)sConfig->CoeffBSize) <= x2size); - /* FIR/IIR: The size of pCoeffB should match the parameter P */ - assert_param(sConfig->CoeffBSize >= sConfig->P); - /* pCoeffA should be provided for IIR but not for FIR */ - /* IIR : if pCoeffB is provided, pCoeffA should also be there */ - /* IIR: The size of pCoeffA should match the parameter Q */ - assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) && - (sConfig->pCoeffA == NULL) && (sConfig->CoeffASize == 0U)) || - ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && - (sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U) && - (sConfig->CoeffASize >= sConfig->Q))); - - /* Write number of values to be loaded, the data load function and start the operation */ - WRITE_REG(hfmac->Instance->PARAM, \ - (((uint32_t)(sConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \ - ((uint32_t)(sConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \ - FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START)); - - if (PreloadAccess == PRELOAD_ACCESS_POLLING) + /* Load the buffer into the internal memory */ + FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffB), pConfig->CoeffBSize); + + /* Load pCoeffA if needed */ + if ((pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U)) { /* Load the buffer into the internal memory */ - FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffB), sConfig->CoeffBSize); - - /* Load pCoeffA if needed */ - if ((sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U)) - { - /* Load the buffer into the internal memory */ - FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffA), sConfig->CoeffASize); - } - - /* Wait for the end of the writing */ - if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) - { - hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_READY; + FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffA), pConfig->CoeffASize); } - else + + /* Wait for the end of the writing */ + if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) { - hfmac->pInput = sConfig->pCoeffA; - hfmac->InputCurrentSize = sConfig->CoeffASize; - - /* Set the FMAC DMA transfer complete callback */ - hfmac->hdmaPreload->XferHalfCpltCallback = NULL; - hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig; - /* Set the DMA error callback */ - hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; - - /* Enable the DMA stream managing FMAC preload data write */ - return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)sConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA, - sConfig->CoeffBSize)); + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; + hfmac->State = HAL_FMAC_STATE_TIMEOUT; + return HAL_TIMEOUT; } + + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_READY; } else { - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_READY; + hfmac->pInput = pConfig->pCoeffA; + hfmac->InputCurrentSize = pConfig->CoeffASize; + + /* Set the FMAC DMA transfer complete callback */ + hfmac->hdmaPreload->XferHalfCpltCallback = NULL; + hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig; + /* Set the DMA error callback */ + hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; + + /* Enable the DMA stream managing FMAC preload data write */ + return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA, + pConfig->CoeffBSize)); } } else { - /* Return function status */ - return HAL_BUSY; + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_READY; } - /* Return function status */ return HAL_OK; } /** * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter. - * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called. + * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pInput Preloading of the first elements of the input buffer (X1). @@ -1823,24 +1849,26 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte * If not needed, it should be set to NULL. * @param OutputSize Size of the output vector. * As pOutput is used for preloading data, it cannot be bigger than the output memory area. - * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload + * @param PreloadAccess access mode used for the preload (polling or DMA). + * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload * (each call filling partly the buffers). In case of overflow (too much data provided through * all these calls), an error will be returned. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess) { uint32_t tickstart; + HAL_StatusTypeDef status; /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) != 0UL) + if (FMAC_GET_START_BIT(hfmac) != 0U) { return HAL_ERROR; } /* Check that a valid configuration was done previously */ - if (hfmac->FilterParam == 0UL) + if (hfmac->FilterParam == 0U) { return HAL_ERROR; } @@ -1858,122 +1886,126 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t * } /* Check handle state is ready */ - if (hfmac->State == HAL_FMAC_STATE_READY) + if (hfmac->State != HAL_FMAC_STATE_READY) { - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_BUSY; + return HAL_BUSY; + } - /* Get tick */ - tickstart = HAL_GetTick(); + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_BUSY; - /* Preload the input buffer if required */ - if ((pInput != NULL) && (InputSize != 0U)) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Preload the input buffer if required */ + if ((pInput != NULL) && (InputSize != 0U)) + { + /* Write number of values to be loaded, the data load function and start the operation */ + WRITE_REG(hfmac->Instance->PARAM, \ + (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START)); + + if (PreloadAccess == PRELOAD_ACCESS_POLLING) { - /* Write number of values to be loaded, the data load function and start the operation */ - WRITE_REG(hfmac->Instance->PARAM, \ - (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START)); + /* Load the buffer into the internal memory */ + FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize); - if (PreloadAccess == PRELOAD_ACCESS_POLLING) + /* Wait for the end of the writing */ + if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) { - /* Load the buffer into the internal memory */ - FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize); - - /* Wait for the end of the writing */ - if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) - { - hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; + hfmac->State = HAL_FMAC_STATE_TIMEOUT; + return HAL_TIMEOUT; } - else - { - hfmac->pInput = pOutput; - hfmac->InputCurrentSize = OutputSize; + } + else + { + hfmac->pInput = pOutput; + hfmac->InputCurrentSize = OutputSize; - /* Set the FMAC DMA transfer complete callback */ - hfmac->hdmaPreload->XferHalfCpltCallback = NULL; - hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload; - /* Set the DMA error callback */ - hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; + /* Set the FMAC DMA transfer complete callback */ + hfmac->hdmaPreload->XferHalfCpltCallback = NULL; + hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload; + /* Set the DMA error callback */ + hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; - /* Enable the DMA stream managing FMAC preload data write */ - return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize)); - } + /* Enable the DMA stream managing FMAC preload data write */ + return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize)); } + } + + /* Preload the output buffer if required */ + if ((pOutput != NULL) && (OutputSize != 0U)) + { + /* Write number of values to be loaded, the data load function and start the operation */ + WRITE_REG(hfmac->Instance->PARAM, \ + (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START)); - /* Preload the output buffer if required */ - if ((pOutput != NULL) && (OutputSize != 0U)) + if (PreloadAccess == PRELOAD_ACCESS_POLLING) { - /* Write number of values to be loaded, the data load function and start the operation */ - WRITE_REG(hfmac->Instance->PARAM, \ - (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START)); + /* Load the buffer into the internal memory */ + FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize); - if (PreloadAccess == PRELOAD_ACCESS_POLLING) + /* Wait for the end of the writing */ + if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) { - /* Load the buffer into the internal memory */ - FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize); - - /* Wait for the end of the writing */ - if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) - { - hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; + hfmac->State = HAL_FMAC_STATE_TIMEOUT; + return HAL_TIMEOUT; } - else - { - hfmac->pInput = NULL; - hfmac->InputCurrentSize = 0U; + } + else + { + hfmac->pInput = NULL; + hfmac->InputCurrentSize = 0U; - /* Set the FMAC DMA transfer complete callback */ - hfmac->hdmaPreload->XferHalfCpltCallback = NULL; - hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload; - /* Set the DMA error callback */ - hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; + /* Set the FMAC DMA transfer complete callback */ + hfmac->hdmaPreload->XferHalfCpltCallback = NULL; + hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload; + /* Set the DMA error callback */ + hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; - /* Enable the DMA stream managing FMAC preload data write */ - return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize)); - } + /* Enable the DMA stream managing FMAC preload data write */ + return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize)); } + } - /* Update the error codes */ - if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL)) - { - hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL; - } - if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL)) - { - hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL; - } + /* Update the error codes */ + if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL)) + { + hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL; + } + if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL)) + { + hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL; + } + if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT)) + { + hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT; + } - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_READY; + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_READY; - /* Return function status */ - if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } + /* Return function status */ + if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE) + { + status = HAL_OK; } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_ERROR; } + return status; } /** * @brief Write data into FMAC internal memory through WDATA and increment input buffer pointer. - * This function is only used with preload functions. + * @note This function is only used with preload functions. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param ppData pointer to pointer to the data buffer. * @param Size size of the data buffer. - * @retval none + * @retval None */ static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size) { @@ -1992,17 +2024,16 @@ static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t * @param hfmac FMAC handle. * @param Tickstart Tick start value. * @param Timeout Timeout duration. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag changes */ - while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL) + while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) { if ((HAL_GetTick() - Tickstart) > Timeout) { - /* Process Unlocked */ - __HAL_UNLOCK(hfmac); + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; return HAL_TIMEOUT; } @@ -2011,14 +2042,13 @@ static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, } /** - * @brief Register the new input buffer, update DMA configuration - * if needed and change the FMAC state. + * @brief Register the new input buffer, update DMA configuration if needed and change the FMAC state. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pInput New input vector (additional input data). * @param pInputSize Size of the input vector (if all the data can't be * written, it will be updated with the number of data read from FMAC). - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize) @@ -2051,20 +2081,18 @@ static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hf hfmac->pInputSize = pInputSize; } - /* Return function status */ return HAL_OK; } /** - * @brief Register the new output buffer, update DMA configuration - * if needed and change the FMAC state. + * @brief Register the new output buffer, update DMA configuration if needed and change the FMAC state. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pOutput New output vector. * @param pOutputSize Size of the output vector (if the vector can't * be entirely filled, pOutputSize will be updated with the number * of data read from FMAC). - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize) @@ -2073,7 +2101,7 @@ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTyp hfmac->OutputCurrentSize = 0U; /* Check whether a valid pointer was provided */ - if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0UL)) + if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0U)) { /* The user will have to provide a valid configuration later */ hfmac->pOutput = NULL; @@ -2110,7 +2138,6 @@ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTyp hfmac->RdState = HAL_FMAC_STATE_BUSY_RD; } - /* Return function status */ return HAL_OK; } @@ -2119,7 +2146,7 @@ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTyp * @param hfmac FMAC handle. * @param MaxSizeToRead Maximum number of data to read (this serves as a timeout * if FMAC continuously writes into the output buffer). - * @retval HAL status + * @retval None */ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead) { @@ -2128,7 +2155,7 @@ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSiz uint32_t tmpvalue; /* Check if there is data to read */ - if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0UL) + if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0U) { return; } @@ -2157,7 +2184,7 @@ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSiz *(hfmac->pOutput) = (int16_t)tmpvalue; hfmac->pOutput++; hfmac->OutputCurrentSize++; - } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0UL); + } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0U); /* Y buffer empty flag has just be raised, read the threshold */ threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_Y_EMPTY_WM(hfmac)) - 1U; @@ -2183,7 +2210,7 @@ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSiz * @param hfmac FMAC handle. * @param MaxSizeToWrite Maximum number of data to write (this serves as a timeout * if FMAC continuously empties the input buffer). - * @retval HAL status + * @retval None */ static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite) { @@ -2191,7 +2218,7 @@ static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSi uint16_t threshold; /* Check if there is room in FMAC */ - if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0UL) + if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0U) { return; } @@ -2219,7 +2246,7 @@ static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSi WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA)); hfmac->pInput++; hfmac->InputCurrentSize++; - } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0UL); + } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0U); /* X1 buffer full flag has just be raised, read the threshold */ threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_X1_FULL_WM(hfmac)) - 1U; @@ -2348,7 +2375,7 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) else { /* Wait for the end of the writing */ - for (index = 0U; index < 0xFFU; index++) + for (index = 0U; index < MAX_PRELOAD_INDEX; index++) { if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) { @@ -2356,8 +2383,8 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) } } - /* If 'START' is still set, there was an error: set FMAC handle state to error */ - if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL) + /* If 'START' is still set, there was a timeout: set FMAC handle state to timeout */ + if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) { hfmac->State = HAL_FMAC_STATE_TIMEOUT; } @@ -2400,16 +2427,16 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma) FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Wait for the end of the X1 writing */ - for (index = 0U; index < 0xFFU; index++) + for (index = 0U; index < MAX_PRELOAD_INDEX; index++) { - if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0UL) + if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) { break; } } /* If 'START' is still set, there was an error: set FMAC handle state to error */ - if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL) + if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) { hfmac->State = HAL_FMAC_STATE_TIMEOUT; hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; @@ -2445,7 +2472,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma) /* nothing to do */ } - /* Return function status */ if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE) { /* Change the FMAC state */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.h index b6e21d7b467..1f289dd8d7d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.h @@ -2,8 +2,7 @@ ****************************************************************************** * @file stm32g4xx_hal_fmac.h * @author MCD Application Team - * @brief This file contains all the functions prototypes for the FMAC firmware - * library. + * @brief Header for stm32g4xx_hal_fmac.c module ****************************************************************************** * @attention * @@ -135,7 +134,7 @@ typedef struct #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) /** - * @brief FMAC Callback ID structure definition + * @brief FMAC Callback ID enumeration definition */ typedef enum { @@ -165,31 +164,31 @@ typedef struct { uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF). Ignored if InputBufferSize is set to 0 (previous configuration kept). - NB: the buffers can overlap or even coincide exactly. */ + Note: the buffers can overlap or even coincide exactly. */ - uint8_t InputBufferSize; /*!< Number of 16-bit addresses allocated to the input buffer (including the optional "headroom"). + uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom"). 0 if a previous configuration should be kept. */ uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces - in the buffer is inferior to this threshold. + in the buffer is lower than this threshold. This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0 (previous configuration kept). - NB: the buffers can overlap or even coincide exactly. */ + Note: the buffers can overlap or even coincide exactly. */ - uint8_t CoeffBufferSize; /*!< Number of 16-bit addresses allocated to the coefficient buffer. + uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer. 0 if a previous configuration should be kept. */ uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0 (previous configuration kept). - NB: the buffers can overlap or even coincide exactly. */ + Note: the buffers can overlap or even coincide exactly. */ - uint8_t OutputBufferSize; /*!< Number of 16-bit addresses allocated to the output buffer (including the optional "headroom"). + uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom"). 0 if a previous configuration should be kept. */ uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values - in the buffer is inferior to this threshold. + in the buffer is lower than this threshold. This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A. @@ -202,13 +201,15 @@ typedef struct uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */ - uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMT, IT, Polling, None. + uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint32_t Clip; /*!< Enable or disable the clipping feature (wrapping when the q1.15 range is exceeded). + uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping + is done when the clipping feature is disabled and saturation is done when the + clipping feature is enabled. This parameter can be a value of @ref FMAC_Clip_State. */ uint32_t Filter; /*!< Filter type. @@ -237,17 +238,17 @@ typedef struct /** @defgroup FMAC_Error_Code FMAC Error code * @{ */ -#define HAL_FMAC_ERROR_NONE 0x00000000UL /*!< No error */ -#define HAL_FMAC_ERROR_SAT 0x00000001UL /*!< Saturation error */ -#define HAL_FMAC_ERROR_UNFL 0x00000002UL /*!< Underflow error */ -#define HAL_FMAC_ERROR_OVFL 0x00000004UL /*!< Overflow error */ -#define HAL_FMAC_ERROR_DMA 0x00000008UL /*!< DMA error */ -#define HAL_FMAC_ERROR_RESET 0x00000010UL /*!< Reset error */ -#define HAL_FMAC_ERROR_PARAM 0x00000020UL /*!< Parameter error */ +#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */ +#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */ +#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */ +#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */ +#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */ +#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */ #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) -#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040UL /*!< Invalid Callback error */ +#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */ #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ -#define HAL_FMAC_ERROR_TIMEOUT 0x00000080UL /*!< Timeout error */ +#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */ /** * @} @@ -256,11 +257,11 @@ typedef struct /** @defgroup FMAC_Functions FMAC Functions * @{ */ -#define FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */ -#define FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */ -#define FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */ -#define FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */ -#define FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */ +#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ /** * @} */ @@ -269,15 +270,15 @@ typedef struct * @{ * @note This parameter sets a watermark for buffer full (input) or buffer empty (output). */ -#define FMAC_THRESHOLD_1 0x00000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. +#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */ -#define FMAC_THRESHOLD_2 0x01000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. +#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */ -#define FMAC_THRESHOLD_4 0x02000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. +#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */ -#define FMAC_THRESHOLD_8 0x03000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. +#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */ -#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFUL /*!< The configured threshold value shouldn't be changed */ +#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */ /** * @} */ @@ -286,7 +287,7 @@ typedef struct * @{ */ #define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */ -#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through the FMAC DMA */ +#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */ #define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */ #define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */ /** @@ -296,7 +297,7 @@ typedef struct /** @defgroup FMAC_Clip_State FMAC Clip State * @{ */ -#define FMAC_CLIP_DISABLED 0x00000000UL /*!< Clipping disabled */ +#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */ #define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */ /** * @} @@ -326,52 +327,13 @@ typedef struct * @} */ -/** @defgroup FMAC_DMAR DMA Read Request Enable bit - * @{ - */ -#define FMAC_DMA_REN FMAC_CR_DMAREN /*!< DMA Read Requests Enable */ -/** - * @} - */ - -/** @defgroup FMAC_DMAW DMA Write Request Enable bit - * @{ - */ -#define FMAC_DMA_WEN FMAC_CR_DMAWEN /*!< DMA Write Channel Enable */ -/** - * @} - */ - -/** @defgroup FMAC_DMAS DMA START bit - * @{ - */ -#define FMAC_START FMAC_PARAM_START /*!< DMA Start */ -/** - * @} - */ - -/** @defgroup FMAC_TimeOut_Value FMAC polling-based communications time-out value - * @{ - */ -#define HAL_FMAC_TIMEOUT_VALUE 1000UL /*!< FMAC polling-based communications time-out value */ /** * @} */ -/** @defgroup FMAC_Reset_TimeOut_Value FMAC reset time-out value - * @{ - */ -#define HAL_FMAC_RESET_TIMEOUT_VALUE 500UL /*!< FMAC reset time-out value */ -/** - * @} - */ -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup FMAC_Exported_Macros FMAC Exported Macros * @{ */ @@ -391,10 +353,10 @@ typedef struct #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ /** - * @brief Enable the FMAC interrupt when result is ready + * @brief Enable the specified FMAC interrupt * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC Interrupt. - * This parameter can be one of the following values: + * This parameter can be any combination of the following values: * @arg @ref FMAC_IT_RIEN Read interrupt enable * @arg @ref FMAC_IT_WIEN Write interrupt enable * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable @@ -409,7 +371,7 @@ typedef struct * @brief Disable the FMAC interrupt * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC Interrupt. - * This parameter can be one of the following values: + * This parameter can be any combination of the following values: * @arg @ref FMAC_IT_RIEN Read interrupt enable * @arg @ref FMAC_IT_WIEN Write interrupt enable * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable @@ -423,7 +385,7 @@ typedef struct /** @brief Check whether the specified FMAC interrupt occurred or not. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to check. - * This parameter can be one of the following values: + * This parameter can be any combination of the following values: * @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag * @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag * @arg @ref FMAC_FLAG_OVFL Overflow Error Flag @@ -445,7 +407,7 @@ typedef struct /** @brief Check whether the specified FMAC status flag is set or not. * @param __HANDLE__ FMAC handle. * @param __FLAG__ FMAC flag to check. - * This parameter can be one of the following values: + * This parameter can be any combination of the following values: * @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag * @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag * @arg @ref FMAC_FLAG_OVFL Overflow Error Flag @@ -482,7 +444,6 @@ typedef struct * @} */ -/* Private macros --------------------------------------------------------*/ /** @addtogroup FMAC_Private_Macros * @{ */ @@ -499,7 +460,7 @@ typedef struct ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) /** - * @brief Verify the FMAC load function. + * @brief Verify the FMAC load function used for input data, output data or coefficients. * @param __FUNCTION__ ID of the load function. * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid) */ @@ -508,7 +469,7 @@ typedef struct ((__FUNCTION__) == FMAC_FUNC_LOAD_Y)) /** - * @brief Verify the FMAC load function. + * @brief Verify the FMAC load function used with N values as input or output data. * @param __FUNCTION__ ID of the load function. * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid) */ @@ -516,7 +477,7 @@ typedef struct ((__FUNCTION__) == FMAC_FUNC_LOAD_Y)) /** - * @brief Verify the FMAC load function. + * @brief Verify the FMAC load function used with N + M values as coefficients. * @param __FUNCTION__ ID of the load function. * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid) */ @@ -591,6 +552,19 @@ typedef struct #define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \ ((__CLIP_STATE__) == FMAC_CLIP_ENABLED)) +/** + * @brief Check whether the threshold is applicable. + * @param __SIZE__ Size of the matching buffer. + * @param __WM__ Watermark value. + * @param __ACCESS__ Access to the buffer (polling, it, dma, none). + * @retval THRESHOLD + */ +#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \ + ((__WM__) == FMAC_THRESHOLD_2)? 2U: \ + ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \ + ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \ + ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA))) + /** * @} */ @@ -623,8 +597,8 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig); -HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig); +HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig); +HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig); HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize); HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_gpio.c index 3a8dfd36564..f9363711627 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_gpio.c @@ -188,26 +188,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if (iocurrent != 0x00u) { /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3U]; - temp &= ~(0xFU << ((position & 0x07U) * 4U)); - temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); - GPIOx->AFR[position >> 3U] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -233,6 +213,26 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) @@ -334,16 +334,16 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)); - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position); - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); } position++; @@ -432,17 +432,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { + uint32_t odr; + /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->ODR & GPIO_Pin) != 0x00u) - { - GPIOx->BRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_gpio_ex.h index cda163639fe..4f26da27473 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_gpio_ex.h @@ -82,6 +82,7 @@ extern "C" { #endif /* TIM5 */ #define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */ #define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */ #if defined(TIM20) #define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */ #endif /* TIM20 */ @@ -214,6 +215,7 @@ extern "C" { * @brief AF 9 selection */ #define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */ +#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */ #define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */ #define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */ @@ -245,6 +247,7 @@ extern "C" { #define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */ #endif /* FDCAN3 */ #define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */ #define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */ #define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */ @@ -252,7 +255,8 @@ extern "C" { * @brief AF 12 selection */ #define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ #define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ #if defined(HRTIM1) #define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c index 7aa48e8517f..b9a8fdaa286 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c @@ -793,6 +793,9 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim, SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL); } + /* Set HRTIM state */ + hhrtim->State = HAL_HRTIM_STATE_READY; + return HAL_OK; } @@ -843,6 +846,9 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim, SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL); } + /* Set HRTIM state */ + hhrtim->State = HAL_HRTIM_STATE_READY; + return HAL_OK; } @@ -1393,6 +1399,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hhrtim); + /* Set HRTIM state */ hhrtim->State = HAL_HRTIM_STATE_BUSY; @@ -1491,6 +1500,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, default: { + OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; + OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; + hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -1513,6 +1525,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Set HRTIM state */ hhrtim->State = HAL_HRTIM_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); + return HAL_OK; } @@ -2059,6 +2074,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, } default: { + OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; + OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; + hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -2693,7 +2711,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure - * @note When the timer operates in simple capture mode the capture is trigerred + * @note When the timer operates in simple capture mode the capture is triggered * by the designated external event and GPIO input is implicitly used as event source. * The cature can be triggered by a rising edge, a falling edge or both * edges on event channel. @@ -3422,6 +3440,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh default: { + OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE; + OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE; + hhrtim->State = HAL_HRTIM_STATE_ERROR; /* Process Unlocked */ @@ -3888,6 +3909,7 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, { /* Check parameters */ assert_param(IS_HRTIM_EVENT(Event)); + assert_param(IS_HRTIM_EVENTSRC(Event, pEventCfg->Source)); assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity)); assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity)); assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode)); @@ -4005,7 +4027,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, { case HRTIM_FAULT_1: { - hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK); + hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK); hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P); hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT1SRC_0_Pos); hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT1SRC_1); @@ -4017,7 +4039,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_FAULT_2: { - hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); + hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P); hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT2SRC_0_Pos); hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT2SRC_1); @@ -4029,7 +4051,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_FAULT_3: { - hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); + hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P); hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT3SRC_0_Pos); hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT3SRC_1); @@ -4041,7 +4063,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_FAULT_4: { - hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); + hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC_0 | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK); hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P); hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT4SRC_0_Pos); hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT4SRC_1); @@ -4053,7 +4075,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_FAULT_5: { - hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); + hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK); hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P); hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT5SRC_0_Pos); hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5SRC_1); @@ -4065,7 +4087,7 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, case HRTIM_FAULT_6: { - hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6P | HRTIM_FLTINR2_FLT6SRC | HRTIM_FLTINR2_FLT6F | HRTIM_FLTINR2_FLT6LCK); + hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6P | HRTIM_FLTINR2_FLT6SRC_0 | HRTIM_FLTINR2_FLT6F | HRTIM_FLTINR2_FLT6LCK); hrtim_fltinr2 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR2_FLT6P); hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT6SRC_0_Pos); hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6SRC_1); @@ -5279,8 +5301,8 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @param EventCounter external event Counter A or B for which timer event must be configured * This parameter can be one of the following values: - * @arg HRTIM_TIMEEVENT_A - * @arg HRTIM_TIMEEVENT_B + * @arg HRTIM_EVENTCOUNTER_A + * @arg HRTIM_EVENTCOUNTER_B * @param pTimerExternalEventCfg: pointer to the timer external event configuration structure * @note This function must be called before starting the timer * @retval HAL status @@ -5309,7 +5331,7 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; - if ((EventCounter & HRTIM_TIMEEVENT_A) != 0U) + if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U) { if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE) { /* reset External EventCounter A */ @@ -5327,7 +5349,7 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, } } - if ((EventCounter & HRTIM_TIMEEVENT_B) != 0U) + if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U) { if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE) { /* reset External EventCounter B */ @@ -5365,8 +5387,8 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @param EventCounter external Event Counter A or B for which timer event must be configured * This parameter can be a one of the following values: - * @arg HRTIM_TIMEEVENT_A - * @arg HRTIM_TIMEEVENT_B + * @arg HRTIM_EVENTCOUNTER_A + * @arg HRTIM_EVENTCOUNTER_B * @note This function must be called before starting the timer * @retval HAL status */ @@ -5388,11 +5410,11 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; - if ((EventCounter & HRTIM_TIMEEVENT_A) != 0U) + if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U) { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE); } - if ((EventCounter & HRTIM_TIMEEVENT_B) != 0U) + if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U) { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE); } @@ -5418,8 +5440,8 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @param EventCounter external event Counter A or B for which timer event must be configured * This parameter can be a one of the following values: - * @arg HRTIM_TIMEEVENT_A - * @arg HRTIM_TIMEEVENT_B + * @arg HRTIM_EVENTCOUNTER_A + * @arg HRTIM_EVENTCOUNTER_B * @retval HAL status */ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim, @@ -5440,12 +5462,12 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; - if ((EventCounter & HRTIM_TIMEEVENT_A) != 0U) + if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U) { CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE); } - if ((EventCounter & HRTIM_TIMEEVENT_B) != 0U) + if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U) { CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE); } @@ -5471,8 +5493,8 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_F for timer F * @param EventCounter external event Counter A or B for which timer event must be configured * This parameter can be one of the following values: - * @arg HRTIM_TIMEEVENT_A - * @arg HRTIM_TIMEEVENT_B + * @arg HRTIM_EVENTCOUNTER_A + * @arg HRTIM_EVENTCOUNTER_B * @note This function must be called before starting the timer * @retval HAL status */ @@ -5494,11 +5516,11 @@ HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim, hhrtim->State = HAL_HRTIM_STATE_BUSY; - if ((EventCounter & HRTIM_TIMEEVENT_A) != 0U) + if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U) { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACRES); } - if ((EventCounter & HRTIM_TIMEEVENT_B) != 0U) + if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U) { SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3,HRTIM_EEFR3_EEVBCRES); } @@ -6380,12 +6402,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim, * @param Timers Timer counter(s) to stop * This parameter can be any combination of the following values: * @arg HRTIM_TIMERID_MASTER - * @arg HRTIM_TIMERID_A - * @arg HRTIM_TIMERID_B - * @arg HRTIM_TIMERID_C - * @arg HRTIM_TIMERID_D - * @arg HRTIM_TIMERID_E - * @arg HRTIM_TIMERID_F + * @arg HRTIM_TIMERID_TIMER_A + * @arg HRTIM_TIMERID_TIMER_B + * @arg HRTIM_TIMERID_TIMER_C + * @arg HRTIM_TIMERID_TIMER_D + * @arg HRTIM_TIMERID_TIMER_E + * @arg HRTIM_TIMERID_TIMER_F * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled */ @@ -6418,12 +6440,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim, * @param Timers Timer counter(s) to start * This parameter can be any combination of the following values: * @arg HRTIM_TIMERID_MASTER - * @arg HRTIM_TIMERID_A - * @arg HRTIM_TIMERID_B - * @arg HRTIM_TIMERID_C - * @arg HRTIM_TIMERID_D - * @arg HRTIM_TIMERID_E - * @arg HRTIM_TIMERID_F + * @arg HRTIM_TIMERID_TIMER_A + * @arg HRTIM_TIMERID_TIMER_B + * @arg HRTIM_TIMERID_TIMER_C + * @arg HRTIM_TIMERID_TIMER_D + * @arg HRTIM_TIMERID_TIMER_E + * @arg HRTIM_TIMERID_TIMER_F * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related * to the timers to start are enabled within this function. * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig @@ -6483,12 +6505,12 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim, * @param Timers Timer counter(s) to stop * This parameter can be any combination of the following values: * @arg HRTIM_TIMERID_MASTER - * @arg HRTIM_TIMERID_A - * @arg HRTIM_TIMERID_B - * @arg HRTIM_TIMERID_C - * @arg HRTIM_TIMERID_D - * @arg HRTIM_TIMERID_E - * @arg HRTIM_TIMERID_F + * @arg HRTIM_TIMERID_TIMER_A + * @arg HRTIM_TIMERID_TIMER_B + * @arg HRTIM_TIMERID_TIMER_C + * @arg HRTIM_TIMERID_TIMER_D + * @arg HRTIM_TIMERID_TIMER_E + * @arg HRTIM_TIMERID_TIMER_F * @retval HAL status * @note The counter of a timer is stopped only if all timer outputs are disabled * @note All enabled timer related interrupts are disabled. @@ -6560,7 +6582,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERID_TIMER_E * @arg HRTIM_TIMERID_TIMER_F * @retval HAL status - * @note This function enables the dma request(s) mentionned in the timer + * @note This function enables the dma request(s) mentioned in the timer * configuration data structure for every timers to start. * @note The source memory address, the destination memory address and the * size of each DMA transfer are specified at timer configuration time @@ -6907,7 +6929,7 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERUPDATE_E * @arg HRTIM_TIMERUPDATE_F * @retval HAL status - * @note The 'software update' bits in the HRTIM conrol register 2 register are + * @note The 'software update' bits in the HRTIM control register 2 register are * automatically reset by hardware */ HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, @@ -6991,7 +7013,7 @@ HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERRESET_TIMER_E * @arg HRTIM_TIMERRESET_TIMER_F * @retval HAL status - * @note The 'software reset' bits in the HRTIM conrol register 2 are + * @note The 'software reset' bits in the HRTIM control register 2 are * automatically reset by hardware */ HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim, @@ -7697,7 +7719,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET) { - /* Output is enabled: output in RUN state (whatever ouput disable status is)*/ + /* Output is enabled: output in RUN state (whatever output disable status is)*/ output_state = HRTIM_OUTPUTSTATE_RUN; } else @@ -9177,7 +9199,7 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, hrtim_mcr &= ~(HRTIM_MCR_DACSYNC); hrtim_mcr |= pTimerCfg->DACSynchro; - /* Enable/Disable preload meachanism for timer registers */ + /* Enable/Disable preload mechanism for timer registers */ hrtim_mcr &= ~(HRTIM_MCR_PREEN); hrtim_mcr |= pTimerCfg->PreloadEnable; @@ -9262,7 +9284,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC); hrtim_timcr |= pTimerCfg->DACSynchro; - /* Enable/Disable preload meachanism for timer registers */ + /* Enable/Disable preload mechanism for timer registers */ hrtim_timcr &= ~(HRTIM_TIMCR_PREEN); hrtim_timcr |= pTimerCfg->PreloadEnable; @@ -9398,9 +9420,6 @@ static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim, { uint32_t hrtim_timcr2; - /* UPDGAT bitfield must be reset before programming a new value */ - hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT); - /* Configure timing unit (Timer A to Timer F) */ hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.h index 086ec4f8683..7e6e92b5513 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.h @@ -951,17 +951,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @} */ -/** @defgroup HRTIM_Timer_Rsync_Update_Enable HRTIM Re-Synchronized Update - * @{ - * @brief Constants defining whether the update source coming outside from the timing unit must be synchronized - - */ -#define HRTIM_RSYNCUPDATE_DISABLE 0x00000000U /*!< The update is taken into account immediately */ -#define HRTIM_RSYNCUPDATE_ENABLE (HRTIM_TIMCR_RSYNCU) /*!< The update is taken into account on the following Reset/Roll-over event. */ -/** - * @} - */ - /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update * @{ * @brief Constants defining whether registers are updated when the timer @@ -1148,7 +1137,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_TIM_ADROM_BOTH 0x00000000U /*!< Roll-over event which triggers */ #define HRTIM_TIM_ADROM_CREST (HRTIM_TIMCR2_ADROM_1) /*!< the */ #define HRTIM_TIM_ADROM_VALLEY (HRTIM_TIMCR2_ADROM_0) /*!< ADC */ -#define HRTIM_TIM_OUTROM_BOTH 0x00000000U /*!< Roll-over event which sets and/or resets the ouputs */ +#define HRTIM_TIM_OUTROM_BOTH 0x00000000U /*!< Roll-over event which sets and/or resets the outputs */ #define HRTIM_TIM_OUTROM_CREST (HRTIM_TIMCR2_OUTROM_1) /*!< as per HRTIM_SETxyR */ #define HRTIM_TIM_OUTROM_VALLEY (HRTIM_TIMCR2_OUTROM_0) /*!< and HRTIM_RSTxyR settings */ #define HRTIM_TIM_ROM_BOTH 0x00000000U /*!< Roll-over event with the following destinations: IRQ and DMA requests,*/ @@ -1200,7 +1189,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @{ * @brief Constants defining the polarity of a timer output */ -#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is acitve HIGH */ +#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is active HIGH */ #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */ /** * @} @@ -1244,8 +1233,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ /* Timer Events mapping for Timer C */ -#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ @@ -1268,7 +1257,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ @@ -1336,8 +1325,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ /* Timer Events mapping for Timer C */ -#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ @@ -1360,7 +1349,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ @@ -1599,18 +1588,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @{ * @brief Constants defining the External Event Counter A or B */ -#define HRTIM_TIMEEVENT_A (HRTIM_EEFR3_EEVACE) /*!< External Event Counter A */ -#define HRTIM_TIMEEVENT_B (HRTIM_EEFR3_EEVBCE) /*!< External Event Counter B */ -/** - * @} - */ - -/** @defgroup HRTIM_Timer_External_Event_Counter HRTIM Timer External Event Counter - * @{ - * @brief Constants enabling the External Event A or B Counter - */ -#define HRTIM_TIMEEVENTCOUNTER_DISABLED (0x00000000U) /*!< External Event Counter disabled */ -#define HRTIM_TIMEEVENTCOUNTER_ENABLED (0x00000001U) /*!< External Event Counter enabled */ +#define HRTIM_EVENTCOUNTER_A (HRTIM_EEFR3_EEVACE) /*!< External Event Counter A */ +#define HRTIM_EVENTCOUNTER_B (HRTIM_EEFR3_EEVBCE) /*!< External Event Counter B */ /** * @} */ @@ -1619,9 +1598,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @{ * @brief Constants enabling the External Event Counter A or B Reset Mode */ -#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL (0x00000000U) /*!< External Event Counter is reset on each reset / roll-over event */ -#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL (0x00000001U) /*!< External Event Counter is reset on each reset / roll-over event only - if no event occurs during last counting period */ +#define HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL (0x00000000U) /*!< External Event Counter is reset on each reset / roll-over event */ +#define HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL (0x00000001U) /*!< External Event Counter is reset on each reset / roll-over event only + if no event occurs during last counting period */ /** * @} */ @@ -1966,20 +1945,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @} */ -/** @defgroup HRTIM_Fault_Input_Sources HRTIM Fault Input Sources - * @{ - * @brief Constants defining the fault input for a Fault channel - */ -#define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_0 /*!< bit 0 of the source input for Fault channel 1 */ -#define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_0 /*!< bit 0 of the source input for Fault channel 2 */ -#define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_0 /*!< bit 0 of the source input for Fault channel 3 */ -#define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_0 /*!< bit 0 of the source input for Fault channel 4 */ -#define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_0 /*!< bit 0 of the source input for Fault channel 5 */ -#define HRTIM_FLTINR2_FLT6SRC HRTIM_FLTINR2_FLT6SRC_0 /*!< bit 0 of the source input for Fault channel 6 */ -/** - * @} - */ - /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity * @{ * @brief Constants defining the polarity of a fault event @@ -2368,7 +2333,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @{ * @brief Constants defining the DLL calibration periods (in micro seconds) */ -#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */ +#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */ #define HRTIM_CALIBRATIONRATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */ #define HRTIM_CALIBRATIONRATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */ #define HRTIM_CALIBRATIONRATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */ @@ -2755,16 +2720,12 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((OUTPUT) == HRTIM_OUTPUT_TF2)))) #define IS_HRTIM_TIMEEVENT(EVENT)\ - (((EVENT) == HRTIM_TIMEEVENT_A) || \ - ((EVENT) == HRTIM_TIMEEVENT_B)) - -#define IS_HRTIM_TIMEEVENT_ENABLE(EVENT)\ - (((EVENT) == HRTIM_TIMEEVENTCOUNTER_ENABLED) || \ - ((EVENT) == HRTIM_TIMEEVENTCOUNTER_DISABLED)) + (((EVENT) == HRTIM_EVENTCOUNTER_A) || \ + ((EVENT) == HRTIM_EVENTCOUNTER_B)) #define IS_HRTIM_TIMEEVENT_RESETMODE(EVENT)\ - (((EVENT) == HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL) || \ - ((EVENT) == HRTIM_TIMEEVENTRESETMODE_CONDITIONAL)) + (((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL) || \ + ((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL)) #define IS_HRTIM_TIMSYNCUPDATE(EVENT)\ (((EVENT) == HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL) || \ @@ -2830,10 +2791,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_QUAD)) -#define IS_HRTIM_RESYNCUPDATE(RSYNCUPDATE)\ - (((RSYNCUPDATE) == HRTIM_RSYNCUPDATE_DISABLE) || \ - ((RSYNCUPDATE) == HRTIM_RSYNCUPDATE_ENABLE)) - #define IS_HRTIM_SYNCSTART(SYNCSTART)\ (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) @@ -3361,47 +3318,66 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) -#define IS_HRTIM_EVENTSRC(EVENTSRC)\ - (((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \ - ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \ - ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \ - ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \ - ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \ - ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \ - ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \ - ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \ - ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ) || \ - ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ) || \ - ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ) || \ - ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ) || \ - ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ) || \ - ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ) || \ - ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ) || \ - ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ) || \ - ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ) || \ - ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1)) +#define IS_HRTIM_EVENTSRC(EVENT, EVENTSRC) \ + ((((EVENT) == HRTIM_EVENT_1) && \ + (((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \ + ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_2) && \ + (((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \ + ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_3) && \ + (((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \ + ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_4) && \ + (((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_5) && \ + (((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_6) && \ + (((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_7) && \ + (((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \ + ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_8) && \ + (((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ))) \ + || \ + (((EVENT) == HRTIM_EVENT_9) && \ + (((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \ + ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \ + ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ))) \ + || \ + (((EVENT) == HRTIM_EVENT_10) && \ + (((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \ + ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \ + ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \ + ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1)))) #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ @@ -3627,26 +3603,20 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F)) #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ - (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \ + (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1) || \ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2) || \ ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3)) -#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ - ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U))) +#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ + ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U))) #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ @@ -3946,15 +3916,15 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier * @param Event external event Counter A or B for which timer event must be enabled * This parameter can be one of the following values: - * @arg HRTIM_TIMEEVENT_A - * @arg HRTIM_TIMEEVENT_B + * @arg HRTIM_EVENTCOUNTER_A + * @arg HRTIM_EVENTCOUNTER_B * @retval None */ #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_ENABLE(__HANDLE__, __TIMER__, __EVENT__)\ do {\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ }\ @@ -3965,55 +3935,55 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ }\ @@ -4032,74 +4002,74 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier * @param Event external event A or B for which timer event must be disabled * This parameter can be one of the following values: - * @arg HRTIM_TIMEEVENT_A - * @arg HRTIM_TIMEEVENT_B + * @arg HRTIM_EVENTCOUNTER_A + * @arg HRTIM_EVENTCOUNTER_B * @retval None */ #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_DISABLE(__HANDLE__, __TIMER__, __EVENT__)\ do {\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ }\ @@ -4118,74 +4088,74 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier * @param Event external event A or B for which timer event must be reset * This parameter can be one of the following values: - * @arg HRTIM_TIMEEVENT_A - * @arg HRTIM_TIMEEVENT_B + * @arg HRTIM_EVENTCOUNTER_A + * @arg HRTIM_EVENTCOUNTER_B * @retval None */ #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_RESET(__HANDLE__, __TIMER__, __EVENT__)\ do {\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ }\ }\ if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ {\ - if (((__EVENT__) & HRTIM_TIMEEVENT_A) == HRTIM_TIMEEVENT_A)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ }\ - if (((__EVENT__) & HRTIM_TIMEEVENT_B) == HRTIM_TIMEEVENT_B)\ + if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ {\ ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ }\ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.c index bd3eac9ad1d..b5a79be7002 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.c @@ -93,7 +93,7 @@ [..] (+) A specific option field manage the different steps of a sequential transfer (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address @@ -112,7 +112,7 @@ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential interface. @@ -122,7 +122,7 @@ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. - (+) Differents sequential I2C interfaces are listed below: + (+) Different sequential I2C interfaces are listed below: (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA() (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can @@ -223,12 +223,12 @@ *** Callback registration *** ============================================= - + [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() to register an interrupt callback. - + [..] Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. @@ -243,9 +243,9 @@ (+) MspDeInitCallback : callback for Msp DeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - + [..] For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). - + [..] Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, @@ -262,9 +262,9 @@ (+) AbortCpltCallback : callback for abort completion process. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. - + [..] For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). - + [..] By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). @@ -273,7 +273,7 @@ these callbacks are null (not registered beforehand). If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - + [..] Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, @@ -281,7 +281,7 @@ Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() or @ref HAL_I2C_Init() function. - + [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -351,13 +351,13 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -390,8 +390,10 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); /* Private functions for I2C transfer IRQ handler */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); @@ -400,7 +402,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); @@ -410,11 +413,15 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); /* Private function to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); @@ -429,8 +436,8 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -669,7 +676,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -974,8 +982,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -1057,7 +1065,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1171,7 +1180,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1547,7 +1557,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1783,7 +1794,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -1926,7 +1938,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -2277,7 +2290,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2369,8 +2383,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2412,7 +2425,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2504,8 +2518,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2545,7 +2558,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2636,7 +2650,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2726,7 +2741,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2870,7 +2886,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param Size Amount of data to be read * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -3121,8 +3138,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Increment Trials */ I2C_Trials++; - } - while (I2C_Trials < Trials); + } while (I2C_Trials < Trials); /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; @@ -3153,7 +3169,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3200,7 +3217,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3237,7 +3254,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3285,7 +3303,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3399,7 +3417,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3446,7 +3465,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3483,7 +3502,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3531,7 +3551,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3643,7 +3663,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3738,7 +3759,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -3917,7 +3939,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4012,7 +4035,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -4251,9 +4275,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; @@ -4285,8 +4321,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA */ /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /** * @brief This function handles I2C event interrupt request. @@ -4524,8 +4560,8 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * + * @brief Peripheral State, Mode and Error functions + * @verbatim =============================================================================== ##### Peripheral State, Mode and Error functions ##### @@ -4562,11 +4598,11 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) } /** -* @brief Return the I2C error code. + * @brief Return the I2C error code. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ + * @retval I2C Error Code + */ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; @@ -4737,6 +4773,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Process locked */ __HAL_LOCK(hi2c); + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ @@ -4745,7 +4788,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); @@ -4788,9 +4832,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { if (hi2c->XferCount > 0U) { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; @@ -4808,7 +4849,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint I2C_ITSlaveSeqCplt(hi2c); } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, tmpITFlags); } @@ -4816,7 +4858,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ + /* Check if all data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) { @@ -4844,13 +4886,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Nothing to do */ } - /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, tmpITFlags); - } - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5004,10 +5039,18 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ @@ -5043,7 +5086,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin if (treatdmanack == 1U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); @@ -5075,8 +5119,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -5092,11 +5152,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { I2C_ITAddrCplt(hi2c, ITFlags); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } else { /* Nothing to do */ @@ -5120,7 +5175,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -5173,7 +5229,8 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); @@ -5370,9 +5427,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ @@ -5427,19 +5502,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5448,12 +5540,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; @@ -5467,6 +5564,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5501,6 +5599,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5547,12 +5646,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5566,6 +5679,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if (hi2c->hdmatx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); @@ -5573,6 +5689,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if (hi2c->hdmarx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); @@ -5609,7 +5728,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5627,11 +5745,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ I2C_ITSlaveSeqCplt(hi2c); hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5647,6 +5766,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5661,6 +5781,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5734,6 +5855,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -5753,7 +5875,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else @@ -5761,23 +5882,27 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - /* If state is an abort treatment on goind, don't change state */ + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } - if (hi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5793,13 +5918,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } - if (hi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5815,10 +5948,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else + { + I2C_TreatErrorCallback(hi2c); } - else if (hi2c->State == HAL_I2C_STATE_ABORT) +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5832,6 +5983,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } else { + hi2c->PreviousState = I2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -6042,30 +6195,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->hdmatx != NULL) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmatx->XferAbortCallback = NULL; } - else + if (hi2c->hdmarx != NULL) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmarx->XferAbortCallback = NULL; } + + I2C_TreatErrorCallback(hi2c); } /** @@ -6078,7 +6217,8 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { @@ -6310,7 +6450,8 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -6318,8 +6459,11 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin assert_param(IS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hi2c->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** @@ -6342,19 +6486,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6380,7 +6524,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; @@ -6434,19 +6578,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6459,7 +6603,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) } /** - * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. * @param hi2c I2C handle. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.h index 158d2d06c0c..14d7dc5bedc 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.h @@ -495,7 +495,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified I2C flag is set or not. * @param __HANDLE__ specifies the I2C Handle. @@ -521,7 +522,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval The new state of __FLAG__ (SET or RESET). */ #define I2C_FLAG_MASK (0x0001FFFFU) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the I2C Handle. @@ -541,7 +543,7 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval None */ #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. @@ -583,7 +585,8 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); @@ -598,49 +601,70 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); /******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); /** * @} */ /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -732,7 +756,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) #define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) #define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) @@ -743,13 +768,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c_ex.c index ca37d849f36..2d7043de9c3 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c_ex.c @@ -73,7 +73,7 @@ /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c_ex.h index 68a443d410a..4f7686e8f93 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c_ex.h @@ -38,7 +38,6 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ - /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants * @{ */ @@ -77,24 +76,51 @@ extern "C" { */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions * @{ */ - /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions + * @{ + */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions + * @{ + */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + + +/** + * @} + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants @@ -110,7 +136,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) @@ -144,14 +170,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.c index 8d497e36245..bacad7d2d0e 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.c @@ -90,6 +90,10 @@ (+) Pause the DMA Transfer using HAL_I2S_DMAPause() (+) Resume the DMA Transfer using HAL_I2S_DMAResume() (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error + HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data. + In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data + inside DR register and avoid using DeInit/Init process for the next transfer. *** I2S HAL driver macros list *** =================================== @@ -101,6 +105,7 @@ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data [..] (@) You can refer to the I2S HAL driver header file for more useful macros @@ -195,6 +200,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -332,7 +338,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /* I2S standard */ if (hi2s->Init.Standard <= I2S_STANDARD_LSB) { - /* In I2S standard packet lenght is multiplied by 2 */ + /* In I2S standard packet length is multiplied by 2 */ packetlength = packetlength * 2U; } @@ -1350,35 +1356,86 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() */ - /* Disable the I2S Tx/Rx DMA requests */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Abort the I2S DMA tx Stream/Channel */ - if (hi2s->hdmatx != NULL) + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) { - /* Disable the I2S DMA tx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - errorcode = HAL_ERROR; + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + + /* Wait until BSY flag is Reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear UDR flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Disable the I2S Tx DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } - /* Abort the I2S DMA rx Stream/Channel */ - if (hi2s->hdmarx != NULL) + else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)) { - /* Disable the I2S DMA rx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) + { + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear OVR flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Disable the I2S Rx DMA request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + + if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX) { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; errorcode = HAL_ERROR; } + else + { + /* Read DR to Flush RX Data */ + READ_REG((hi2s->Instance)->DR); + } } - /* Disable I2S peripheral */ - __HAL_I2S_DISABLE(hi2s); - hi2s->State = HAL_I2S_STATE_READY; return errorcode; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.h index 8cf3be7f41f..24a3d999619 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.h @@ -174,6 +174,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ /** * @} */ @@ -380,6 +381,15 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to tmpreg_udr = ((__HANDLE__)->Instance->SR);\ UNUSED(tmpreg_udr); \ }while(0U) +/** @brief Flush the I2S DR Register. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ + __IO uint32_t tmpreg_dr = 0x00U;\ + tmpreg_dr = ((__HANDLE__)->Instance->DR);\ + UNUSED(tmpreg_dr); \ + }while(0U) /** * @} */ @@ -462,7 +472,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); */ /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of I2S SR regsiter. + * @param __SR__ copy of I2S SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag @@ -477,7 +487,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of I2S CR2 regsiter. + * @param __CR2__ copy of I2S CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.c index d1cdaa56637..953cd027761 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.c @@ -40,7 +40,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), the normal or low power mode and the clock prescaler in the hirda handle Init structure. @@ -612,43 +613,45 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD switch (CallbackID) { case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : - hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_IRDA_TX_COMPLETE_CB_ID : - hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : - hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_IRDA_RX_COMPLETE_CB_ID : - hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_IRDA_ERROR_CB_ID : - hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_IRDA_ABORT_COMPLETE_CB_ID : - hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : - hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : - hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -771,13 +774,16 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Transfer is kept ongoing on IRDA side. If user wants to abort it, Abort services should be called by user. (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, and + HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -815,7 +821,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->gState = HAL_IRDA_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hirda->TxXferSize = Size; @@ -905,7 +911,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hirda->RxXferSize = Size; @@ -1280,7 +1286,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1380,7 +1386,8 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Tx request if enabled */ @@ -1578,7 +1585,8 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) uint32_t abortcplt = 1U; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised @@ -2322,7 +2330,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) /* Initialize the IRDA ErrorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -2377,7 +2385,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.h index edf22f57a08..7190535f17d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.h @@ -78,7 +78,8 @@ typedef struct /** * @brief HAL IRDA State definition - * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition). + * @note HAL IRDA State value is a combination of 2 different substates: + * gState and RxState (see @ref IRDA_State_Definition). * - gState contains IRDA state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -248,7 +249,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer Value is allowed for RxState only */ #define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Value is result of combination (Or) between + gState and RxState values */ #define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error @@ -571,9 +573,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__ specifies the IRDA Handle. @@ -587,10 +594,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) - +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -606,8 +617,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -621,9 +632,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ + & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ + & ((uint32_t)0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.c index d51539d9b7f..e4f887fcb8b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.c @@ -143,7 +143,7 @@ @endverbatim ****************************************************************************** - * @attention + * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

@@ -152,7 +152,8 @@ * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** + * + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -173,13 +174,21 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Constants + * @{ + */ #define TIMEOUT 1000UL /* Timeout is 1s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); /* Exported functions --------------------------------------------------------*/ @@ -226,17 +235,20 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); } + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); + } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); @@ -269,13 +281,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); + } + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); } /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ @@ -289,18 +305,28 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UpdateMode | hlptim->Init.CounterSource); - if (((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) || ((hlptim->Init.CounterSource) == LPTIM_COUNTERSOURCE_EXTERNAL)) + /* Glitch filters for internal triggers and external inputs are configured + * only if an internal clock source is provided to the LPTIM + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + tmpcfgr |= (hlptim->Init.Trigger.SampleTime | hlptim->Init.UltraLowPowerClock.SampleTime); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + /* Configure the active edge or edges used by the counter only if LPTIM is + * clocked by an external clock source + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + { + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + } + + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge | - hlptim->Init.Trigger.SampleTime); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge); } /* Write to LPTIMx CFGR */ @@ -343,6 +369,11 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) /* Disable the LPTIM Peripheral Clock */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) if (hlptim->MspDeInitCallback == NULL) { @@ -451,12 +482,30 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -483,6 +532,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -512,6 +566,41 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -534,12 +623,6 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -566,6 +649,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -617,12 +705,30 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -649,6 +755,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -678,6 +789,41 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -700,12 +846,6 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -732,6 +872,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -783,12 +928,30 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -815,6 +978,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -844,6 +1012,41 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -866,12 +1069,6 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -898,6 +1095,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -963,9 +1165,18 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -992,6 +1203,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; @@ -1039,6 +1255,29 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set ENC bit to enable the encoder interface */ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable "switch to down direction" interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); @@ -1048,9 +1287,6 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1077,6 +1313,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; @@ -1120,12 +1361,30 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1152,6 +1411,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; @@ -1189,18 +1453,47 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Enable Compare match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1230,6 +1523,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; @@ -1271,9 +1569,18 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1300,6 +1607,11 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -1335,6 +1647,29 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; } + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -1344,9 +1679,6 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1376,12 +1708,16 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -1978,16 +2314,40 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +/** + * @brief LPTimer Wait for flag set + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param flag The lptim flag + * @retval HAL status + */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +{ + HAL_StatusTypeDef result = HAL_OK; + uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); + do + { + count--; + if (count == 0UL) + { + result = HAL_TIMEOUT; + } + } + while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + + return result; +} + /** * @brief Disable LPTIM HW instance. - * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains * the configuration information for LPTIM module. * @note The following sequence is required to solve LPTIM disable HW limitation. * Please check Errata Sheet ES0335 for more details under "MCU may remain * stuck in LPTIM interrupt when entering Stop mode" section. * @retval None */ -void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) { uint32_t tmpclksource = 0; uint32_t tmpIER; @@ -2000,95 +2360,91 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) /*********** Save LPTIM Config ***********/ /* Save LPTIM source clock */ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); - break; - default: - break; + case LPTIM1_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); + break; + default: + break; } /* Save LPTIM configuration registers */ - tmpIER = lptim->Instance->IER; - tmpCFGR = lptim->Instance->CFGR; - tmpCMP = lptim->Instance->CMP; - tmpARR = lptim->Instance->ARR; - tmpOR = lptim->Instance->OR; + tmpIER = hlptim->Instance->IER; + tmpCFGR = hlptim->Instance->CFGR; + tmpCMP = hlptim->Instance->CMP; + tmpARR = hlptim->Instance->ARR; + tmpOR = hlptim->Instance->OR; /*********** Reset LPTIM ***********/ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_FORCE_RESET(); - __HAL_RCC_LPTIM1_RELEASE_RESET(); - break; - default: - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_FORCE_RESET(); + __HAL_RCC_LPTIM1_RELEASE_RESET(); + break; + default: + break; } /*********** Restore LPTIM Config ***********/ - uint32_t Ref_Time; - uint32_t Time_Elapsed; - if ((tmpCMP != 0UL) || (tmpARR != 0UL)) { /* Force LPTIM source kernel clock from APB */ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); - break; - default: - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); + break; + default: + break; } if (tmpCMP != 0UL) { /* Restore CMP register (LPTIM should be enabled first) */ - lptim->Instance->CR |= LPTIM_CR_ENABLE; - lptim->Instance->CMP = tmpCMP; - /* Polling on CMP write ok status after above restore operation */ - Ref_Time = HAL_GetTick(); - do - { - Time_Elapsed = HAL_GetTick() - Ref_Time; - } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_CMPOK))) && (Time_Elapsed <= TIMEOUT)); + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->CMP = tmpCMP; - __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_CMPOK); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); } if (tmpARR != 0UL) { /* Restore ARR register (LPTIM should be enabled first) */ - lptim->Instance->CR |= LPTIM_CR_ENABLE; - lptim->Instance->ARR = tmpARR; - /* Polling on ARR write ok status after above restore operation */ - Ref_Time = HAL_GetTick(); - do + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->ARR = tmpARR; + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) { - Time_Elapsed = HAL_GetTick() - Ref_Time; - } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_ARROK))) && (Time_Elapsed <= TIMEOUT)); + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } - __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_ARROK); + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); } /* Restore LPTIM source kernel clock */ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(tmpclksource); - break; - default: - break; + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(tmpclksource); + break; + default: + break; } } /* Restore configuration registers (LPTIM should be disabled first) */ - lptim->Instance->CR &= ~(LPTIM_CR_ENABLE); - lptim->Instance->IER = tmpIER; - lptim->Instance->CFGR = tmpCFGR; - lptim->Instance->OR = tmpOR; + hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE); + hlptim->Instance->IER = tmpIER; + hlptim->Instance->CFGR = tmpCFGR; + hlptim->Instance->OR = tmpOR; __enable_irq(); } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.h index e3bfd5547d8..d5bb1664b89 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.h @@ -4,7 +4,7 @@ * @author MCD Application Team * @brief Header file of LPTIM HAL module. ****************************************************************************** - * @attention + * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

@@ -13,7 +13,8 @@ * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** + * + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -411,6 +412,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @note The following sequence is required to solve LPTIM disable HW limitation. * Please check Errata Sheet ES0335 for more details under "MCU may remain * stuck in LPTIM interrupt when entering Stop mode" section. + * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to + * check for TIMEOUT. * @retval None */ #define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) @@ -447,6 +450,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value * @retval None + * @note The ARR register can only be modified when the LPTIM instance is enabled. */ #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) @@ -455,6 +459,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @param __HANDLE__ LPTIM handle * @param __VALUE__ Compare value * @retval None + * @note The CMP register can only be modified when the LPTIM instance is enabled. */ #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) @@ -503,6 +508,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. + * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled. */ #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) @@ -519,6 +525,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. + * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled. */ #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) @@ -572,6 +579,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @{ */ +/** @addtogroup LPTIM_Exported_Functions_Group1 + * @brief Initialization and Configuration functions. + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); @@ -579,7 +590,14 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); /* MSP functions *************************************************************/ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ +/** @addtogroup LPTIM_Exported_Functions_Group2 + * @brief Start-Stop operation functions. + * @{ + */ /* Start/Stop operation functions *********************************************/ /* ################################# PWM Mode ################################*/ /* Blocking mode: Polling */ @@ -628,12 +646,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ +/** @addtogroup LPTIM_Exported_Functions_Group3 + * @brief Read operation functions. + * @{ + */ /* Reading operation functions ************************************************/ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ +/** @addtogroup LPTIM_Exported_Functions_Group4 + * @brief LPTIM IRQ handler and callback functions. + * @{ + */ /* LPTIM IRQ functions *******************************************************/ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); @@ -651,9 +683,19 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +/** + * @} + */ +/** @addtogroup LPTIM_Group5 + * @brief Peripheral State functions. + * @{ + */ /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ /** * @} @@ -745,7 +787,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); ((__TRIG__) == LPTIM_TRIGSOURCE_7) || \ ((__TRIG__) == LPTIM_TRIGSOURCE_8) || \ ((__TRIG__) == LPTIM_TRIGSOURCE_9)) -#endif /* STM32G473xx || STM32G483xx ||STM32G474xx || STM32G484xx */ +#endif /* STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */ #define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \ ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \ @@ -807,7 +849,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @defgroup LPTIM_Private_Functions LPTIM Private Functions * @{ */ -void LPTIM_Disable(LPTIM_HandleTypeDef *lptim); +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.h index 7f7e36a844d..4edf511d107 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.h @@ -90,10 +90,10 @@ typedef struct typedef struct { uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.c index d77d4a0d4ec..d43b127836c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.c @@ -128,7 +128,7 @@ (++) Select the mode (++) Select the inverting input (++) Select the non-inverting input - (++) Select if the internal ouput should be enabled/disabled (if enabled, regular I/O output is disabled) + (++) Select if the internal output should be enabled/disabled (if enabled, regular I/O output is disabled) (++) Select if the Timer controlled Mux is disabled or enabled and controlled by specified timer(s) (++) If the Timer controlled Mux mode is enabled, select the secondary inverting input (++) If the Timer controlled Mux mode is enabled, Select the secondary non-inverting input @@ -813,7 +813,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP); /* Self calibration is successful */ - /* Store calibration(user timming) results in init structure. */ + /* Store calibration(user timing) results in init structure. */ /* Write calibration result N */ hopamp->Init.TrimmingValueN = trimmingvaluen; @@ -821,7 +821,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp) /* Write calibration result P */ hopamp->Init.TrimmingValueP = trimmingvaluep; - /* Select user timming mode */ + /* Select user timing mode */ /* And updated with calibrated settings */ hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER; MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep << OPAMP_INPUT_NONINVERTING); @@ -1010,7 +1010,7 @@ OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, oldtrimmingvaluen = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING; } - /* Set factory timming mode */ + /* Set factory timing mode */ CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM); /* Get factory trimming */ @@ -1048,8 +1048,8 @@ OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, * @param hopamp : OPAMP handle * @param CallbackID : ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MspInit callback ID - * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MspDeInit callback ID + * @arg @ref HAL_OPAMP_MSPINIT_CB_ID OPAMP MspInit callback ID + * @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MspDeInit callback ID * @param pCallback : pointer to the Callback function * @retval status */ @@ -1070,10 +1070,10 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OP { switch (CallbackId) { - case HAL_OPAMP_MSP_INIT_CB_ID : + case HAL_OPAMP_MSPINIT_CB_ID : hopamp->MspInitCallback = pCallback; break; - case HAL_OPAMP_MSP_DEINIT_CB_ID : + case HAL_OPAMP_MSPDEINIT_CB_ID : hopamp->MspDeInitCallback = pCallback; break; default : @@ -1086,10 +1086,10 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OP { switch (CallbackId) { - case HAL_OPAMP_MSP_INIT_CB_ID : + case HAL_OPAMP_MSPINIT_CB_ID : hopamp->MspInitCallback = pCallback; break; - case HAL_OPAMP_MSP_DEINIT_CB_ID : + case HAL_OPAMP_MSPDEINIT_CB_ID : hopamp->MspDeInitCallback = pCallback; break; default : @@ -1115,8 +1115,8 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OP * @param hopamp : OPAMP handle * @param CallbackID : ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_OPAMP_MSP_INIT_CB_ID OPAMP MSP Init Callback ID - * @arg @ref HAL_OPAMP_MSP_DEINIT_CB_ID OPAMP MSP DeInit Callback ID + * @arg @ref HAL_OPAMP_MSPINIT_CB_ID OPAMP MSP Init Callback ID + * @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MSP DeInit Callback ID * @arg @ref HAL_OPAMP_ALL_CB_ID OPAMP All Callbacks * @retval status */ @@ -1132,10 +1132,10 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_ { switch (CallbackId) { - case HAL_OPAMP_MSP_INIT_CB_ID : + case HAL_OPAMP_MSPINIT_CB_ID : hopamp->MspInitCallback = HAL_OPAMP_MspInit; break; - case HAL_OPAMP_MSP_DEINIT_CB_ID : + case HAL_OPAMP_MSPDEINIT_CB_ID : hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; break; case HAL_OPAMP_ALL_CB_ID : @@ -1152,10 +1152,10 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_ { switch (CallbackId) { - case HAL_OPAMP_MSP_INIT_CB_ID : + case HAL_OPAMP_MSPINIT_CB_ID : hopamp->MspInitCallback = HAL_OPAMP_MspInit; break; - case HAL_OPAMP_MSP_DEINIT_CB_ID : + case HAL_OPAMP_MSPDEINIT_CB_ID : hopamp->MspDeInitCallback = HAL_OPAMP_MspDeInit; break; default : diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.h index 8f185c07432..31050a32c54 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.h @@ -172,8 +172,8 @@ typedef uint32_t OPAMP_TrimmingValueTypeDef; */ typedef enum { - HAL_OPAMP_MSP_INIT_CB_ID = 0x01UL, /*!< OPAMP MspInit Callback ID */ - HAL_OPAMP_MSP_DEINIT_CB_ID = 0x02UL, /*!< OPAMP MspDeInit Callback ID */ + HAL_OPAMP_MSPINIT_CB_ID = 0x01UL, /*!< OPAMP MspInit Callback ID */ + HAL_OPAMP_MSPDEINIT_CB_ID = 0x02UL, /*!< OPAMP MspDeInit Callback ID */ HAL_OPAMP_ALL_CB_ID = 0x03UL /*!< OPAMP All ID */ } HAL_OPAMP_CallbackIDTypeDef; @@ -203,18 +203,18 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); */ #define OPAMP_NONINVERTINGINPUT_IO0 (0x00000000UL) /*!< Non inverting input connected to I/O VINP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define OPAMP_NONINVERTINGINPUT_IO1 OPAMP_CSR_VPSEL_0 /*!< Non inverting input connected to I/O VINP1 (PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< Non inverting input connected to I/O VINP2 (PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL /*!< Non inverting input connected to I/O VINP3 (PD14 for OPAMP2) */ #define OPAMP_NONINVERTINGINPUT_DAC OPAMP_CSR_VPSEL /*!< Non inverting input connected internally to DAC channel (DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ /** * @} */ @@ -224,10 +224,10 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); */ #define OPAMP_INVERTINGINPUT_IO0 (0x00000000UL) /*!< Inverting input connected to I/O VINM0 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< Inverting input connected to I/0 VINM1 (PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ /** * @} */ @@ -243,7 +243,7 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); #define OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 OPAMP_TCMR_T8CMEN /*!< Timer controlled Mux mode enabled using TIM8 OC6 */ #if defined(TIM20) #define OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6 OPAMP_TCMR_T20CMEN /*!< Timer controlled Mux mode enabled using TIM20 OC6 - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #endif /** * @} @@ -254,18 +254,18 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); */ #define OPAMP_SEC_NONINVERTINGINPUT_IO0 (0x00000000UL) /*!< Secondary non inverting input connected to I/O VINP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define OPAMP_SEC_NONINVERTINGINPUT_IO1 OPAMP_TCMR_VPSSEL_0 /*!< Secondary non inverting input connected to I/O VINP1 (PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_TCMR_VPSSEL_1 /*!< Secondary non inverting input connected to I/O VINP2 (PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_TCMR_VPSSEL /*!< Secondary non inverting input connected to I/O VINP3 (PD14 for OPAMP2) */ #define OPAMP_SEC_NONINVERTINGINPUT_DAC OPAMP_TCMR_VPSSEL /*!< Secondary non inverting input connected internally to DAC channel (DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ /** * @} */ @@ -277,12 +277,12 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); has been configured by call to @ref HAL_OPAMP_Init(). Secondary inverting input connected to I/O VINM0 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_TCMR_VMSSEL /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref OPAMP_STANDALONE_MODE has been configured by call to @ref HAL_OPAMP_Init(). Secondary inverting input connected to I/0 VINM1 (PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define OPAMP_SEC_INVERTINGINPUT_PGA (0x00000000UL) /*!< OPAMP secondary mode is PGA mode - Only applicable if configured mode through call to @ref HAL_OPAMP_Init() is @ref OPAMP_PGA_MODE or @ref OPAMP_FOLLOWER_MODE. OPAMP secondary inverting input is: diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp_ex.c index 02c39845b4e..0471bdd8816 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp_ex.c @@ -88,6 +88,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, + OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6) #endif { uint32_t trimmingvaluen1; @@ -103,6 +106,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA uint32_t trimmingvaluep5; uint32_t trimmingvaluen6; uint32_t trimmingvaluep6; +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + uint32_t trimmingvaluen6; + uint32_t trimmingvaluep6; #endif uint32_t delta; @@ -110,6 +116,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA if ((hopamp1 == NULL) || (hopamp2 == NULL) || (hopamp3 == NULL) #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) || (hopamp4 == NULL) || (hopamp5 == NULL) || (hopamp6 == NULL) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + || (hopamp6 == NULL) #endif ) { @@ -140,6 +148,11 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { return HAL_ERROR; } +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + else if (hopamp6->State != HAL_OPAMP_STATE_READY) + { + return HAL_ERROR; + } #endif else { @@ -152,6 +165,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance)); assert_param(IS_OPAMP_ALL_INSTANCE(hopamp5->Instance)); assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance)); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance)); #endif /* Set Calibration mode */ @@ -163,6 +178,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP); SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_FORCEVP); SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP); #endif /* user trimming values are used for offset calibration */ @@ -173,6 +190,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_USERTRIM); SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_USERTRIM); SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_USERTRIM); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_USERTRIM); #endif /* Enable calibration */ @@ -183,6 +202,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_CALON); SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_CALON); SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON); #endif /* 1st calibration - N */ @@ -194,6 +215,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA); #endif /* Enable the opamps */ @@ -204,6 +227,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN); SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_OPAMPxEN); SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN); #endif /* Init trimming counter */ @@ -215,6 +240,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA trimmingvaluen4 = 16UL; trimmingvaluen5 = 16UL; trimmingvaluen6 = 16UL; +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + trimmingvaluen6 = 16UL; #endif delta = 8UL; @@ -228,6 +255,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); #endif /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ @@ -301,6 +330,18 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* OPAMP_CSR_OUTCAL is LOW try lower trimming */ trimmingvaluen6 -= delta; } + +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) + { + /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ + trimmingvaluen6 += delta; + } + else + { + /* OPAMP_CSR_OUTCAL is LOW try lower trimming */ + trimmingvaluen6 -= delta; + } #endif delta >>= 1; @@ -315,6 +356,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); #endif /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ @@ -370,6 +413,15 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Set right trimming */ MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); } + +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) + { + /* OPAMP_CSR_OUTCAL is actually one value more */ + trimmingvaluen6++; + /* Set right trimming */ + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); + } #endif /* 2nd calibration - P */ @@ -381,6 +433,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA); #endif /* Init trimming counter */ @@ -392,6 +446,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA trimmingvaluep4 = 16UL; trimmingvaluep5 = 16UL; trimmingvaluep6 = 16UL; +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + trimmingvaluep6 = 16UL; #endif delta = 8UL; @@ -406,6 +462,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); #endif /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ @@ -473,6 +531,17 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA { trimmingvaluep6 -= delta; } + +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) + { + /* OPAMP_CSR_OUTCAL is HIGH try higher trimming */ + trimmingvaluep6 += delta; + } + else + { + trimmingvaluep6 -= delta; + } #endif delta >>= 1; @@ -488,6 +557,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); #endif /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ @@ -543,6 +614,15 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA /* Set right trimming */ MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); } + +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + if ((hopamp6->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL) + { + /* Trimming value is actually one value more */ + trimmingvaluep6++; + /* Set right trimming */ + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); + } #endif /* Disable calibration */ @@ -553,6 +633,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_CALON); CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_CALON); CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON); #endif /* Disable the OPAMPs */ @@ -563,6 +645,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN); CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_OPAMPxEN); CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN); #endif /* Set normal operating mode back */ @@ -573,11 +657,13 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP); CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_FORCEVP); CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP); #endif /* Self calibration is successful */ - /* Store calibration(user timming) results in init structure. */ - /* Select user timming mode */ + /* Store calibration(user timing) results in init structure. */ + /* Select user timing mode */ /* Write calibration result N */ hopamp1->Init.TrimmingValueN = trimmingvaluen1; @@ -587,6 +673,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA hopamp4->Init.TrimmingValueN = trimmingvaluen4; hopamp5->Init.TrimmingValueN = trimmingvaluen5; hopamp6->Init.TrimmingValueN = trimmingvaluen6; +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + hopamp6->Init.TrimmingValueN = trimmingvaluen6; #endif /* Write calibration result P */ @@ -597,9 +685,11 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA hopamp4->Init.TrimmingValueP = trimmingvaluep4; hopamp5->Init.TrimmingValueP = trimmingvaluep5; hopamp6->Init.TrimmingValueP = trimmingvaluep6; +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + hopamp6->Init.TrimmingValueP = trimmingvaluep6; #endif - /* Select user timming mode */ + /* Select user timing mode */ /* And updated with calibrated settings */ hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER; hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER; @@ -608,6 +698,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA hopamp4->Init.UserTrimming = OPAMP_TRIMMING_USER; hopamp5->Init.UserTrimming = OPAMP_TRIMMING_USER; hopamp6->Init.UserTrimming = OPAMP_TRIMMING_USER; +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + hopamp6->Init.UserTrimming = OPAMP_TRIMMING_USER; #endif MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING); @@ -617,6 +709,8 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING); MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING); #endif MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING); @@ -624,8 +718,10 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING); #if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx) MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING); - MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING); - MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING); + MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING); + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING); #endif } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp_ex.h index a89c2caba89..7dc215a0d8c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp_ex.h @@ -55,6 +55,9 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3); +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, + OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6); #endif /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.c index c435ac671ff..e36b98a3a08 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.c @@ -88,6 +88,8 @@ */ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); +static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); +static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); /** * @} @@ -99,8 +101,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); */ /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -224,7 +226,10 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ - (void)HAL_PCD_Stop(hpcd); + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + return HAL_ERROR; + } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) if (hpcd->MspDeInitCallback == NULL) @@ -538,7 +543,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Data OUT Stage Callback + * @brief Unregister the USB PCD Data OUT Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -611,7 +616,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Data IN Stage Callback + * @brief Unregister the USB PCD Data IN Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -684,7 +689,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Iso OUT incomplete Callback + * @brief Unregister the USB PCD Iso OUT incomplete Callback * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -757,7 +762,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Iso IN incomplete Callback + * @brief Unregister the USB PCD Iso IN incomplete Callback * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -830,7 +835,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC } /** - * @brief UnRegister the USB PCD BCD Callback + * @brief Unregister the USB PCD BCD Callback * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -903,7 +908,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC } /** - * @brief UnRegister the USB PCD LPM Callback + * @brief Unregister the USB PCD LPM Callback * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -940,8 +945,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -962,9 +967,10 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - (void)USB_DevConnect(hpcd->Instance); __HAL_PCD_ENABLE(hpcd); + (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -977,9 +983,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); - - (void)USB_StopDevice(hpcd->Instance); - + (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1050,21 +1054,18 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP)) { /* Force low-power mode in the macrocell */ - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; - if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U) - { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SuspendCallback(hpcd); + hpcd->SuspendCallback(hpcd); #else - HAL_PCD_SuspendCallback(hpcd); + HAL_PCD_SuspendCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } } /* Handle LPM Interrupt */ @@ -1074,8 +1075,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (hpcd->LPM_State == LPM_L0) { /* Force suspend and low-power mode before going to L1 state*/ - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_LPMODE; + hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP; hpcd->LPM_State = LPM_L1; hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; @@ -1291,8 +1292,8 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1315,6 +1316,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1328,6 +1330,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1343,6 +1346,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) hpcd->USB_Address = address; (void)USB_SetDevAddress(hpcd->Instance, address); __HAL_UNLOCK(hpcd); + return HAL_OK; } /** @@ -1480,6 +1484,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; + ep->xfer_fill_db = 1U; + ep->xfer_len_db = len; ep->xfer_count = 0U; ep->is_in = 1U; ep->num = ep_addr & EP_ADDR_MSK; @@ -1613,8 +1619,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -1659,9 +1665,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { PCD_EPTypeDef *ep; - uint16_t count; - uint16_t wIstr; - uint16_t wEPVal; + uint16_t count, wIstr, wEPVal, TxByteNbre; uint8_t epindex; /* stay in loop while pending interrupts */ @@ -1680,8 +1684,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /* DIR = 0 */ - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ + /* DIR = 0 => IN int */ + /* DIR = 0 implies that (EP_CTR_TX = 1) always */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); ep = &hpcd->IN_ep[0]; @@ -1705,20 +1709,20 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /* DIR = 1 */ - /* DIR = 1 & CTR_RX => SETUP or OUT int */ + /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ ep = &hpcd->OUT_ep[0]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); if ((wEPVal & USB_EP_SETUP) != 0U) { - /* Get SETUP Packet*/ + /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ + /* SETUP bit kept frozen while CTR_RX = 1 */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Process SETUP Packet*/ @@ -1728,12 +1732,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) HAL_PCD_SetupStageCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - else if ((wEPVal & USB_EP_CTR_RX) != 0U) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - /* Get Control Data OUT Packet*/ + /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) @@ -1743,7 +1746,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep->xfer_buff += ep->xfer_count; - /* Process Control Data OUT Packet*/ + /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, 0U); #else @@ -1758,20 +1761,21 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - /* Decode and service non control endpoints interrupt */ - + /* Decode and service non control endpoints interrupt */ /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); + if ((wEPVal & USB_EP_CTR_RX) != 0U) { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); ep = &hpcd->OUT_ep[epindex]; - /* OUT double Buffering*/ + /* OUT Single Buffering */ if (ep->doublebuffer == 0U) { count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); @@ -1779,28 +1783,39 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) + /* manage double buffer bulk out */ + if (ep->type == EP_TYPE_BULK) { - /*read from endpoint BUF0Addr buffer*/ - count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0U) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - } + count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal); } - else + else /* manage double buffer iso out */ { - /*read from endpoint BUF1Addr buffer*/ - count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0U) + /* free EP OUT Buffer */ + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); + + if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + /* read from endpoint BUF0Addr buffer */ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + else + { + /* read from endpoint BUF1Addr buffer */ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } } } - /* free EP OUT Buffer */ - PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); } - /*multi-packet on the NON control OUT endpoint*/ + /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; ep->xfer_buff += count; @@ -1815,10 +1830,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { - (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + (void) USB_EPStartXfer(hpcd->Instance, ep); } - } /* if((wEPVal & EP_CTR_RX) */ + } if ((wEPVal & USB_EP_CTR_TX) != 0U) { @@ -1827,31 +1842,296 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - /*multi-packet on the NON control IN endpoint*/ - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff += ep->xfer_count; + /* Manage all non bulk transaction or Bulk Single Buffer Transaction */ + if ((ep->type != EP_TYPE_BULK) || + ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))) + { + /* multi-packet on the NON control IN endpoint */ + TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len > TxByteNbre) + { + ep->xfer_len -= TxByteNbre; + } + else + { + ep->xfer_len = 0U; + } + + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* Transfer is not yet Done */ + ep->xfer_buff += TxByteNbre; + ep->xfer_count += TxByteNbre; + (void)USB_EPStartXfer(hpcd->Instance, ep); + } + } + /* bulk in double buffer enable in case of transferLen> Ep_Mps */ + else + { + (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); + } + } + } + } + + return HAL_OK; +} + + +/** + * @brief Manage double buffer bulk out transaction from ISR + * @param hpcd PCD handle + * @param ep current endpoint handle + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + uint16_t count; + + /* Manage Buffer0 OUT */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + /* Get count of received Data on buffer0 */ + count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= count) + { + ep->xfer_len -= count; + } + else + { + ep->xfer_len = 0U; + } + + if (ep->xfer_len == 0U) + { + /* set NAK to OUT endpoint since double buffer is enabled */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + } + + /* Check if Buffer1 is in blocked state which requires to toggle */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); + } + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); + } + } + /* Manage Buffer 1 DTOG_RX=0 */ + else + { + /* Get count of received data */ + count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= count) + { + ep->xfer_len -= count; + } + else + { + ep->xfer_len = 0U; + } + + if (ep->xfer_len == 0U) + { + /* set NAK on the current endpoint */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); + } + + /*Need to FreeUser Buffer*/ + if ((wEPVal & USB_EP_DTOG_TX) == 0U) + { + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); + } + + if (count != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); + } + } + + return count; +} + - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) +/** + * @brief Manage double buffer bulk IN transaction from ISR + * @param hpcd PCD handle + * @param ep current endpoint handle + * @param wEPVal Last snapshot of EPRx register value taken in ISR + * @retval HAL status + */ +static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, + PCD_EPTypeDef *ep, uint16_t wEPVal) +{ + uint32_t len; + uint16_t TxByteNbre; + + /* Data Buffer0 ACK received */ + if ((wEPVal & USB_EP_DTOG_TX) != 0U) + { + /* multi-packet on the NON control IN endpoint */ + TxByteNbre = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len > TxByteNbre) + { + ep->xfer_len -= TxByteNbre; + } + else + { + ep->xfer_len = 0U; + } + /* Transfer is completed */ + if (ep->xfer_len == 0U) + { + /* TX COMPLETE */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, ep->num); +#else + HAL_PCD_DataInStageCallback(hpcd, ep->num); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U); + } + } + else /* Transfer is not yet Done */ + { + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) != 0U) + { + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U); + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + { + ep->xfer_buff += TxByteNbre; + ep->xfer_count += TxByteNbre; + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) { - /* TX COMPLETE */ + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else if (ep->xfer_len_db == 0U) + { + len = TxByteNbre; + ep->xfer_fill_db = 0U; + } + else + { + ep->xfer_fill_db = 0U; + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + /* Write remaining Data to Buffer */ + /* Set the Double buffer counter for pma buffer1 */ + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /* Copy user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); + } + } + } + else /* Data Buffer1 ACK received */ + { + /* multi-packet on the NON control IN endpoint */ + TxByteNbre = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); + + if (ep->xfer_len >= TxByteNbre) + { + ep->xfer_len -= TxByteNbre; + } + else + { + ep->xfer_len = 0U; + } + + /* Transfer is completed */ + if (ep->xfer_len == 0U) + { + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, ep->num); + hpcd->DataInStageCallback(hpcd, ep->num); #else - HAL_PCD_DataInStageCallback(hpcd, ep->num); + HAL_PCD_DataInStageCallback(hpcd, ep->num); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + /*need to Free USB Buff*/ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + { + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U); + } + } + else /* Transfer is not yet Done */ + { + /* need to Free USB Buff */ + if ((wEPVal & USB_EP_DTOG_RX) == 0U) + { + PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U); + } + + /* Still there is data to Fill in the next Buffer */ + if (ep->xfer_fill_db == 1U) + { + ep->xfer_buff += TxByteNbre; + ep->xfer_count += TxByteNbre; + + /* Calculate the len of the new buffer to fill */ + if (ep->xfer_len_db >= ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else if (ep->xfer_len_db == 0U) + { + len = TxByteNbre; + ep->xfer_fill_db = 0U; } else { - (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + ep->xfer_fill_db = 0; } + + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); + + /* Copy the user buffer to USB PMA */ + USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); } } } + + /*enable endpoint IN*/ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); + return HAL_OK; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.h index ce60a8ac3b2..df2d62b6f63 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.h @@ -99,16 +99,16 @@ typedef struct __PCD_HandleTypeDef typedef struct #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - __IO uint32_t ErrorCode; /*!< PCD Error code */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; @@ -188,15 +188,15 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__))) #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE) @@ -233,7 +233,7 @@ typedef enum HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ - HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ @@ -353,7 +353,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ -#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ /** @@ -363,10 +363,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_EP0_MPS PCD EP0 MPS * @{ */ -#define PCD_EP0MPS_64 DEP0CTL_MPS_64 -#define PCD_EP0MPS_32 DEP0CTL_MPS_32 -#define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 +#define PCD_EP0MPS_64 EP_MPS_64 +#define PCD_EP0MPS_32 EP_MPS_32 +#define PCD_EP0MPS_16 EP_MPS_16 +#define PCD_EP0MPS_08 EP_MPS_8 /** * @} */ @@ -401,8 +401,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ + * @{ + */ /******************** Bit definition for USB_COUNTn_RX register *************/ #define USB_CNTRX_NBLK_MSK (0x1FU << 10) @@ -463,7 +463,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ /* toggle first bit ? */ \ @@ -487,7 +487,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ /* toggle first bit ? */ \ @@ -512,7 +512,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ /* toggle first bit ? */ \ @@ -564,10 +564,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval TRUE = endpoint in stall condition. */ -#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ - == USB_EP_TX_STALL) -#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ - == USB_EP_RX_STALL) +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL) /** * @brief set & clear EP_KIND bit. @@ -576,7 +574,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_KIND(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ \ @@ -584,7 +582,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_SET_EP_KIND */ #define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ \ @@ -616,7 +614,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ \ @@ -624,7 +622,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_CLEAR_RX_EP_CTR */ #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ \ @@ -638,7 +636,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_RX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wEPVal; \ + uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ \ @@ -646,7 +644,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_RX_DTOG */ #define PCD_TX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wEPVal; \ + uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ \ @@ -659,7 +657,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ \ @@ -670,7 +668,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_CLEAR_RX_DTOG */ #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ \ @@ -688,7 +686,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \ - register uint16_t _wRegVal; \ + uint16_t _wRegVal; \ \ _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ \ @@ -714,8 +712,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \ - register __IO uint16_t *_wRegVal; \ - register uint32_t _wRegBase = (uint32_t)USBx; \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ @@ -723,8 +721,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_SET_EP_TX_ADDRESS */ #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \ - register __IO uint16_t *_wRegVal; \ - register uint32_t _wRegBase = (uint32_t)USBx; \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ @@ -783,8 +781,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* PCD_SET_EP_CNT_RX_REG */ #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \ - register uint32_t _wRegBase = (uint32_t)(USBx); \ - register __IO uint16_t *pdwReg; \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *pdwReg; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ @@ -799,8 +797,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \ - register uint32_t _wRegBase = (uint32_t)(USBx); \ - register __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ @@ -808,8 +806,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) #define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \ - register uint32_t _wRegBase = (uint32_t)(USBx); \ - register __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ @@ -887,7 +885,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } while(0) /* SetEPDblBuf0Count*/ #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \ - register uint32_t _wBase = (uint32_t)(USBx); \ + uint32_t _wBase = (uint32_t)(USBx); \ __IO uint16_t *_wEPRegVal; \ \ if ((bDir) == 0U) \ @@ -910,7 +908,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - } while(0) /* PCD_SET_EP_DBUF_CNT */ + } while(0) /* PCD_SET_EP_DBUF_CNT */ /** * @brief Gets buffer 0/1 rx/tx counter for double buffering. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.c index 74d50c0415f..1fe3b6bcf40 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.c @@ -49,7 +49,7 @@ /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @brief PCDEx control functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr.c index 49b519092de..d4038599ad9 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr.c @@ -187,7 +187,7 @@ void HAL_PWR_DisableBkUpAccess(void) ========================================= [..] (+) Entry: - The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API + The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). @@ -209,7 +209,7 @@ void HAL_PWR_DisableBkUpAccess(void) =============================== [..] (+) Entry: - The Stop 0, Stop 1 modes are entered thru the following API's: + The Stop 0, Stop 1 modes are entered through the following API's: (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode(). (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): (++) PWR_MAINREGULATOR_ON @@ -241,7 +241,7 @@ void HAL_PWR_DisableBkUpAccess(void) and Standby circuitry. (++) Entry: - (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. + (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API. SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API @@ -262,7 +262,7 @@ void HAL_PWR_DisableBkUpAccess(void) SRAM and registers contents are lost except for backup domain registers. (+) Entry: - The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API. + The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API. (+) Exit: (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr_ex.c index fddf7fb547a..0da5546049e 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr_ex.c @@ -43,7 +43,7 @@ #if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) #define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */ #define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */ -#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) +#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx) #define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */ #define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */ #endif @@ -229,7 +229,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /** * @brief Enable battery charging. - * When VDD is present, charge the external battery on VBAT thru an internal resistor. + * When VDD is present, charge the external battery on VBAT through an internal resistor. * @param ResistorSelection: specifies the resistor impedance. * This parameter can be one of the following values: * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor @@ -682,7 +682,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) /* Configure EXTI 35 to 38 interrupts if so required: - scan thru PVMType to detect which PVMx is set and + scan through PVMType to detect which PVMx is set and configure the corresponding EXTI line accordingly. */ switch (sConfigPVM->PVMType) { @@ -822,62 +822,6 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) return status; } -#if defined(PWR_CR3_UCPD_DBDIS) -/** - * @brief Enable the USB Type-C dead battery pull-down behavior - * on UCPDx_CC1 and UCPDx_CC2 pins - * @note After exiting reset, the USB Type-C dead battery behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. - * It is recommended to disable it in all cases, either to stop this pull-down - * or to hand over control to the UCPD (which should therefore be - * initialized before doing the disable). - * @retval None - */ -void HAL_PWREx_EnableUSBDeadBatteryPD(void) -{ - /* writing 0 to enable the USB Type-C dead battery pull-down behavior */ - CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); -} - -/** - * @brief Disable the USB Type-C dead battery pull-down behavior - * on UCPDx_CC1 and UCPDx_CC2 pins - * @note After exiting reset, the USB Type-C dead battery behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. - * It is recommended to disable it in all cases, either to stop this pull-down - * or to hand over control to the UCPD (which should therefore be - * initialized before doing the disable). - * @retval None - */ -void HAL_PWREx_DisableUSBDeadBatteryPD(void) -{ - /* writing 1 to disable the USB Type-C dead battery pull-down behavior */ - SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); -} -#endif /* PWR_CR3_UCPD_DBDIS */ - -#if defined(PWR_CR3_UCPD_STDBY) -/** - * @brief Enable the USB Type-C and Power Delivery standby mode - * @retval None - */ -void HAL_PWREx_EnableUSBStandByModePD(void) -{ - /* Write 1 just before entering Standby when using UCPD */ - SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); -} - -/** - * @brief Disable the USB Type-C and Power Delivery standby mode - * @retval None - */ -void HAL_PWREx_DisableUSBStandByModePD (void) -{ - /* Write 0 immediately after Standby exit when using UCPD, - and before writing any UCPD registers */ - CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); -} -#endif /* PWR_CR3_UCPD_STDBY */ /** * @brief Enter Low-power Run mode @@ -1164,6 +1108,61 @@ __weak void HAL_PWREx_PVM4Callback(void) */ } +#if defined(PWR_CR3_UCPD_STDBY) +/** + * @brief Enable UCPD configuration memorization in Standby. + * @retval None + */ +void HAL_PWREx_EnableUCPDStandbyMode(void) +{ + /* Memorize UCPD configuration when entering standby mode */ + SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); +} + +/** + * @brief Disable UCPD configuration memorization in Standby. + * @note This function must be called on exiting the Standby mode and before any UCPD + * configuration update. + * @retval None + */ +void HAL_PWREx_DisableUCPDStandbyMode(void) +{ + /* Write 0 immediately after Standby exit when using UCPD, + and before writing any UCPD registers */ + CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); +} +#endif /* PWR_CR3_UCPD_STDBY */ + +#if defined(PWR_CR3_UCPD_DBDIS) +/** + * @brief Enable the USB Type-C dead battery pull-down behavior + * on UCPDx_CC1 and UCPDx_CC2 pins + * @retval None + */ +void HAL_PWREx_EnableUCPDDeadBattery(void) +{ + /* Write 0 to enable the USB Type-C dead battery pull-down behavior */ + CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); +} + +/** + * @brief Disable the USB Type-C dead battery pull-down behavior + * on UCPDx_CC1 and UCPDx_CC2 pins + * @note After exiting reset, the USB Type-C dead battery behavior will be enabled, + * which may have a pull-down effect on CC1 and CC2 pins. + * It is recommended to disable it in all cases, either to stop this pull-down + * or to hand over control to the UCPD (which should therefore be + * initialized before doing the disable). + * @retval None + */ +void HAL_PWREx_DisableUCPDDeadBattery(void) +{ + /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ + SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); +} +#endif /* PWR_CR3_UCPD_DBDIS */ + + /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr_ex.h index 6e0ac9e3dbc..8450897af35 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pwr_ex.h @@ -767,15 +767,6 @@ void HAL_PWREx_EnablePVM4(void); void HAL_PWREx_DisablePVM4(void); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); -#if defined(PWR_CR3_UCPD_DBDIS) -void HAL_PWREx_EnableUSBDeadBatteryPD(void); -void HAL_PWREx_DisableUSBDeadBatteryPD(void); -#endif /* PWR_CR3_UCPD_DBDIS */ -#if defined(PWR_CR3_UCPD_STDBY) -void HAL_PWREx_EnableUSBStandByModePD(void); -void HAL_PWREx_DisableUSBStandByModePD (void); -#endif /* PWR_CR3_UCPD_STDBY */ - /* Low Power modes configuration functions ************************************/ void HAL_PWREx_EnableLowPowerRunMode(void); HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); @@ -793,6 +784,15 @@ void HAL_PWREx_PVM2Callback(void); void HAL_PWREx_PVM3Callback(void); void HAL_PWREx_PVM4Callback(void); +#if defined(PWR_CR3_UCPD_STDBY) +void HAL_PWREx_EnableUCPDStandbyMode(void); +void HAL_PWREx_DisableUCPDStandbyMode(void); +#endif /* PWR_CR3_UCPD_STDBY */ +#if defined(PWR_CR3_UCPD_DBDIS) +void HAL_PWREx_EnableUCPDDeadBattery(void); +void HAL_PWREx_DisableUCPDDeadBattery(void); +#endif /* PWR_CR3_UCPD_DBDIS */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc.c index a515fec7043..78fcfcee4cb 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc.c @@ -18,8 +18,8 @@ and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses: - all peripherals mapped on these busses are running at HSI speed. + (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses: + all peripherals mapped on these buses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in analog mode, except the JTAG pins which are assigned to be used for debug purpose. @@ -29,7 +29,7 @@ (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers + (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not derived from the System clock (USB, RNG, USART, LPUART, FDCAN, some TIMERs, @@ -119,7 +119,7 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); =============================================================================== [..] This section provides functions allowing to configure the internal and external oscillators - (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration @@ -149,14 +149,14 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE, main PLL clock, system clock or RC48 clock (through a configurable prescaler) on PA8 pin. - [..] System, AHB and APB busses clocks configuration + [..] System, AHB and APB buses clocks configuration (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and main PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use + the peripherals mapped on these buses. You can use "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: @@ -180,30 +180,22 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void); @endverbatim Table 1. HCLK clock frequency for STM32G4xx devices - +--------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |--------------------------------------| - | | voltage range 1 | voltage range 2 | - | | 1.2 V | 1.0 V | - |-----------------|-------------------|------------------| - |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | - |-----------------|-------------------|------------------| - |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | - |-----------------|-------------------|------------------| - |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |6WS(7 CPU cycles)| 120 < HCLK <= 140 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |7WS(8 CPU cycles)| 140 < HCLK <= 160 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |8WS(9 CPU cycles)| 160 < HCLK <= 170 | 16 < HCLK <= 26 | - +--------------------------------------------------------+ + +----------------------------------------------------------------------------+ + | Latency | HCLK clock frequency (MHz) | + | |----------------------------------------------------------| + | | voltage range 1 | voltage range 1 | voltage range 2 | + | | boost mode 1.28 V | normal mode 1.2 V | 1.0 V | + |-----------------|-------------------|-------------------|------------------| + |0WS(1 CPU cycles)| HCLK <= 34 | HCLK <= 30 | HCLK <= 13 | + |-----------------|-------------------|-------------------|------------------| + |1WS(2 CPU cycles)| HCLK <= 68 | HCLK <= 60 | HCLK <= 26 | + |-----------------|-------------------|-------------------|------------------| + |2WS(3 CPU cycles)| HCLK <= 102 | HCLK <= 90 | - | + |-----------------|-------------------|-------------------|------------------| + |3WS(4 CPU cycles)| HCLK <= 136 | HCLK <= 120 | - | + |-----------------|-------------------|-------------------|------------------| + |4WS(5 CPU cycles)| HCLK <= 170 | HCLK <= 150 | - | + +----------------------------------------------------------------------------+ * @{ */ @@ -723,7 +715,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /** - * @brief Initialize the CPU, AHB and APB busses clocks according to the specified + * @brief Initialize the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. @@ -960,7 +952,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui [..] This subsection provides a set of functions allowing to: - (+) Ouput clock to MCO pin. + (+) Output clock to MCO pin. (+) Retrieve current clock frequencies. (+) Enable the Clock Security System. @@ -1008,7 +1000,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M /* MCO Clock Enable */ MCO1_CLK_ENABLE(); - /* Configue the MCO1 pin in alternate function mode */ + /* Configure the MCO1 pin in alternate function mode */ GPIO_InitStruct.Pin = MCO1_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc_ex.c index 56f57048290..8e195b3f177 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc_ex.c @@ -498,6 +498,15 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ RCC_PERIPHCLK_QSPI | \ RCC_PERIPHCLK_RTC; +#elif defined(STM32G491xx) || defined(STM32G4A1xx) + + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ + RCC_PERIPHCLK_UART5 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | \ + RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \ + RCC_PERIPHCLK_QSPI | \ + RCC_PERIPHCLK_RTC; #elif defined(STM32G473xx) || defined(STM32G483xx) @@ -1360,7 +1369,7 @@ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) /* LSCO Pin Clock Enable */ __LSCO_CLK_ENABLE(); - /* Configue the LSCO pin in analog mode */ + /* Configure the LSCO pin in analog mode */ GPIO_InitStruct.Pin = LSCO_PIN; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; @@ -1442,7 +1451,7 @@ void HAL_RCCEx_DisableLSCO(void) ##### Extended Clock Recovery System Control functions ##### =============================================================================== [..] - For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: (#) In System clock config, HSI48 needs to be enabled diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc_ex.h index 899dbf7406d..7f3ba6dd547 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rcc_ex.h @@ -1220,14 +1220,14 @@ typedef struct #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) /** - * @brief Enable the automatic hardware adjustement of TRIM bits. + * @brief Enable the automatic hardware adjustment of TRIM bits. * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. * @retval None */ #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) /** - * @brief Enable or disable the automatic hardware adjustement of TRIM bits. + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. * @retval None */ #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) @@ -1338,7 +1338,28 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \ + (((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ @@ -1355,6 +1376,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.c index fc50f290f5b..879efa617df 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.c @@ -222,7 +222,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -1198,7 +1198,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } - else /* format BCD */ + else /* Format BCD */ { if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) { @@ -1420,6 +1420,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } + /* Configure the Alarm A or Alarm B Sub Second registers */ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); @@ -1430,7 +1431,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef if (sAlarm->Alarm == RTC_ALARM_A) { /* Disable the Alarm A interrupt */ - CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE); + CLEAR_BIT(RTC->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + /* Clear flag alarm A */ WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); __HAL_RTC_ALARM_EXTI_CLEAR_IT(); @@ -1462,7 +1464,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef else { /* Disable the Alarm B interrupt */ - CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE); + CLEAR_BIT(RTC->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + /* Clear flag alarm B */ WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); __HAL_RTC_ALARM_EXTI_CLEAR_IT(); @@ -1499,6 +1502,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.h index d7497de8a5c..5e664434204 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.c index b4d8a440452..fc3adce9c5e 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.c @@ -93,7 +93,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.h index 3757c0a496f..0fefc8fb3a9 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sai.c index d70367678ed..d17a6f31cfa 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sai.c @@ -521,8 +521,26 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) { /* NODIV = 1 */ + uint32_t tmpframelength; + + if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) + { + /* For SPDIF protocol, frame length is set by hardware to 64 */ + tmpframelength = 64U; + } + else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL) + { + /* For AC97 protocol, frame length is set by hardware to 256 */ + tmpframelength = 256U; + } + else + { + /* For free protocol, frame length is set by user */ + tmpframelength = hsai->FrameInit.FrameLength; + } + /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength); + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength); } else { @@ -539,6 +557,12 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) { hsai->Init.Mckdiv += 1U; } + + /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */ + if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) + { + hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1; + } } /* Check the SAI Block master clock divider parameter */ assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); @@ -1351,29 +1375,17 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Abort the SAI Tx DMA Stream */ if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) { - if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) - { - /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } + /* No need to check the returned value of HAL_DMA_Abort. */ + /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */ + (void) HAL_DMA_Abort(hsai->hdmatx); } /* Abort the SAI Rx DMA Stream */ if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) { - if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) - { - /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } + /* No need to check the returned value of HAL_DMA_Abort. */ + /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */ + (void) HAL_DMA_Abort(hsai->hdmarx); } /* Disable SAI peripheral */ @@ -1416,29 +1428,17 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Abort the SAI Tx DMA Stream */ if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) { - if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) - { - /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } + /* No need to check the returned value of HAL_DMA_Abort. */ + /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */ + (void) HAL_DMA_Abort(hsai->hdmatx); } /* Abort the SAI Rx DMA Stream */ if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) { - if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) - { - /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } + /* No need to check the returned value of HAL_DMA_Abort. */ + /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */ + (void) HAL_DMA_Abort(hsai->hdmarx); } } @@ -1517,7 +1517,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, /* Enable SAI Tx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - /* Wait untill FIFO is not empty */ + /* Wait until FIFO is not empty */ while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) { /* Check for the Timeout */ @@ -1597,6 +1597,12 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u return HAL_ERROR; } + /* Enable the interrupts for error handling */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + /* Enable SAI Rx DMA Request */ + hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + /* Check if the SAI is already enabled */ if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) { @@ -1604,12 +1610,6 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u __HAL_SAI_ENABLE(hsai); } - /* Enable the interrupts for error handling */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - /* Enable SAI Rx DMA Request */ - hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - /* Process Unlocked */ __HAL_UNLOCK(hsai); @@ -1752,6 +1752,9 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /* SAI AFSDET interrupt occurred ----------------------------------*/ else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) { + /* Clear the SAI AFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET); + /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; @@ -1815,6 +1818,9 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /* SAI LFSDET interrupt occurred ----------------------------------*/ else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) { + /* Clear the SAI LFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET); + /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; @@ -1878,6 +1884,9 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /* SAI WCKCFG interrupt occurred ----------------------------------*/ else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) { + /* Clear the SAI WCKCFG flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG); + /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; @@ -2138,20 +2147,16 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, return HAL_ERROR; } - switch (protocol) + if (protocol == SAI_I2S_STANDARD) { - case SAI_I2S_STANDARD : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; - hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - break; - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; - hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; - break; - default : - status = HAL_ERROR; - break; + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + } + else + { + /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */ + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; + hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; } /* Frame definition */ @@ -2233,17 +2238,14 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->SlotInit.SlotNumber = nbslot; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - switch (protocol) + if (protocol == SAI_PCM_SHORT) { - case SAI_PCM_SHORT : - hsai->FrameInit.ActiveFrameLength = 1; - break; - case SAI_PCM_LONG : - hsai->FrameInit.ActiveFrameLength = 13; - break; - default : - status = HAL_ERROR; - break; + hsai->FrameInit.ActiveFrameLength = 1; + } + else + { + /* SAI_PCM_LONG */ + hsai->FrameInit.ActiveFrameLength = 13; } switch (datasize) @@ -2360,7 +2362,7 @@ static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef */ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) { - register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U); + uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U); HAL_StatusTypeDef status = HAL_OK; /* Disable the SAI instance */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sai.h index 36d9b1821e0..b249460443e 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sai.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sai.h @@ -153,6 +153,7 @@ typedef struct /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition * @brief SAI Frame Init structure definition + * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). * @{ */ typedef struct @@ -185,6 +186,8 @@ typedef struct /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition * @brief SAI Block Slot Init Structure definition + * @note For SPDIF protocol, these parameters are not used (set by hardware). + * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). * @{ */ typedef struct diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.c index 77277cd0606..85581f3cbb3 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.c @@ -35,7 +35,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission @@ -107,8 +108,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. - Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. (+) ErrorCallback : Error Callback. @@ -123,9 +124,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. @@ -140,13 +141,13 @@ (+) MspDeInitCallback : SMARTCARD MspDeInit. [..] - By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() - and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -155,8 +156,8 @@ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() - or @ref HAL_SMARTCARD_Init() function. + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or @@ -483,7 +484,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -618,43 +620,45 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma switch (CallbackID) { case HAL_SMARTCARD_TX_COMPLETE_CB_ID : - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_SMARTCARD_RX_COMPLETE_CB_ID : - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_SMARTCARD_ERROR_CB_ID : - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback*/ break; case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : - hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : - hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_SMARTCARD_MSPINIT_CB_ID : - hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_SMARTCARD_MSPDEINIT_CB_ID : - hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -725,62 +729,67 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. [..] - (+) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) Non-Blocking mode: The communication is performed using Interrupts + (##) Non-Blocking mode: The communication is performed using Interrupts or DMA, the relevant API's return the HAL status. The end of the data processing will be indicated through the dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks will be executed respectively at the end of the Transmit or Receive process The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected. - (+) Blocking mode APIs are : - (++) HAL_SMARTCARD_Transmit() - (++) HAL_SMARTCARD_Receive() + (#) Blocking mode APIs are : + (##) HAL_SMARTCARD_Transmit() + (##) HAL_SMARTCARD_Receive() - (+) Non Blocking mode APIs with Interrupt are : - (++) HAL_SMARTCARD_Transmit_IT() - (++) HAL_SMARTCARD_Receive_IT() - (++) HAL_SMARTCARD_IRQHandler() + (#) Non Blocking mode APIs with Interrupt are : + (##) HAL_SMARTCARD_Transmit_IT() + (##) HAL_SMARTCARD_Receive_IT() + (##) HAL_SMARTCARD_IRQHandler() - (+) Non Blocking mode functions with DMA are : - (++) HAL_SMARTCARD_Transmit_DMA() - (++) HAL_SMARTCARD_Receive_DMA() + (#) Non Blocking mode functions with DMA are : + (##) HAL_SMARTCARD_Transmit_DMA() + (##) HAL_SMARTCARD_Receive_DMA() - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SMARTCARD_TxCpltCallback() - (++) HAL_SMARTCARD_RxCpltCallback() - (++) HAL_SMARTCARD_ErrorCallback() + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (##) HAL_SMARTCARD_TxCpltCallback() + (##) HAL_SMARTCARD_RxCpltCallback() + (##) HAL_SMARTCARD_ErrorCallback() [..] (#) Non-Blocking mode transfers could be aborted using Abort API's : - (++) HAL_SMARTCARD_Abort() - (++) HAL_SMARTCARD_AbortTransmit() - (++) HAL_SMARTCARD_AbortReceive() - (++) HAL_SMARTCARD_Abort_IT() - (++) HAL_SMARTCARD_AbortTransmit_IT() - (++) HAL_SMARTCARD_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (++) HAL_SMARTCARD_AbortCpltCallback() - (++) HAL_SMARTCARD_AbortTransmitCpltCallback() - (++) HAL_SMARTCARD_AbortReceiveCpltCallback() + (##) HAL_SMARTCARD_Abort() + (##) HAL_SMARTCARD_AbortTransmit() + (##) HAL_SMARTCARD_AbortReceive() + (##) HAL_SMARTCARD_Abort_IT() + (##) HAL_SMARTCARD_AbortTransmit_IT() + (##) HAL_SMARTCARD_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), + a set of Abort Complete Callbacks are provided: + (##) HAL_SMARTCARD_AbortCpltCallback() + (##) HAL_SMARTCARD_AbortTransmitCpltCallback() + (##) HAL_SMARTCARD_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. - If user wants to abort it, Abort services should be called by user. - (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. + (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt + mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -824,14 +833,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Disable Rx, enable Tx */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST); + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; @@ -846,20 +864,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); ptmpdata++; } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, - Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, + tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { - /* Disable the Peripheral first to update modes */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); /* At end of Tx process, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -980,14 +1006,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Disable Rx, enable Tx */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST); + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + /* Configure Tx interrupt processing */ if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) { @@ -1128,14 +1163,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Disable Rx, enable Tx */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST); + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + /* Set the SMARTCARD DMA transfer complete callback */ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; @@ -1276,7 +1320,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); @@ -1338,8 +1383,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1430,7 +1475,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ @@ -1470,8 +1516,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1498,14 +1544,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t abortcplt = 1U; - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); - /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, + DMA Abort complete callbacks should be initialised before any call + to DMA Abort functions */ /* DMA Tx Handle is valid */ if (hsmartcard->hdmatx != NULL) { @@ -1599,8 +1647,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1732,7 +1780,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ @@ -1771,8 +1820,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1797,8 +1846,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2269,14 +2318,18 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) { /* Init the SMARTCARD Callback settings */ - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ - hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak + RxFifoFullCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak + TxFifoEmptyCallback */ } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -2366,21 +2419,26 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { case SMARTCARD_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: - tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; default: ret = HAL_ERROR; @@ -2541,7 +2599,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -2735,8 +2794,8 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2784,8 +2843,8 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2846,8 +2905,8 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2950,15 +3009,22 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { - /* Disable the Peripheral first to update modes */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); /* Tx process is ended, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.h index 40028b90d5a..4af3163117a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.h @@ -52,7 +52,8 @@ typedef struct where usart_ker_ckpres is the USART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ + This parameter @ref SMARTCARD_Word_Length can only be + set to 9 (8 data + 1 parity bits). */ uint32_t StopBits; /*!< Specifies the number of stop bits. This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ @@ -76,13 +77,14 @@ typedef struct data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote + is selected. Selecting the single sample method increases + the receiver tolerance to clock deviations. This parameter can be a value + of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied - by 2 to give the division factor of the source clock frequency */ + This parameter can be any value from 0x01 to 0x1F. Prescaler value is + multiplied by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -111,7 +113,7 @@ typedef struct } SMARTCARD_InitTypeDef; /** - * @brief SMARTCARD advanced features initalization structure definition + * @brief SMARTCARD advanced features initialization structure definition */ typedef struct { @@ -141,14 +143,16 @@ typedef struct uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when - relevant flag is available) or once guard time period has elapsed. - This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value + of @ref SMARTCARDEx_Transmission_Completion_Indication. */ } SMARTCARD_AdvFeatureInitTypeDef; /** * @brief HAL SMARTCARD State definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition). + * @note HAL SMARTCARD State value is a combination of 2 different substates: + * gState and RxState (see @ref SMARTCARD_State_Definition). * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -215,7 +219,8 @@ typedef struct __SMARTCARD_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. - This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ + This parameter can be a value of + @ref SMARTCARDEx_FIFO_mode. */ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ @@ -227,12 +232,14 @@ typedef struct __SMARTCARD_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global + Handle management and also related to Tx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO uint32_t ErrorCode; /*!< SmartCard Error code */ @@ -312,23 +319,26 @@ typedef enum /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition * @{ */ -#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value + is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for + use. Value is allowed for gState + and RxState */ #define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ -#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception + process is ongoing Not to be used for + neither gState nor RxState. + Value is result of combination (Or) + between gState and RxState values */ #define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ + Value is allowed for gState only */ /** * @} */ @@ -664,7 +674,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before + * guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -677,9 +688,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -689,7 +707,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard + * time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -702,9 +721,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -714,7 +740,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -728,7 +755,9 @@ typedef enum * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) + & ((uint32_t)0x01U << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U)\ + ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -738,7 +767,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -751,9 +781,15 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x01U)?\ + (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x02U)?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) &\ + ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -1101,7 +1137,8 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard_ex.c index 8c731c6cea8..ad2626fadec 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard_ex.c @@ -472,8 +472,10 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \ + (uint16_t)denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \ + (uint16_t)denominator[rx_fifo_threshold]; } } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.c index 829b12b5acc..ab0ffe1e6a1 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.c @@ -89,12 +89,12 @@ *** Callback registration *** ============================================= - + [..] The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback() to register an interrupt callback. - + [..] Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. @@ -106,9 +106,9 @@ (+) MspDeInitCallback : callback for Msp DeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - + [..] For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback. - + [..] Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default weak function. @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, @@ -122,9 +122,9 @@ (+) ErrorCallback : callback for error detection. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. - + [..] For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback. - + [..] By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). @@ -133,7 +133,7 @@ these callbacks are null (not registered beforehand). If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - + [..] Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, @@ -141,7 +141,7 @@ Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() or @ref HAL_SMBUS_Init() function. - + [..] When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -203,18 +203,20 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, + uint32_t Timeout); -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); /** * @} */ @@ -226,8 +228,8 @@ static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t */ /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -579,7 +581,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -858,8 +861,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -911,7 +914,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -950,7 +954,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { @@ -1010,7 +1015,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -1050,7 +1056,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { @@ -1165,7 +1172,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1213,7 +1221,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { @@ -1259,7 +1268,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1417,7 +1427,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -1526,8 +1537,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Increment Trials */ SMBUS_Trials++; - } - while (SMBUS_Trials < Trials); + } while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1549,8 +1559,8 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t */ /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /** * @brief Handle SMBUS event interrupt request. @@ -1566,7 +1576,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) @@ -1585,7 +1600,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1604,7 +1624,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Listener Only --------------------------------------------------*/ - if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { @@ -1744,8 +1769,8 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * + * @brief Peripheral State and Errors functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -1771,11 +1796,11 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) } /** -* @brief Return the SMBUS error code. + * @brief Return the SMBUS error code. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. -* @retval SMBUS Error Code -*/ + * @retval SMBUS Error Code + */ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) { return hsmbus->ErrorCode; @@ -1790,7 +1815,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) */ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions + * @brief Data transfers Private functions * @{ */ @@ -1801,7 +1826,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint16_t DevAddress; @@ -1854,7 +1879,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* REenable the selected SMBUS peripheral */ + /* Re-enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); /* Call the corresponding callback to inform upper layer of End of Transfer */ @@ -1941,7 +1966,8 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else @@ -2085,7 +2111,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint8_t TransferDirection; uint16_t SlaveAddrCode; @@ -2155,7 +2181,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, u HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } - else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) + else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) { if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { @@ -2210,7 +2237,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, u { if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else @@ -2341,7 +2369,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, u * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; @@ -2381,7 +2409,7 @@ static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Inte * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; uint32_t tmpstate = hsmbus->State; @@ -2453,7 +2481,7 @@ static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Int * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t itflags = READ_REG(hsmbus->Instance->ISR); uint32_t itsources = READ_REG(hsmbus->Instance->CR1); @@ -2554,7 +2582,8 @@ static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, + uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2603,7 +2632,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeD * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2611,16 +2641,20 @@ static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hsmbus->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** - * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. + * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions. * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) { /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.h index c3abdb69118..2bb2d88287f 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.h @@ -65,7 +65,7 @@ typedef struct uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of @ref SMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. @@ -132,7 +132,11 @@ typedef struct * @brief SMBUS handle Structure definition * @{ */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) typedef struct __SMBUS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ { I2C_TypeDef *Instance; /*!< SMBUS registers base address */ @@ -326,6 +330,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) @@ -353,7 +358,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE #define SMBUS_IT_RXI I2C_CR1_RXIE #define SMBUS_IT_TXI I2C_CR1_TXIE -#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \ + SMBUS_IT_TXI) #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) @@ -403,10 +409,10 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) #endif @@ -457,7 +463,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SMBUS flag is set or not. * @param __HANDLE__ specifies the SMBUS Handle. @@ -483,7 +490,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @retval The new state of __FLAG__ (SET or RESET). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) -#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. @@ -534,15 +542,15 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ - ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ - ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) + ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ ((MASK) == SMBUS_OA2_MASK01) || \ @@ -560,46 +568,49 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ - ((PEC) == SMBUS_PEC_ENABLE)) + ((PEC) == SMBUS_PEC_ENABLE)) -#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) -#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ - ((MODE) == SMBUS_AUTOEND_MODE) || \ - ((MODE) == SMBUS_SOFTEND_MODE) || \ - ((MODE) == SMBUS_SENDPEC_MODE) || \ - ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ - ((REQUEST) == SMBUS_GENERATE_START_READ) || \ - ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ - ((REQUEST) == SMBUS_NO_STARTSTOP)) + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == SMBUS_FIRST_FRAME) || \ - ((REQUEST) == SMBUS_NEXT_FRAME) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + ((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) -#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) -#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) @@ -607,7 +618,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) -#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) @@ -623,8 +635,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ + * @{ + */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); @@ -636,7 +648,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); @@ -647,28 +660,33 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ + * @{ + */ /* IO operation functions *****************************************************/ /** @addtogroup Blocking_mode_Polling Blocking mode Polling - * @{ - */ + * @{ + */ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); /** * @} */ /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt - * @{ - */ + * @{ + */ /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); @@ -679,8 +697,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); @@ -697,8 +715,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ + * @{ + */ /* Peripheral State and Errors functions **************************************************/ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.c index fa5e3eaf53d..5fa006098cc 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.c @@ -131,7 +131,7 @@ DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | @@ -156,7 +156,7 @@ DataSize = SPI_DATASIZE_16BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | @@ -337,6 +337,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + } + } + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; } #if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); @@ -400,44 +418,56 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; } - /* Align the CRC Length on the data size */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) - { - /* CRC Length aligned on the data size : value set by default */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; - } - else - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; - } - } - /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ - WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + (hspi->Init.NSS & SPI_CR1_SSM) | + (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); #if (USE_SPI_CRC != 0U) - /* Configure : CRC Length */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + /*---------------------------- SPIx CRCL Configuration -------------------*/ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCL; + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Length aligned on the data size : value set by default */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } + + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); + } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | - hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + (hspi->Init.TIMode & SPI_CR2_FRF) | + (hspi->Init.NSSPMode & SPI_CR2_NSSP) | + (hspi->Init.DataSize & SPI_CR2_DS_Msk) | + (frxth & SPI_CR2_FRXTH))); #if (USE_SPI_CRC != 0U) /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); } #endif /* USE_SPI_CRC */ @@ -835,6 +865,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1042,6 +1074,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Configure communication direction: 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1544,6 +1578,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1635,6 +1671,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1835,6 +1873,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1965,6 +2005,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -3051,8 +3093,17 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } #endif /* USE_SPI_CRC */ - /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) @@ -3469,7 +3520,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 8bit CRC to flush Data Regsiter */ + /* Read 8bit CRC to flush Data Register */ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); hspi->CRCSize--; @@ -3577,7 +3628,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 16bit CRC to flush Data Regsiter */ + /* Read 16bit CRC to flush Data Register */ READ_REG(hspi->Instance->DR); /* Disable RXNE interrupt */ @@ -3794,15 +3845,26 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) { if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); @@ -3827,6 +3889,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + { + tmp_timeout = 0U; + } + count--; } } @@ -3846,6 +3914,17 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + while ((hspi->Instance->SR & Fifo) != State) { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) @@ -3856,7 +3935,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -3885,6 +3964,12 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + { + tmp_timeout = 0U; + } + count--; } } @@ -3971,7 +4056,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { uint32_t tickstart; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Disable ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.h index 6c5940a74cb..c209933d633 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.h @@ -582,7 +582,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of SPI SR regsiter. + * @param __SR__ copy of SPI SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag @@ -596,10 +596,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_FLAG_FRLVL: SPI fifo reception level * @retval SET or RESET. */ -#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of SPI CR2 regsiter. + * @param __CR2__ copy of SPI CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable @@ -607,15 +608,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_IT_ERR: Error interrupt enable * @retval SET or RESET. */ -#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. * This parameter can be a value of @ref SPI_Mode * @retval None */ -#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ - ((__MODE__) == SPI_MODE_MASTER)) +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) /** @brief Checks if SPI Direction Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Direction Mode. @@ -663,33 +665,33 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_Clock_Polarity * @retval None */ -#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ - ((__CPOL__) == SPI_POLARITY_HIGH)) +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) /** @brief Checks if SPI Clock Phase parameter is in allowed range. * @param __CPHA__ specifies the SPI Clock Phase. * This parameter can be a value of @ref SPI_Clock_Phase * @retval None */ -#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ - ((__CPHA__) == SPI_PHASE_2EDGE)) +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) /** @brief Checks if SPI Slave Select parameter is in allowed range. * @param __NSS__ specifies the SPI Slave Select management parameter. * This parameter can be a value of @ref SPI_Slave_Select_management * @retval None */ -#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ - ((__NSS__) == SPI_NSS_HARD_INPUT) || \ - ((__NSS__) == SPI_NSS_HARD_OUTPUT)) +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) /** @brief Checks if SPI NSS Pulse parameter is in allowed range. * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. * This parameter can be a value of @ref SPI_NSSP_Mode * @retval None */ -#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ - ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. * @param __PRESCALER__ specifies the SPI Baudrate prescaler. @@ -710,16 +712,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_MSB_LSB_transmission * @retval None */ -#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ - ((__BIT__) == SPI_FIRSTBIT_LSB)) +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) /** @brief Checks if SPI TI mode parameter is in allowed range. * @param __MODE__ specifies the SPI TI mode. * This parameter can be a value of @ref SPI_TI_mode * @retval None */ -#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ - ((__MODE__) == SPI_TIMODE_ENABLE)) +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) /** @brief Checks if SPI CRC calculation enabled state is in allowed range. * @param __CALCULATION__ specifies the SPI CRC calculation enable state. @@ -734,8 +736,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_CRC_length * @retval None */ -#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ - ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. @@ -743,7 +745,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 * @retval None */ -#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.c index 249d904f5d6..da4d951e04d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.c @@ -452,7 +452,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; - /* Check if the size is a 32-bits mulitple */ + /* Check if the size is a 32-bits multiple */ limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); /* Read data from memory */ @@ -510,7 +510,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; - /* Check if the size is a 32-bits mulitple */ + /* Check if the size is a 32-bits multiple */ limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); /* Write data to memory */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.c index 58aa3e6c5f7..fd78efb895b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.c @@ -205,7 +205,7 @@ all interrupt callbacks are set to the corresponding weak functions: /* Private define ------------------------------------------------------------*/ #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions @@ -227,6 +227,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -312,6 +313,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -345,6 +353,13 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -397,19 +412,29 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } - /* Change the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -424,13 +449,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the TIM state*/ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -449,12 +471,28 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -472,12 +510,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -496,6 +538,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + /* Set the TIM state */ if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; @@ -513,7 +556,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else { - /* nothing to do */ + return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ @@ -533,8 +576,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -561,7 +611,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -644,6 +694,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -677,6 +734,13 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -736,6 +800,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -746,8 +819,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -786,6 +866,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -808,6 +891,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -852,8 +944,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -924,6 +1023,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -948,11 +1050,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -960,12 +1063,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -1062,8 +1165,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1138,8 +1248,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1221,6 +1331,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1254,6 +1371,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1313,6 +1437,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -1323,8 +1456,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1363,8 +1503,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1387,6 +1527,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1431,8 +1580,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1503,6 +1659,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1527,11 +1686,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -1539,12 +1699,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -1640,8 +1800,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1716,8 +1883,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1799,6 +1966,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1832,6 +2006,13 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1885,16 +2066,36 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1925,6 +2126,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1943,10 +2148,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1984,8 +2202,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2050,6 +2275,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2070,16 +2299,21 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -2087,12 +2321,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -2181,8 +2416,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2208,6 +2450,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2246,14 +2491,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -2290,6 +2533,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: @@ -2345,6 +2591,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2378,6 +2633,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2428,9 +2692,29 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2485,6 +2769,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2500,9 +2790,29 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2568,6 +2878,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2606,6 +2922,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status @@ -2623,15 +2942,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini } /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -2703,6 +3022,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2737,6 +3065,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2788,8 +3125,58 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } /* Enable the encoder interface channels */ switch (Channel) @@ -2833,7 +3220,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2862,6 +3249,20 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + /* Return function status */ return HAL_OK; } @@ -2878,8 +3279,58 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ @@ -2929,7 +3380,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2960,8 +3411,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -2983,27 +3445,95 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) { - return HAL_BUSY; + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } } - else if (htim->State == HAL_TIM_STATE_READY) + else if (Channel == TIM_CHANNEL_2) { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { - return HAL_ERROR; + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } } else { - htim->State = HAL_TIM_STATE_BUSY; + return HAL_ERROR; } } else { - /* nothing to do */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } } switch (Channel) @@ -3101,6 +3631,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch default: break; } + /* Return function status */ return HAL_OK; } @@ -3118,7 +3649,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -3153,8 +3684,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -3475,8 +4017,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3543,8 +4083,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3575,8 +4113,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ @@ -3640,8 +4176,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3675,8 +4209,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3785,8 +4317,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -4025,11 +4555,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4037,7 +4567,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -4174,8 +4704,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -4188,7 +4716,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4197,51 +4724,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4357,11 +4884,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4369,7 +4896,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -4507,8 +5034,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -4521,7 +5046,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4530,51 +5054,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4664,7 +5188,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } else { - CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); } break; } @@ -4682,17 +5206,17 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, #if defined (COMP7) case TIM_CLEARINPUTSOURCE_COMP7: #endif /* COMP7 */ - { - if (IS_TIM_OCCS_INSTANCE(htim->Instance)) { - /* Clear the OCREF clear selection bit */ - CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + if (IS_TIM_OCCS_INSTANCE(htim->Instance)) + { + /* Clear the OCREF clear selection bit */ + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - /* Clear TIM1_AF2_OCRSEL (reset value) */ - MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); + /* Clear TIM1_AF2_OCRSEL (reset value) */ + MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); + } + break; } - break; - } case TIM_CLEARINPUTSOURCE_ETR: { @@ -4965,15 +5489,17 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo #if defined (TIM20) case TIM_CLOCKSOURCE_ITR9: #endif /* TIM20 */ +#if defined (HRTIM1) case TIM_CLOCKSOURCE_ITR10: +#endif /* HRTIM1 */ case TIM_CLOCKSOURCE_ITR11: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } default: break; @@ -5957,6 +6483,54 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + /** * @} */ @@ -5978,13 +6552,38 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** @@ -5996,23 +6595,41 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -6037,8 +6654,6 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -6078,23 +6693,45 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -6119,8 +6756,6 @@ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -6160,7 +6795,10 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); @@ -6178,8 +6816,6 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else @@ -6196,7 +6832,10 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); @@ -6214,8 +6853,6 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else @@ -6274,7 +6911,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6349,7 +6986,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6425,7 +7062,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6499,7 +7136,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6576,7 +7213,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, @@ -6629,7 +7266,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, @@ -6795,13 +7432,15 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, #if defined (TIM20) case TIM_TS_ITR9: #endif /* TIM20 */ +#if defined (HRTIM1) case TIM_TS_ITR10: +#endif /* HRTIM1 */ case TIM_TS_ITR11: - { - /* Check the parameter */ - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger)); - break; - } + { + /* Check the parameter */ + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger)); + break; + } default: break; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.h index fcf095087b6..b7516e4d20b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.h @@ -174,7 +174,7 @@ typedef struct This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -186,7 +186,7 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -315,6 +315,26 @@ typedef enum HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + /** * @brief HAL Active channel structures definition */ @@ -338,13 +358,16 @@ typedef struct __TIM_HandleTypeDef typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ @@ -388,39 +411,39 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - - ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ - ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ - ,HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ - ,HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ - ,HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ - ,HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ + , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ + , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ + , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ + , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** @@ -554,6 +577,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ @@ -647,6 +679,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ @@ -936,7 +977,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} @@ -1182,25 +1223,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** @@ -1426,6 +1491,31 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. @@ -1445,6 +1535,8 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None @@ -1804,6 +1896,9 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) @@ -1826,6 +1921,9 @@ mode. #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ ((__STATE__) == TIM_OCNIDLESTATE_RESET)) +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) @@ -1905,7 +2003,23 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) +#elif defined(TIM20) +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #else #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1922,7 +2036,6 @@ mode. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) #endif /* TIM5 && TIM20 */ @@ -2046,22 +2159,6 @@ mode. ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) #if defined (TIM5) && defined(TIM20) -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR9) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ - ((__SELECTION__) == TIM_TS_ITR11) || \ - ((__SELECTION__) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ @@ -2077,22 +2174,6 @@ mode. ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) #elif defined (TIM5) -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ - ((__SELECTION__) == TIM_TS_ITR11) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ @@ -2105,22 +2186,19 @@ mode. ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) +#elif defined (TIM20) +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR11)|| \ + ((__SELECTION__) == TIM_TS_NONE)) #else -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ - ((__SELECTION__) == TIM_TS_ITR11) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ ((__SELECTION__) == TIM_TS_ITR1) || \ ((__SELECTION__) == TIM_TS_ITR2) || \ @@ -2129,7 +2207,6 @@ mode. ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE)) #endif /* TIM5 && TIM20 */ @@ -2150,15 +2227,15 @@ mode. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ @@ -2215,6 +2292,50 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) + /** * @} */ @@ -2440,6 +2561,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ @@ -2459,7 +2585,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.c index a6a50577105..1ee2f141767 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.c @@ -62,7 +62,7 @@ (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @@ -109,9 +109,11 @@ */ /* End of private constants --------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ @@ -142,6 +144,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status @@ -227,6 +232,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -260,6 +274,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -307,17 +330,43 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -343,6 +392,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -355,10 +410,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -367,8 +441,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -397,6 +478,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -411,29 +498,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -453,8 +547,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -482,9 +583,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -532,6 +638,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -539,8 +654,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -575,6 +697,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -598,6 +723,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -643,8 +777,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -721,6 +862,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -746,24 +890,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -771,11 +916,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) @@ -790,11 +935,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) @@ -809,11 +954,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) @@ -828,11 +973,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) @@ -855,8 +1000,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -929,8 +1081,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -988,6 +1140,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -995,8 +1156,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1030,6 +1198,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1053,6 +1224,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1097,8 +1277,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1176,6 +1363,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1201,35 +1391,37 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) @@ -1244,11 +1436,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) @@ -1263,11 +1455,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) @@ -1282,11 +1474,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_4: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) @@ -1309,8 +1501,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1383,8 +1582,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1424,11 +1623,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Enable the complementary One Pulse output */ + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1449,12 +1664,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1462,6 +1679,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1478,17 +1699,33 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - /* Enable the complementary One Pulse output */ + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1509,6 +1746,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1518,8 +1757,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1527,6 +1767,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1613,14 +1857,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || - (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR10) || - (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) +#elif defined(TIM20) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || + (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || + (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || - (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ @@ -1699,14 +1948,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || - (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR10) || - (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) +#elif defined(TIM20) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || + (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || + (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || - (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ @@ -1786,14 +2040,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || - (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR10) || - (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) +#elif defined(TIM20) + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || + (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || + (InputTrigger == TIM_TS_ITR9) || (InputTrigger == TIM_TS_ITR11)) #else if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || (InputTrigger == TIM_TS_ITR5) || (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || (InputTrigger == TIM_TS_ITR8) || - (InputTrigger == TIM_TS_ITR10) || (InputTrigger == TIM_TS_ITR11)) + (InputTrigger == TIM_TS_ITR11)) #endif /* TIM5 && TIM20 */ { /* Select the Input trigger */ @@ -1840,7 +2099,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); @@ -1873,16 +2132,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; @@ -3125,6 +3387,28 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} /** * @} */ @@ -3177,6 +3461,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) } +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.h index 2db8481e6c1..de04731254a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.h @@ -237,15 +237,23 @@ typedef struct #define TIM_TIM20_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ #define TIM_TIM20_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ #define TIM_TIM20_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#if defined(COMP5) #define TIM_TIM20_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#endif /* COMP5 */ +#if defined(COMP6) #define TIM_TIM20_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#endif /* COMP6 */ +#if defined(COMP7) #define TIM_TIM20_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */ +#endif /* COMP7 */ #define TIM_TIM20_ETR_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC3 analog watchdog 1 */ #define TIM_TIM20_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 2 */ #define TIM_TIM20_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC3 analog watchdog 3 */ +#if defined (ADC5) #define TIM_TIM20_ETR_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 1 */ #define TIM_TIM20_ETR_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC5 analog watchdog 2 */ #define TIM_TIM20_ETR_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 3 */ +#endif /* ADC5 */ #endif /* TIM20 */ /** * @} @@ -594,7 +602,7 @@ typedef struct /** * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency. * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000); - * @note This macro should be used only if ditehring is already enabled + * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __FREQ__ output signal frequency (in Hz) @@ -618,7 +626,7 @@ typedef struct /** * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay. * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10); - * @note This macro should be used only if ditehring is already enabled + * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) @@ -644,7 +652,7 @@ typedef struct /** * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode). * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20); - * @note This macro should be used only if ditehring is already enabled + * @note This macro should be used only if dithering is already enabled * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler * @param __DELAY__ timer output compare active/inactive delay (in us) @@ -1095,8 +1103,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1113,7 +1120,6 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ @@ -1130,8 +1136,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1147,8 +1152,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1164,8 +1168,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1181,8 +1184,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1196,8 +1198,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))) + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ @@ -1212,8 +1213,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1228,7 +1228,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ @@ -1243,8 +1242,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1258,8 +1256,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM5) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1273,8 +1270,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1288,8 +1284,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1302,8 +1297,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR4) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)))) + ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ @@ -1315,7 +1309,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ @@ -1327,7 +1320,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ @@ -1340,7 +1332,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ @@ -1352,7 +1343,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM5) && \ @@ -1364,7 +1354,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ @@ -1376,7 +1365,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ @@ -1388,10 +1376,8 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE)))) - -#else +#elif defined(TIM20) #define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ ((((INSTANCE) == TIM1) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1407,7 +1393,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM2) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1423,7 +1409,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ @@ -1440,7 +1426,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM4) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1456,7 +1442,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM8) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1472,7 +1458,7 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ || \ (((INSTANCE) == TIM15) && \ (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ @@ -1486,7 +1472,291 @@ typedef struct ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10)))) + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \ + || \ + (((INSTANCE) == TIM20) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) + +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR11))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM8) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM15) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9))) \ + || \ + (((INSTANCE) == TIM20) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8)))) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_ITR11)|| \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM8) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM15) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR9) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM20) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE)))) +#else +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + ((((INSTANCE) == TIM1) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM4) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM8) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM15) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) #define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ @@ -1500,8 +1770,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM2) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1515,7 +1784,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10) || \ ((__SELECTION__) == TIM_TS_ITR11))) \ || \ (((INSTANCE) == TIM3) && \ @@ -1529,8 +1797,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM4) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1543,8 +1810,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM8) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1557,8 +1823,7 @@ typedef struct ((__SELECTION__) == TIM_TS_ETRF) || \ ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10))) \ + ((__SELECTION__) == TIM_TS_ITR8))) \ || \ (((INSTANCE) == TIM15) && \ (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1570,8 +1835,7 @@ typedef struct ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)))) + ((__SELECTION__) == TIM_TS_ITR8)))) #define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ ((((INSTANCE) == TIM1) && \ @@ -1582,7 +1846,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM2) && \ @@ -1593,7 +1856,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_ITR11)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ @@ -1605,7 +1867,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM4) && \ @@ -1616,7 +1877,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM8) && \ @@ -1627,7 +1887,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR6) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE))) \ || \ (((INSTANCE) == TIM15) && \ @@ -1638,7 +1897,6 @@ typedef struct ((__SELECTION__) == TIM_TS_ITR5) || \ ((__SELECTION__) == TIM_TS_ITR7) || \ ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR10)|| \ ((__SELECTION__) == TIM_TS_NONE)))) #endif /* TIM5 && TIM20 */ @@ -1839,6 +2097,7 @@ void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.c index 9bb0ed64233..15d681ada88 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.c @@ -39,7 +39,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. @@ -191,6 +192,8 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ @@ -842,55 +845,57 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR switch (CallbackID) { case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_UART_WAKEUP_CB_ID : - huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ break; case HAL_UART_RX_FIFO_FULL_CB_ID : - huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_UART_TX_FIFO_EMPTY_CB_ID : - huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -998,13 +1003,16 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. If user wants to abort it, Abort services should be called by user. (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -1047,7 +1055,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); huart->TxXferSize = Size; @@ -1065,6 +1073,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u pdata16bits = NULL; } + __HAL_UNLOCK(huart); + while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) @@ -1092,8 +1102,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1137,7 +1145,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); huart->RxXferSize = Size; @@ -1159,6 +1167,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } + __HAL_UNLOCK(huart); + /* as long as data have to be received */ while (huart->RxXferCount > 0U) { @@ -1182,8 +1192,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1552,7 +1560,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); SET_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -1648,7 +1656,8 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); /* Disable the UART DMA Tx request if enabled */ @@ -1861,7 +1870,8 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) uint32_t abortcplt = 1U; /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised @@ -2184,7 +2194,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); if (errorflags == 0U) { /* UART in mode Receiver ---------------------------------------------------*/ @@ -2203,7 +2213,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* If some errors occur */ if ((errorflags != 0U) && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) @@ -2239,10 +2249,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->ErrorCode |= HAL_UART_ERROR_ORE; } - /* Call UART Error Call back function if need be --------------------------*/ + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) { - /* UART in mode Receiver ---------------------------------------------------*/ + /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_RXFTIE) != 0U))) @@ -2253,11 +2271,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } } - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ errorcode = huart->ErrorCode; if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - ((errorcode & HAL_UART_ERROR_ORE) != 0U)) + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, @@ -2523,6 +2544,9 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) =============================================================================== [..] This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode @@ -2536,6 +2560,99 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) * @{ */ +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + /** * @brief Enable UART in mute mode (does not mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). @@ -2750,9 +2867,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; - uint32_t usartdiv = 0x00000000U; + uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - uint32_t lpuart_ker_ck_pres = 0x00000000U; + uint32_t lpuart_ker_ck_pres; uint32_t pclk; /* Check the parameters */ @@ -2819,26 +2936,30 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); break; case UART_CLOCKSOURCE_HSI: - lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: - lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetSysClockFreq(); break; case UART_CLOCKSOURCE_LSE: - lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } - /* if proper clock source reported */ - if (lpuart_ker_ck_pres != 0U) + /* If proper clock source reported */ + if (pclk != 0U) { - /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) { @@ -2846,28 +2967,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) } else { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_HSI: - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - case UART_CLOCKSOURCE_LSE: - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - break; - default: - ret = HAL_ERROR; - break; - } - - /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) { huart->Instance->BRR = usartdiv; @@ -2876,8 +2978,9 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { ret = HAL_ERROR; } - } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ - } /* if (lpuart_ker_ck_pres != 0) */ + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) @@ -2886,37 +2989,39 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else + if (pclk != 0U) { - ret = HAL_ERROR; + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } } } else @@ -2925,35 +3030,37 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } - /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + if (pclk != 0U) { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } } } @@ -3054,7 +3161,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -3108,7 +3215,8 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3119,6 +3227,29 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_TIMEOUT; } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } } } return HAL_OK; @@ -3497,7 +3628,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) } /** - * @brief TX interrrupt handler for 7 or 8 bits data word length . + * @brief TX interrupt handler for 7 or 8 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3526,7 +3657,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 9 bits data word length. + * @brief TX interrupt handler for 9 bits data word length. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3558,7 +3689,7 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3598,7 +3729,7 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3666,7 +3797,7 @@ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ @@ -3714,7 +3845,7 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 9 bits data word length . + * @brief RX interrupt handler for 9 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -3766,7 +3897,7 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -3794,7 +3925,8 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ @@ -3838,7 +3970,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -3868,7 +4000,8 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.h index 002d35ad970..bf38d1a578a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.h @@ -50,16 +50,18 @@ typedef struct The baud rate register is computed using the following formula: LPUART: ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) where lpuart_ker_ck_pres is the UART input clock divided by a prescaler UART: ===== - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 where uart_ker_ck_pres is the UART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. @@ -82,7 +84,8 @@ typedef struct or disabled. This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). This parameter can be a value of @ref UART_Over_Sampling. */ uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. @@ -101,7 +104,8 @@ typedef struct { uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . - This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. This parameter can be a value of @ref UART_Tx_Inv. */ @@ -133,11 +137,10 @@ typedef struct This parameter can be a value of @ref UART_MSB_First. */ } UART_AdvFeatureInitTypeDef; - - /** * @brief HAL UART State definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). * - gState contains UART state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -221,9 +224,9 @@ typedef struct __UART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ @@ -232,11 +235,11 @@ typedef struct __UART_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /*!< UART Error code */ @@ -312,8 +315,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ #define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ #define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error @@ -331,8 +334,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ #define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ #define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -429,19 +434,23 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ /** * @} */ -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ /** * @} */ @@ -594,8 +603,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ /** * @} */ @@ -621,7 +632,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ /** * @} */ @@ -629,9 +640,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ /** * @} */ @@ -648,7 +660,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ /** * @} */ @@ -656,7 +669,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ /** * @} */ @@ -695,6 +709,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ #define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ #define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ #define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ #define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ #define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ @@ -730,27 +745,28 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ -#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ -#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ -#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ -#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ - -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ - -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ @@ -769,6 +785,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ /** * @} */ @@ -822,6 +839,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag @@ -890,6 +908,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_FLAG_TC Transmission Complete flag * @arg @ref UART_FLAG_RXNE Receive data register not empty flag * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag * @arg @ref UART_FLAG_IDLE Idle Line detection flag * @arg @ref UART_FLAG_ORE Overrun Error flag * @arg @ref UART_FLAG_NE Noise Error flag @@ -916,15 +935,21 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disable the specified UART interrupt. * @param __HANDLE__ specifies the UART Handle. @@ -943,14 +968,21 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. * @param __HANDLE__ specifies the UART Handle. @@ -969,6 +1001,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) @@ -994,14 +1027,19 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -1013,6 +1051,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag @@ -1067,8 +1106,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1085,8 +1125,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1103,8 +1144,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1121,8 +1163,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1157,14 +1200,17 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. * @param __BAUD__ Baud rate set by the user. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\ - + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1172,8 +1218,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\ - + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1181,8 +1227,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\ - + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__ specifies the UART Handle. @@ -1294,8 +1340,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** * @brief Ensure that UART LIN state is valid. @@ -1416,8 +1469,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. @@ -1494,6 +1548,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #include "stm32g4xx_hal_uart_ex.h" +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; + + /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1564,6 +1623,10 @@ void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); */ /* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.c index 818203910e6..fe2678b90ca 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.c @@ -336,9 +336,6 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) * @{ */ - - - /** * @brief By default in multiprocessor mode, when the wake up method is set * to address mark, the UART handles only 4-bit long addresses detection; @@ -419,7 +416,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Wait until REACK flag is set */ @@ -711,8 +708,10 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; } } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.h index f3582bd5dce..2450681d71a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.h @@ -69,9 +69,9 @@ typedef struct /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ @@ -79,8 +79,8 @@ typedef struct /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ @@ -89,8 +89,8 @@ typedef struct * @brief UART FIFO mode * @{ */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ /** * @} */ @@ -166,7 +166,9 @@ void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.c index c9449d8a14c..9e22904252f 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.c @@ -39,7 +39,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode (Receiver/Transmitter) in the husart handle Init structure. @@ -317,7 +318,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ husart->Instance->CR2 &= ~USART_CR2_LINEN; husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); @@ -531,9 +533,9 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US } /** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @param husart uart handle + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID @@ -561,47 +563,47 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ switch (CallbackID) { case HAL_USART_TX_HALFCOMPLETE_CB_ID : - husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_USART_TX_COMPLETE_CB_ID : - husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_USART_RX_HALFCOMPLETE_CB_ID : - husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_USART_RX_COMPLETE_CB_ID : - husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_USART_TX_RX_COMPLETE_CB_ID : - husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ break; case HAL_USART_ERROR_CB_ID : - husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_USART_ABORT_COMPLETE_CB_ID : - husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_USART_RX_FIFO_FULL_CB_ID : - husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_USART_TX_FIFO_EMPTY_CB_ID : - husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_USART_MSPINIT_CB_ID : - husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_USART_MSPDEINIT_CB_ID : - husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -720,13 +722,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify + error type, and HAL_USART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on USART side. If user wants to abort it, Abort services should be called by user. (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -734,7 +739,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /** * @brief Simplex send an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -762,7 +767,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); husart->TxXferSize = Size; @@ -831,7 +836,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -860,7 +865,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); husart->RxXferSize = Size; @@ -942,7 +947,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -976,7 +981,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); husart->RxXferSize = Size; @@ -1091,7 +1096,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Send an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -1174,7 +1179,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Receive an amount of data in interrupt mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -1277,7 +1282,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -1376,7 +1381,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Send an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -1461,7 +1466,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -1577,7 +1582,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -1768,7 +1773,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -2091,7 +2096,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | + USART_ISR_UDR)); if (errorflags == 0U) { /* USART in mode Receiver ---------------------------------------------------*/ @@ -2146,6 +2152,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->ErrorCode |= HAL_USART_ERROR_ORE; } + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + /* USART SPI slave underrun error interrupt occurred -------------------------*/ if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { @@ -2943,7 +2957,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) /* Initialize the USART ErrorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -3412,7 +3426,8 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Clear RxISR function pointer */ @@ -3546,7 +3561,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Clear RxISR function pointer */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.h index 4e94aa43c4a..a51ac4e2e6a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.h @@ -48,11 +48,15 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler. - @note Oversampling by 8 is systematically applied to achieve high baud rates. */ + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) + divided by a prescaler. + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USARTEx_Word_Length. */ @@ -226,6 +230,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) #define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -350,6 +355,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ #define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ #define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ #define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ #define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ #define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ @@ -404,6 +410,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ #define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ /** * @} */ @@ -460,6 +467,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_FLAG_TC Transmission Complete flag * @arg @ref USART_FLAG_RXNE Receive data register not empty flag * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag * @arg @ref USART_FLAG_IDLE Idle Line detection flag * @arg @ref USART_FLAG_ORE OverRun Error flag * @arg @ref USART_FLAG_NE Noise Error flag @@ -480,6 +488,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag * @retval None */ @@ -545,9 +554,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -567,10 +579,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) - +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -593,7 +607,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) + & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -615,10 +630,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) - +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the USART Handle. @@ -630,6 +648,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None @@ -701,11 +720,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. + * @param __CLOCKPRESCALER__ USART prescaler value. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ - + ((__BAUD__)/2U)) / (__BAUD__)) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\ + (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Report the USART clock source. * @param __HANDLE__ specifies the USART Handle. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.c index 6da75be9d80..a013c54de0a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.c @@ -57,10 +57,10 @@ /** @defgroup USARTEx_Private_Constants USARTEx Private Constants * @{ */ -/* UART RX FIFO depth */ +/* USART RX FIFO depth */ #define RX_FIFO_DEPTH 8U -/* UART TX FIFO depth */ +/* USART TX FIFO depth */ #define TX_FIFO_DEPTH 8U /** * @} @@ -243,7 +243,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) /* Restore USART configuration */ WRITE_REG(husart->Instance->CR1, tmpcr1); - husart->SlaveMode = USART_SLAVEMODE_ENABLE; + husart->SlaveMode = USART_SLAVEMODE_DISABLE; husart->State = HAL_USART_STATE_READY; @@ -515,10 +515,14 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) { rx_fifo_depth = RX_FIFO_DEPTH; tx_fifo_depth = TX_FIFO_DEPTH; - rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); - tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); - husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); + tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); + husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; } } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.h index be45e6028d7..96a67cdf8cb 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.h @@ -46,7 +46,7 @@ extern "C" { * @{ */ #define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} @@ -169,7 +169,6 @@ extern "C" { } \ } while(0U) - /** * @brief Ensure that USART frame length is valid. * @param __LENGTH__ USART frame length. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c index 92f8ec5a2c6..01ed73bdc2b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c @@ -32,12 +32,11 @@ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: - (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler: - max timeout before reset: ~73.14�s - (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128: - max timeout before reset: ~599.18ms + (++) Counter min (T[5;0] = 0x00) at 170MHz (PCLK1) with zero prescaler: + max timeout before reset: approximately 24.09�s + (++) Counter max (T[5;0] = 0x3F) at 170MHz (PCLK1) with prescaler dividing by 128: + max timeout before reset: approximately 197.38ms - ============================================================================== ##### How to use this driver ##### ============================================================================== @@ -67,26 +66,26 @@ [..] The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions - @ref HAL_WWDG_RegisterCallback() to register a user callback. + HAL_WWDG_RegisterCallback() to register a user callback. - (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following + (+) Function HAL_WWDG_RegisterCallback() allows to register following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to - the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback() + (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. [..] - When calling @ref HAL_WWDG_Init function, callbacks are reset to the + When calling HAL_WWDG_Init function, callbacks are reset to the corresponding legacy weak (surcharged) functions: - @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. [..] @@ -198,7 +197,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) #else /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /* Set WWDG Counter */ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); @@ -243,7 +242,8 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -304,7 +304,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD return status; } -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} @@ -372,7 +372,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) #else /* Early Wakeup callback */ HAL_WWDG_EarlyWakeupCallback(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } } } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.h index 0299d7f4931..a79a9ffe05b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.h @@ -56,7 +56,7 @@ typedef struct uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ - uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not. This parameter can be a value of @ref WWDG_EWI_Mode */ } WWDG_InitTypeDef; @@ -68,17 +68,17 @@ typedef struct typedef struct __WWDG_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ { WWDG_TypeDef *Instance; /*!< Register base address */ WWDG_InitTypeDef Init; /*!< WWDG required parameters */ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) - void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ - void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ -#endif + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } WWDG_HandleTypeDef; #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) @@ -87,8 +87,8 @@ typedef struct */ typedef enum { - HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */ - HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */ + HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ } HAL_WWDG_CallbackIDTypeDef; /** @@ -96,7 +96,7 @@ typedef enum */ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} */ @@ -268,9 +268,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} @@ -303,6 +304,6 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); } #endif -#endif /* __STM32G4xx_HAL_WWDG_H */ +#endif /* STM32G4xx_HAL_WWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.c index 531b7d8fe64..d5f4a173370 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.c @@ -273,6 +273,47 @@ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ + ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \ + || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ + && ( \ + ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) \ + ) \ + || (((__ADC_INSTANCE__) == ADC3) \ + && ( \ + ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \ + ) \ + ) \ + ) #endif #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ @@ -473,6 +514,46 @@ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ + ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \ + || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ + && ( \ + ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ + ) \ + ) \ + || ((((__ADC_INSTANCE__) == ADC3)) \ + && ( \ + ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \ + ) \ + ) \ + ) #endif #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ @@ -563,7 +644,7 @@ * the same ADC common instance to their default reset values. * @note This function is performing a hard reset, using high level * clock source RCC ADC reset. - * Caution: On this STM32 serie, if several ADC instances are available + * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * To de-initialize only 1 ADC instance, use @@ -635,7 +716,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ - /* On this STM32 serie, setting of these features is conditioned to */ + /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) @@ -722,7 +803,7 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) * is in an unknown state. * In this case, perform a hard reset using high level * clock source RCC ADC reset. - * Caution: On this STM32 serie, if several ADC instances are available + * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * Refer to function @ref LL_ADC_CommonDeInit(). @@ -942,7 +1023,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS); /* Reset register OFR4 */ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS); - + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* Note: bits in access mode read only, no direct reset applicable */ @@ -966,10 +1047,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* ADC instance is in an unknown state */ /* Need to performing a hard reset of ADC instance, using high level */ /* clock source RCC ADC reset. */ - /* Caution: On this STM32 serie, if several ADC instances are available */ + /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ - /* Caution: On this STM32 serie, if several ADC instances are available */ + /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ status = ERROR; @@ -1127,7 +1208,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* - Set ADC group regular conversion data transfer: no transfer or */ /* transfer by DMA, and DMA requests mode */ /* - Set ADC group regular overrun behavior */ - /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { @@ -1189,7 +1270,7 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { /* Set ADC_REG_InitStruct fields to default values */ /* Set fields of ADC group regular */ - /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; @@ -1256,7 +1337,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* - Set ADC group injected sequencer discontinuous mode */ /* - Set ADC group injected conversion trigger: independent or */ /* from ADC group regular */ - /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.h index f6870c9a7a8..beb7ba63050 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.h @@ -394,7 +394,7 @@ typedef struct { uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - @note On this STM32 serie, if ADC group injected is used, some + @note On this STM32 series, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual. @@ -481,7 +481,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge + @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). @@ -541,7 +541,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE - @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge + @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). @@ -683,7 +683,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */ @@ -706,7 +706,7 @@ typedef struct * @{ */ #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ @@ -789,17 +789,17 @@ typedef struct #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 serie, ADC channel available on all instances but ADC2. */ -#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC1 instance. */ -#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ -#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 serie, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ -#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 serie, ADC channel available only on ADC1 instance. */ -#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 serie, ADC channel available only on ADC2 instance. */ -#define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC2 instance. */ -#define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ -#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */ -#define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */ -#define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 serie, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */ +#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */ +#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */ +#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */ +#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */ +#define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */ +#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */ +#define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */ +#define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */ /** * @} */ @@ -815,39 +815,39 @@ typedef struct ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< @@ -858,60 +858,60 @@ typedef struct ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** @@ -1053,33 +1053,33 @@ typedef struct ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< @@ -1090,62 +1090,62 @@ typedef struct ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances */ #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Trigger available only on ADC3/4/5 instances. On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). - Trigger available only on ADC1/2 instances. On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */ #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ + Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */ #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). - Note: On this STM32 serie, this trigger is available only on ADC1/2 instances. */ + Note: On this STM32 series, this trigger is available only on ADC1/2 instances. */ #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */ /** @@ -1499,7 +1499,7 @@ typedef struct /* configuration (system clock versus ADC clock), */ /* and therefore must be defined in user application. */ /* Indications for estimation of ADC timeout delays, for this */ -/* STM32 serie: */ +/* STM32 series: */ /* - ADC calibration time: maximum delay is 112/fADC. */ /* (refer to device datasheet, parameter "tCAL") */ /* - ADC enable time: maximum delay is 1 conversion cycle. */ @@ -1530,7 +1530,7 @@ typedef struct #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ -/* Note: On this STM32 serie, a minimum number of ADC clock cycles */ +/* Note: On this STM32 series, a minimum number of ADC clock cycles */ /* are required between ADC end of calibration and ADC enable. */ /* Wait time can be computed in user application by waiting for the */ /* equivalent number of CPU cycles, by taking into account */ @@ -1628,7 +1628,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value between Min_Data=0 and Max_Data=18 @@ -1690,7 +1690,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -1768,7 +1768,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). @@ -1829,7 +1829,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: @@ -1890,7 +1890,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected. */ @@ -1981,6 +1981,32 @@ typedef struct ) \ ) \ ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ((((__ADC_INSTANCE__) == ADC1) \ + &&( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ + ) \ + ) \ + || \ + (((__ADC_INSTANCE__) == ADC2) \ + &&( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \ + ) \ + ) \ + || \ + (((__ADC_INSTANCE__) == ADC3) \ + &&( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \ + ) \ + ) \ + ) #endif /** @@ -2031,7 +2057,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -2145,7 +2171,7 @@ typedef struct * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ @@ -2435,7 +2461,7 @@ typedef struct * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. - * @note On this STM32 serie, calibration data of internal voltage reference + * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. @@ -2484,7 +2510,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 serie, calibration data of temperature sensor + * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. @@ -2632,7 +2658,7 @@ typedef struct #if defined(ADC_MULTIMODE_SUPPORT) __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { @@ -2668,11 +2694,11 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis /** * @brief Set parameter common to several ADC: Clock source and prescaler. - * @note On this STM32 serie, if ADC group injected is used, some + * @note On this STM32 series, if ADC group injected is used, some * clock ratio constraints between ADC clock and AHB clock * must be respected. * Refer to reference manual. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -2734,11 +2760,13 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) } /** - * @brief Set parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Configure all paths (overwrite current configuration). * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * The values not selected are removed from configuration. * @note Stabilization time of measurement path to internal channel: * After enabling internal paths, before starting ADC conversion, * a delay is required for internal voltage reference and @@ -2767,6 +2795,65 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); } +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Add paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n + * CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + SET_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Remove paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n + * CCR VBATSEL LL_ADC_SetCommonPathInternalChRem + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); +} + /** * @brief Get parameter common to several ADC: measurement path to internal * channels (VrefInt, temperature sensor, ...). @@ -2814,7 +2901,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx * both calibration factors must be concatenated. * To perform this processing, use helper macro * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. @@ -2864,7 +2951,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t * @brief Set ADC resolution. * Refer to reference manual for alignments formats * dependencies to ADC resolutions. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -2903,7 +2990,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) * @brief Set ADC conversion data alignment. * @note Refer to reference manual for alignments formats * dependencies to ADC resolutions. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -2951,9 +3038,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -2971,7 +3061,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) * Therefore, the ADC conversion data may be outdated: does not * correspond to the current voltage level on the selected * ADC channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3004,9 +3094,12 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -3050,7 +3143,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * to disable state using function LL_ADC_SetOffsetState(). * @note If a channel is mapped on several offsets numbers, only the offset * with the lowest value is considered for the subtraction. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3113,7 +3206,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF @@ -3121,7 +3214,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, @@ -3195,7 +3288,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -3204,7 +3297,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); } @@ -3230,7 +3323,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1); } @@ -3242,7 +3335,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse * @note This function should be needed only in case of offset to be * enabled-disabled dynamically, and should not be needed in other cases: * function LL_ADC_SetOffset() automatically enables the offset. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3263,7 +3356,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSET1_EN, @@ -3289,7 +3382,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN); } @@ -3297,7 +3390,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse /** * @brief Set for the ADC selected offset number 1, 2, 3 or 4: * choose offset sign. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3318,7 +3411,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse */ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_OFFSETPOS, @@ -3344,7 +3437,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS); } @@ -3352,7 +3445,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offset /** * @brief Set for the ADC selected offset number 1, 2, 3 or 4: * choose offset saturation mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3373,7 +3466,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offset */ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); MODIFY_REG(*preg, ADC_OFR1_SATEN, @@ -3399,7 +3492,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offs */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN); } @@ -3411,8 +3504,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t * DATA = DATA(raw) * (gain compensation coef) / 4096 * @note This function enables the gain compensation if given * coefficient is above 0, otherwise it disables it. - * @note Gain compensation when enabled is appied to all channels. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note Gain compensation when enabled is applied to all channels. + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3448,7 +3541,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx) /** * @brief Set ADC sampling time common configuration impacting * settings of sampling time channel wise. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3491,7 +3584,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) * @brief Set ADC group regular conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). - * @note On this STM32 serie, setting trigger source to external trigger + * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). @@ -3499,7 +3592,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) * function @ref LL_ADC_REG_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3548,9 +3641,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) @@ -3615,17 +3708,17 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2) * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); + __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */ /* to match with triggers literals definition. */ @@ -3654,7 +3747,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) /** * @brief Set ADC group regular conversion trigger polarity. * @note Applicable only for trigger source set to external trigger. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3690,8 +3783,8 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) * @brief Set ADC sampling mode. * @note This function set the ADC conversion sampling mode * @note This mode applies to regular group only. - * @note Set sampling mode is appied to all conversion of regular group. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note Set sampling mode is applied to all conversion of regular group. + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3753,7 +3846,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx) * function "LL_ADC_REG_SetSequencerChannels()". * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3845,7 +3938,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) * continuous mode and sequencer discontinuous mode. * @note It is not possible to enable both ADC auto-injected mode * and ADC group regular sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3898,17 +3991,17 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @note This function performs configuration of: * - Channels ordering into each rank of scan sequence: * whatever channel can be placed into whatever rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3985,7 +4078,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval None @@ -3996,7 +4089,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), @@ -4006,7 +4099,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /** * @brief Get ADC group regular sequence: channel on the selected * scan sequence rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). @@ -4096,7 +4189,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -4105,7 +4198,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -4121,7 +4214,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * conversions launched successively automatically. * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -4176,7 +4269,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). * @note To configure DMA source address (peripheral address), * use function @ref LL_ADC_DMA_GetRegAddr(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4238,7 +4331,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) * The default setting of overrun is data preserved. * Therefore, for compatibility with all devices, parameter * overrun should be set to data overwritten. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -4280,7 +4373,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * @brief Set ADC group injected conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). - * @note On this STM32 serie, setting trigger source to external trigger + * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). @@ -4288,7 +4381,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * function @ref LL_ADC_INJ_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4336,9 +4429,9 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval None */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) @@ -4402,17 +4495,17 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { - register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); + __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */ /* to match with triggers literals definition. */ @@ -4441,7 +4534,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) /** * @brief Set ADC group injected conversion trigger polarity. * Applicable only for trigger source set to external trigger. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4481,7 +4574,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) * scan direction is forward (from rank 1 to rank n). * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4558,13 +4651,13 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * sequence rank. * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4617,7 +4710,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval None @@ -4698,7 +4791,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, @@ -4732,7 +4825,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * from ADC group regular. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4790,7 +4883,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * on either groups regular or injected. * @note A modification of the context mode (bit JQDIS) causes the contexts * queue to be flushed and the register JSQR is cleared. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4840,13 +4933,13 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_GetTriggerSource() * @arg @ref LL_ADC_INJ_GetTriggerEdge() * @arg @ref LL_ADC_INJ_GetSequencerRanks() - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32G4, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN1..5). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4899,9 +4992,9 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1) * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT * - * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n - * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5. - * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n + * (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5. + * On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @param ExternalTriggerEdge This parameter can be one of the following values: * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING @@ -4953,7 +5046,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param Rank2_Channel This parameter can be one of the following values: @@ -4995,7 +5088,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param Rank3_Channel This parameter can be one of the following values: @@ -5037,7 +5130,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param Rank4_Channel This parameter can be one of the following values: @@ -5079,7 +5172,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval None @@ -5099,7 +5192,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, /* because containing other bits reserved for other purpose. */ /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ - register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); + uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | @@ -5139,7 +5232,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * Refer to device datasheet for timings values (parameters TS_vrefint, * TS_temp, ...). * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 serie, ADC processing time is: + * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits @@ -5148,7 +5241,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * temperature sensor, ...), a sampling time minimum value * is required. * Refer to device datasheet. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5211,7 +5304,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @param SamplingTime This parameter can be one of the following values: @@ -5235,7 +5328,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), @@ -5248,7 +5341,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @note On this device, sampling time is on channel scope: independently * of channel mapped on ADC group regular or injected. * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 serie, ADC processing time is: + * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits @@ -5312,7 +5405,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution. * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n * @retval Returned value can be one of the following values: @@ -5331,7 +5424,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)) @@ -5366,7 +5459,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @note For ADC channels configured in differential mode, both inputs * should be biased at (Vref+)/2 +/-200mV. * (Vref+ is the analog voltage reference) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @note One or several values can be selected. @@ -5473,7 +5566,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * @note In case of need to define a single channel to monitor * with analog watchdog from sequencer channel definition, * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5494,7 +5587,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5613,7 +5706,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n - * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details. + * - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details. * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) @@ -5622,7 +5715,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* in register and register position depending on parameter "AWDy". */ /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, @@ -5645,7 +5738,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Applicable only when the analog watchdog is set to monitor * one channel. - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5666,7 +5759,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5754,10 +5847,10 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ @@ -5816,7 +5909,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5864,7 +5957,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* "AWDy". */ /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, ADC_TR1_HT1 | ADC_TR1_LT1, @@ -5879,7 +5972,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5904,7 +5997,7 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t * impacted: the comparison of analog watchdog thresholds is done on * oversampling final computation (after ratio and shift application): * ADC data register bitfield [15:4] (12 most significant bits). - * @note On this STM32 serie, setting of this feature is not conditioned to + * @note On this STM32 series, setting of this feature is not conditioned to * ADC state: * ADC can be disabled, enabled with or without conversion on going * on either ADC groups regular or injected. @@ -5933,7 +6026,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, AWDThresholdsHighLow, @@ -5970,7 +6063,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) @@ -5980,11 +6073,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ /** * @brief Set ADC analog watchdog filtering configuration - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @note On this STM32 serie, this feature is only available on first + * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration * @param ADCx ADC instance @@ -6010,7 +6103,7 @@ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint /** * @brief Get ADC analog watchdog filtering configuration - * @note On this STM32 serie, this feature is only available on first + * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration * @param ADCx ADC instance @@ -6050,7 +6143,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -6104,11 +6197,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) * are done from 1 trigger) * - discontinuous mode (each conversion of oversampling ratio * needs a trigger) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @note On this STM32 serie, oversampling discontinuous mode + * @note On this STM32 series, oversampling discontinuous mode * (triggered mode) can be used only when oversampling is * set on group regular only and in resumed mode. * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont @@ -6148,7 +6241,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) * @note This function set the 2 items of oversampling configuration: * - ratio * - shift - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -6237,7 +6330,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) * @note If multimode configuration: the selected ADC instance is * either master or slave depending on hardware. * Refer to reference manual. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -6316,7 +6409,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) * A macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled * or enabled without conversion on going on group regular. @@ -6390,7 +6483,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_CO * - ADC resolution 10 bits can have maximum delay of 10 cycles. * - ADC resolution 8 bits can have maximum delay of 8 cycles. * - ADC resolution 6 bits can have maximum delay of 6 cycles. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -6465,7 +6558,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADC * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown @@ -6488,7 +6581,7 @@ __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown @@ -6516,12 +6609,12 @@ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) /** * @brief Enable ADC instance internal voltage regulator. - * @note On this STM32 serie, after ADC internal voltage regulator enable, + * @note On this STM32 series, after ADC internal voltage regulator enable, * a delay for ADC internal voltage regulator stabilization * is required before performing a ADC calibration or ADC enable. * Refer to device datasheet, parameter tADCVREG_STUP. * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator @@ -6540,7 +6633,7 @@ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) /** * @brief Disable ADC internal voltage regulator. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator @@ -6565,14 +6658,14 @@ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) /** * @brief Enable the selected ADC instance. - * @note On this STM32 serie, after ADC enable, a delay for + * @note On this STM32 series, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled and ADC internal voltage regulator enabled. * @rmtoll CR ADEN LL_ADC_Enable @@ -6591,7 +6684,7 @@ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) /** * @brief Disable the selected ADC instance. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be not disabled. Must be enabled without conversion on going * on either groups regular or injected. @@ -6611,7 +6704,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) /** * @brief Get the selected ADC instance enable state. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll CR ADEN LL_ADC_IsEnabled @@ -6637,7 +6730,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) /** * @brief Start ADC calibration in the mode single-ended * or differential (for devices with differential mode available). - * @note On this STM32 serie, a minimum number of ADC clock cycles + * @note On this STM32 series, a minimum number of ADC clock cycles * are required between ADC end of calibration and ADC enable. * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. * @note For devices with differential mode available: @@ -6646,7 +6739,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) * (calibration run must be performed for each of these * differential modes, if used afterwards and if the application * requires their calibration). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADCAL LL_ADC_StartCalibration\n @@ -6688,14 +6781,14 @@ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) /** * @brief Start ADC group regular conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, @@ -6716,7 +6809,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) /** * @brief Stop ADC group regular conversion. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group regular, * without ADC disable command on going. @@ -6762,7 +6855,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set * using @ref LL_ADC_REG_SetSamplingMode * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, @@ -6784,7 +6877,7 @@ __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx) * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source * - @ref LL_ADC_REG_StartSamplingPhase has been called to start * the sampling phase - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, @@ -6913,14 +7006,14 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef /** * @brief Start ADC group injected conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group injected, * without conversion stop command on going on group injected, @@ -6941,7 +7034,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) /** * @brief Stop ADC group injected conversion. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group injected, * without ADC disable command on going. @@ -7000,7 +7093,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7027,7 +7120,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7054,7 +7147,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7081,7 +7174,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7108,7 +7201,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { - register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -7125,7 +7218,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32 /** * @brief Get flag ADC ready. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY @@ -7249,7 +7342,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) /** * @brief Clear flag ADC ready. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_comp.c index 9dc0ecc1364..6b2c064151a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_comp.c @@ -49,7 +49,7 @@ /* Check of parameters for configuration of COMP hierarchical scope: */ /* COMP instance. */ -/* Note: On this STM32 serie, comparator input plus parameters are */ +/* Note: On this STM32 series, comparator input plus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ @@ -93,7 +93,7 @@ (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) || \ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1)) \ )) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) || \ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) || \ @@ -221,6 +221,39 @@ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \ ) +#elif defined(STM32G491xx) || defined(STM32G4A1xx) +#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ + || \ + (((__INSTANCE__) == COMP3) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ + || \ + (((__INSTANCE__) == COMP4) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \ + ) #endif /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_comp.h index 2a078a82a88..e82f2c9ca76 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_comp.h @@ -43,6 +43,14 @@ extern "C" { /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ +/** @defgroup COMP_LL_Private_Macros COMP Private Macros + * @{ + */ + +/** + * @} + */ + /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure @@ -282,7 +290,7 @@ typedef struct * @note In case of comparator input selected to be connected to IO: * GPIO pins are specific to each comparator instance. * Refer to description of parameters or to reference manual. - * @note On this STM32 serie, scaler bridge is configurable: + * @note On this STM32 series, scaler bridge is configurable: * to optimize power consumption, this function enables the * voltage scaler bridge only when required * (when selecting comparator input based on VrefInt: VrefInt or @@ -365,7 +373,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) * @note In case of comparator input selected to be connected to IO: * GPIO pins are specific to each comparator instance. * Refer to description of parameters or to reference manual. - * @note On this STM32 serie, scaler bridge is configurable: + * @note On this STM32 series, scaler bridge is configurable: * to optimize power consumption, this function enables the * voltage scaler bridge only when required * (when selecting comparator input based on VrefInt: VrefInt or @@ -689,7 +697,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) /** * @brief Read comparator instance output level. - * @note On this STM32 serie, comparator 'value' is taken before + * @note On this STM32 series, comparator 'value' is taken before * polarity and blanking are applied, thus: * - Comparator output is low when the input plus * is at a lower voltage than the input minus diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.h index 44ecaf91d23..5e1126d5785 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.h @@ -139,7 +139,7 @@ extern "C" { * @{ */ #define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data ouput (Q1.31 format), or two 16-bit + 32-bit data output (Q1.31 format), or two 16-bit data output (Q1.15 format) packed in one 32 bits Data */ #define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output (Q1.31 format) */ @@ -240,7 +240,7 @@ extern "C" { * CSR NARGS LL_CORDIC_Configure\n * CSR NRES LL_CORDIC_Configure\n * CSR ARGSIZE LL_CORDIC_Configure\n - * CSR RESSIZE LL_CORDIC_Configure + * CSR RESIZE LL_CORDIC_Configure * @param CORDICx CORDIC instance * @param Function parameter can be one of the following values: * @arg @ref LL_CORDIC_FUNCTION_COSINE @@ -519,7 +519,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx) /** * @brief Configure width of output data. - * @rmtoll CSR RESSIZE LL_CORDIC_SetOutSize + * @rmtoll CSR RESIZE LL_CORDIC_SetOutSize * @param CORDICx CORDIC Instance * @param OutSize parameter can be one of the following values: * @arg @ref LL_CORDIC_OUTSIZE_32BITS @@ -533,7 +533,7 @@ __STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutS /** * @brief Return width of output data. - * @rmtoll CSR RESSIZE LL_CORDIC_GetOutSize + * @rmtoll CSR RESIZE LL_CORDIC_GetOutSize * @param CORDICx CORDIC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_CORDIC_OUTSIZE_32BITS @@ -671,7 +671,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx) */ __STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_CORDIC_DMA_REG_DATA_OUT) { diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_crs.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_crs.c index 12871e19a4f..4939d60f839 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_crs.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_crs.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_crs.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_crs.h index 35ad705d77b..caaf4b5e48a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_crs.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_crs.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -94,7 +94,7 @@ extern "C" { /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source * @{ */ -#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ +#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */ #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.c index 698a693c2ec..c7a8a92a559 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.c @@ -283,7 +283,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure * @retval An ErrorStatus enumeration value: diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.h index cfa805551f0..1eaed748f6d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.h @@ -274,21 +274,21 @@ typedef struct #define LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger */ #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM6 TRGO. */ #define LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM3 TRGO. */ -#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG6 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external peripheral: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ -#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external peripheral: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */ -#define LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external peripheral: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ +#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external peripheral: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */ +#define LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ /** * @} */ @@ -373,7 +373,7 @@ typedef struct * @{ */ #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */ -#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ +#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ /** * @} */ @@ -498,7 +498,7 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval 1...2 */ @@ -518,7 +518,7 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. */ #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ @@ -656,7 +656,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param ChannelMode This parameter can be one of the following values: * @arg @ref LL_DAC_MODE_NORMAL_OPERATION @@ -680,7 +680,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_MODE_NORMAL_OPERATION @@ -704,7 +704,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F * @retval None @@ -727,7 +727,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ @@ -753,7 +753,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -776,12 +776,12 @@ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5) * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5) * - * (1) On this STM32 serie, parameter only available on DAC3. - * (2) On this STM32 serie, parameter only available on DAC1/2/4. - * (3) On this STM32 serie, parameter only available on DAC1&4. - * (4) On this STM32 serie, parameter only available on DAC2. + * (1) On this STM32 series, parameter only available on DAC3. + * (2) On this STM32 series, parameter only available on DAC1/2/4. + * (3) On this STM32 series, parameter only available on DAC1&4. + * (4) On this STM32 series, parameter only available on DAC2. * Refer to device datasheet for DACx instances availability. - * (5) On this STM32 serie, parameter not available on all devices. + * (5) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) * @retval None */ @@ -805,7 +805,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -828,12 +828,12 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5) * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5) * - * (1) On this STM32 serie, parameter only available on DAC3. - * (2) On this STM32 serie, parameter only available on DAC1/2/4. - * (3) On this STM32 serie, parameter only available on DAC1&4. - * (4) On this STM32 serie, parameter only available on DAC2. + * (1) On this STM32 series, parameter only available on DAC3. + * (2) On this STM32 series, parameter only available on DAC1/2/4. + * (3) On this STM32 series, parameter only available on DAC1&4. + * (4) On this STM32 series, parameter only available on DAC2. * Refer to device datasheet for DACx instances availability. - * (5) On this STM32 serie, parameter not available on all devices. + * (5) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) @@ -853,7 +853,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param WaveAutoGeneration This parameter can be one of the following values: * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE @@ -879,7 +879,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE @@ -909,7 +909,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param NoiseLFSRMask This parameter can be one of the following values: * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 @@ -943,7 +943,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 @@ -981,7 +981,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param TriangleAmplitude This parameter can be one of the following values: * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 @@ -1016,7 +1016,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 @@ -1053,7 +1053,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Polarity This parameter can be one of the following values: * @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT @@ -1078,7 +1078,7 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT @@ -1105,7 +1105,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint3 * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param ResetData This parameter is the sawtooth reset value. * Range is from 0 to DAC full range 4095 (0xFFF) @@ -1129,7 +1129,7 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value is the sawtooth reset value. * Range is from 0 to DAC full range 4095 (0xFFF) @@ -1155,7 +1155,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param StepData This parameter is the sawtooth step value. * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa @@ -1181,7 +1181,7 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value is the sawtooth step value. * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa @@ -1209,7 +1209,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(DAC_TypeDef *DACx, uint3 * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -1232,12 +1232,12 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(DAC_TypeDef *DACx, uint3 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5) * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5) * - * (1) On this STM32 serie, parameter only available on DAC3. - * (2) On this STM32 serie, parameter only available on DAC1/2/4. - * (3) On this STM32 serie, parameter only available on DAC1&4. - * (4) On this STM32 serie, parameter only available on DAC2. + * (1) On this STM32 series, parameter only available on DAC3. + * (2) On this STM32 series, parameter only available on DAC1/2/4. + * (3) On this STM32 series, parameter only available on DAC1&4. + * (4) On this STM32 series, parameter only available on DAC2. * Refer to device datasheet for DACx instances availability. - * (5) On this STM32 serie, parameter not available on all devices. + * (5) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) * @retval None */ @@ -1258,7 +1258,7 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -1281,12 +1281,12 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5) * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5) * - * (1) On this STM32 serie, parameter only available on DAC3. - * (2) On this STM32 serie, parameter only available on DAC1/2/4. - * (3) On this STM32 serie, parameter only available on DAC1&4. - * (4) On this STM32 serie, parameter only available on DAC2. + * (1) On this STM32 series, parameter only available on DAC3. + * (2) On this STM32 series, parameter only available on DAC1/2/4. + * (3) On this STM32 series, parameter only available on DAC1&4. + * (4) On this STM32 series, parameter only available on DAC2. * Refer to device datasheet for DACx instances availability. - * (5) On this STM32 serie, parameter not available on all devices. + * (5) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) @@ -1312,7 +1312,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(DAC_TypeDef *D * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param TriggerSource This parameter can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -1332,10 +1332,10 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(DAC_TypeDef *D * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3) * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3) * - * (1) On this STM32 serie, parameter only available on DAC3. - * (2) On this STM32 serie, parameter only available on DAC1/2/4. + * (1) On this STM32 series, parameter only available on DAC3. + * (2) On this STM32 series, parameter only available on DAC1/2/4. * Refer to device datasheet for DACx instances availability. - * (3) On this STM32 serie, parameter not available on all devices. + * (3) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) * @retval None */ @@ -1356,7 +1356,7 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_TRIG_SOFTWARE @@ -1376,10 +1376,10 @@ __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3) * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3) * - * (1) On this STM32 serie, parameter only available on DAC3. - * (2) On this STM32 serie, parameter only available on DAC1/2/4. + * (1) On this STM32 series, parameter only available on DAC3. + * (2) On this STM32 series, parameter only available on DAC1/2/4. * Refer to device datasheet for DACx instances availability. - * (3) On this STM32 serie, parameter not available on all devices. + * (3) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) */ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) @@ -1402,7 +1402,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(DAC_TypeDef *DA * - @ref LL_DAC_SetOutputBuffer() * - @ref LL_DAC_SetOutputMode() * - @ref LL_DAC_SetOutputConnection() - * @note On this STM32 serie, output connection depends on output mode + * @note On this STM32 series, output connection depends on output mode * (normal or sample and hold) and output buffer state. * - if output connection is set to internal path and output buffer * is enabled (whatever output mode): @@ -1425,7 +1425,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(DAC_TypeDef *DA * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param OutputMode This parameter can be one of the following values: * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL @@ -1462,7 +1462,7 @@ __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param OutputMode This parameter can be one of the following values: * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL @@ -1485,7 +1485,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL @@ -1500,7 +1500,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Ch /** * @brief Set the output buffer for the selected DAC channel. - * @note On this STM32 serie, when buffer is enabled, its offset can be + * @note On this STM32 series, when buffer is enabled, its offset can be * trimmed: factory calibration default values can be * replaced by user trimming values, using function * @ref LL_DAC_SetTrimmingValue(). @@ -1511,7 +1511,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Ch * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param OutputBuffer This parameter can be one of the following values: * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE @@ -1534,7 +1534,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE @@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_ /** * @brief Set the output connection for the selected DAC channel. - * @note On this STM32 serie, output connection depends on output mode (normal or + * @note On this STM32 series, output connection depends on output mode (normal or * sample and hold) and output buffer state. * - if output connection is set to internal path and output buffer * is enabled (whatever output mode): @@ -1566,7 +1566,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param OutputConnection This parameter can be one of the following values: * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO @@ -1582,7 +1582,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ /** * @brief Get the output connection for the selected DAC channel. - * @note On this STM32 serie, output connection depends on output mode (normal or + * @note On this STM32 series, output connection depends on output mode (normal or * sample and hold) and output buffer state. * - if output connection is set to internal path and output buffer * is enabled (whatever output mode): @@ -1599,7 +1599,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO @@ -1626,7 +1626,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF * @retval None @@ -1650,7 +1650,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ @@ -1671,7 +1671,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, ui * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF * @retval None @@ -1693,7 +1693,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ @@ -1714,7 +1714,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF * @retval None @@ -1736,7 +1736,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3 * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ @@ -1749,7 +1749,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, u /** * @brief Set the signed format for the selected DAC channel. - * @note On this STM32 serie, signed format can be used to inject + * @note On this STM32 series, signed format can be used to inject * Q1.15, Q1.11, Q1.7 signed format data to DAC. * Ex when using 12bits data format (Q1.11 is used): * 0x800 will output 0v level @@ -1763,7 +1763,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, u * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param SignedFormat This parameter can be one of the following values: * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE @@ -1786,7 +1786,7 @@ __STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Chan * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE @@ -1818,7 +1818,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -1839,7 +1839,7 @@ __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -1859,7 +1859,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ @@ -1879,7 +1879,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -1898,7 +1898,7 @@ __STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -1918,7 +1918,7 @@ __STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ @@ -1955,7 +1955,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, ui * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Register This parameter can be one of the following values: * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED @@ -1990,7 +1990,7 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -2009,7 +2009,7 @@ __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -2029,7 +2029,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ @@ -2050,7 +2050,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ @@ -2078,7 +2078,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsReady(DAC_TypeDef *DACx, uint32_t DAC_Channel) * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -2097,7 +2097,7 @@ __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channe * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -2117,7 +2117,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval State of bit (1 or 0). */ @@ -2151,7 +2151,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -2183,7 +2183,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval None */ @@ -2204,7 +2204,7 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion2(DAC_TypeDef *DACx, uint32_t DAC_Ch * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None @@ -2229,7 +2229,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None @@ -2254,7 +2254,7 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @param Data Value between Min_Data=0x00 and Max_Data=0xFF * @retval None @@ -2343,7 +2343,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 (1) * - * (1) On this STM32 serie, parameter not available on all instances. + * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dma.h index c294bf9b53d..0a4e3b3ec51 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dma.h @@ -1030,7 +1030,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe /** * @brief Configure the Source and Destination addresses. * @note This API must not be called when the DMA channel is enabled. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n * CMAR MA LL_DMA_ConfigAddresses * @param DMAx DMAx Instance diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dmamux.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dmamux.h index 9cc45484676..52ba8350fca 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dmamux.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dmamux.h @@ -246,10 +246,10 @@ extern "C" { #define LL_DMAMUX_REQ_SPI4_TX 0x0000006BU /*!< DMAMUX SPI4 TX request */ #define LL_DMAMUX_REQ_SAI1_A 0x0000006CU /*!< DMAMUX SAI1 A request */ #define LL_DMAMUX_REQ_SAI1_B 0x0000006DU /*!< DMAMUX SAI1 B request */ -#define LL_DMAMUX_REQ_FMAC_WRITE 0x0000006EU /*!< DMAMUX FMAC WRITE request */ -#define LL_DMAMUX_REQ_FMAC_READ 0x0000006FU /*!< DMAMUX FMAC READ request */ -#define LL_DMAMUX_REQ_CORDIC_WRITE 0x00000070U /*!< DMAMUX CORDIC WRITE request*/ -#define LL_DMAMUX_REQ_CORDIC_READ 0x00000071U /*!< DMAMUX CORDIC READ request */ +#define LL_DMAMUX_REQ_FMAC_READ 0x0000006EU /*!< DMAMUX FMAC READ request */ +#define LL_DMAMUX_REQ_FMAC_WRITE 0x0000006FU /*!< DMAMUX FMAC WRITE request */ +#define LL_DMAMUX_REQ_CORDIC_READ 0x00000070U /*!< DMAMUX CORDIC READ request */ +#define LL_DMAMUX_REQ_CORDIC_WRITE 0x00000071U /*!< DMAMUX CORDIC WRITE request*/ #define LL_DMAMUX_REQ_UCPD1_RX 0x00000072U /*!< DMAMUX USBPD1_RX request */ #define LL_DMAMUX_REQ_UCPD1_TX 0x00000073U /*!< DMAMUX USBPD1_TX request */ @@ -314,7 +314,7 @@ extern "C" { #define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */ #define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */ #define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */ -#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Ouput */ +#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */ /** * @} */ @@ -364,7 +364,7 @@ extern "C" { #define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */ #define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */ #define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */ -#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Ouput */ +#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_exti.c index a777e655534..5b729b86629 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_exti.c @@ -117,7 +117,7 @@ uint32_t LL_EXTI_DeInit(void) * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. * @retval An ErrorStatus enumeration value: * - 0x00: EXTI registers are initialized - * - any other calue : wrong configuration + * - any other value : wrong configuration */ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) { diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_exti.h index 4a9b27d5055..cad75349a7c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_exti.h @@ -1173,7 +1173,7 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) /** * @brief Generate a software Interrupt Event for Lines in range 32 to 63 - * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 * resulting in an interrupt request generation. * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.c index 2ad67873f4d..7491be4533b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32g4xx_ll_fmac.c * @author MCD Application Team - * @brief FMAC LL module driver. + * @brief Header for stm32g4xx_ll_fmac.c module ****************************************************************************** * @attention * @@ -37,41 +37,13 @@ * @{ */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup FMAC_LL_Private_Macros - * @{ - */ - -/** @brief Check if the watermark value is a valid one. - * @param __VALUE__ Watermak value. - * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid) - */ -#define IS_LL_FMAC_WM(__VALUE__) (((__VALUE__) == LL_FMAC_WM_0_THRESHOLD_1) \ - || ((__VALUE__) == LL_FMAC_WM_1_THRESHOLD_2) \ - || ((__VALUE__) == LL_FMAC_WM_2_THRESHOLD_4) \ - || ((__VALUE__) == LL_FMAC_WM_3_THRESHOLD_8)) - -/** @brief Check if the function ID is a valid one. - * @param __VALUE__ Function ID. - * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid) - */ -#define IS_LL_FMAC_FUNC(__VALUE__) (((__VALUE__) == LL_FMAC_FUNC_LOAD_X1) \ - || ((__VALUE__) == LL_FMAC_FUNC_LOAD_X2) \ - || ((__VALUE__) == LL_FMAC_FUNC_LOAD_Y) \ - || ((__VALUE__) == LL_FMAC_FUNC_CONVO_FIR) \ - || ((__VALUE__) == LL_FMAC_FUNC_IIR_DIRECT_FORM_1)) - - -/** - * @} - */ - +/* Private variables ---------------------------------------------------------*/ +/* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ /** @addtogroup FMAC_LL_Exported_Functions * @{ */ @@ -83,7 +55,7 @@ /** * @brief Initialize FMAC peripheral registers to their default reset values. * @param FMACx FMAC Instance - * @retval An ErrorStatus enumeration value: + * @retval ErrorStatus enumeration value: * - SUCCESS: FMAC registers are initialized * - ERROR: FMAC registers are not initialized */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.h index b3f3371a23a..5d860c8fdb6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.h @@ -38,20 +38,6 @@ extern "C" { * @{ */ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup FMAC_LL_Private_Macros FMAC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -63,11 +49,11 @@ extern "C" { * @brief Flag defines which can be used with LL_FMAC_ReadReg function * @{ */ -#define LL_FMAC_SR_SAT FMAC_SR_SAT -#define LL_FMAC_SR_UNFL FMAC_SR_UNFL -#define LL_FMAC_SR_OVFL FMAC_SR_OVFL -#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL -#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY +#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */ +#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ +#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ +#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ +#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */ /** * @} */ @@ -76,11 +62,11 @@ extern "C" { * @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions * @{ */ -#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN -#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN -#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN -#define LL_FMAC_CR_WIEN FMAC_CR_WIEN -#define LL_FMAC_CR_RIEN FMAC_CR_RIEN +#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */ +#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ +#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ +#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ +#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */ /** * @} */ @@ -89,10 +75,10 @@ extern "C" { * @brief Watermark defines that can be used for buffer full (input) or buffer empty (output) * @{ */ -#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000UL /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */ -#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000UL /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */ -#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000UL /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */ -#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000UL /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */ +#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */ +#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */ +#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */ +#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */ /** * @} */ @@ -100,11 +86,20 @@ extern "C" { /** @defgroup FMAC_LL_EC_FUNC FMAC functions * @{ */ -#define LL_FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */ -#define LL_FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */ -#define LL_FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */ -#define LL_FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */ -#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */ +#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ +/** + * @} + */ + +/** @defgroup FMAC_LL_EC_PROCESSING FMAC processing + * @{ + */ +#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */ +#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */ /** * @} */ @@ -113,7 +108,8 @@ extern "C" { * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros * @{ */ @@ -177,7 +173,7 @@ __STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Wa * @brief Return X1 full watermark. * @rmtoll X1BUFCFG FULL_WM LL_FMAC_GetX1FullWatermark * @param FMACx FMAC instance - * @retval Returned value can be one of the following values: + * @retval uint32_t Returned value can be one of the following values: * @arg @ref LL_FMAC_WM_0_THRESHOLD_1 * @arg @ref LL_FMAC_WM_1_THRESHOLD_2 * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 @@ -192,7 +188,8 @@ __STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx) * @brief Configure X1 buffer size. * @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_SetX1BufferSize * @param FMACx FMAC instance - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom"). + * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom"). + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize) @@ -204,7 +201,7 @@ __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @brief Return X1 buffer size. * @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize * @param FMACx FMAC instance - * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom"). + * @retval uint8_t Number of 16-bit words allocated to the input buffer (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx) { @@ -215,7 +212,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx) * @brief Configure X1 base. * @rmtoll X1BUFCFG X1_BASE LL_FMAC_SetX1Base * @param FMACx FMAC instance - * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory. + * @param Base Base address of the input buffer (X1) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base) @@ -227,7 +225,7 @@ __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base) * @brief Return X1 base. * @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory. + * @retval uint8_t Base address of the input buffer (X1) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx) { @@ -238,7 +236,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx) * @brief Configure X2 buffer size. * @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_SetX2BufferSize * @param FMACx FMAC instance - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer. + * @param BufferSize Number of 16-bit words allocated to the coefficient buffer. + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize) @@ -250,7 +249,7 @@ __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @brief Return X2 buffer size. * @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize * @param FMACx FMAC instance - * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer. + * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer (value between Min_Data=0x01 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx) { @@ -261,7 +260,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx) * @brief Configure X2 base. * @rmtoll X2BUFCFG X2_BASE LL_FMAC_SetX2Base * @param FMACx FMAC instance - * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory. + * @param Base Base address of the coefficient buffer (X2) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base) @@ -273,7 +273,7 @@ __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base) * @brief Return X2 base. * @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory. + * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx) { @@ -300,7 +300,7 @@ __STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Wa * @brief Return Y empty watermark. * @rmtoll YBUFCFG EMPTY_WM LL_FMAC_GetYEmptyWatermark * @param FMACx FMAC instance - * @retval Returned value can be one of the following values: + * @retval uint32_t Returned value can be one of the following values: * @arg @ref LL_FMAC_WM_0_THRESHOLD_1 * @arg @ref LL_FMAC_WM_1_THRESHOLD_2 * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 @@ -315,7 +315,8 @@ __STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx) * @brief Configure Y buffer size. * @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_SetYBufferSize * @param FMACx FMAC instance - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom"). + * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom"). + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize) @@ -327,7 +328,7 @@ __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferS * @brief Return Y buffer size. * @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize * @param FMACx FMAC instance - * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom"). + * @retval uint8_t Number of 16-bit words allocated to the output buffer (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx) { @@ -338,7 +339,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx) * @brief Configure Y base. * @rmtoll YBUFCFG Y_BASE LL_FMAC_SetYBase * @param FMACx FMAC instance - * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory. + * @param Base Base address of the output buffer (Y) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base) @@ -350,7 +352,7 @@ __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base) * @brief Return Y base. * @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory. + * @retval uint8_t Base address of the output buffer (Y) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx) { @@ -383,7 +385,7 @@ __STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx) * @brief Check the state of FMAC processing. * @rmtoll PARAM START LL_FMAC_IsEnabledStart * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx) { @@ -411,7 +413,7 @@ __STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function) * @brief Return function. * @rmtoll PARAM FUNC LL_FMAC_GetFunction * @param FMACx FMAC instance - * @retval Returned value can be one of the following values: + * @retval uint32_t Returned value can be one of the following values: * @arg @ref LL_FMAC_FUNC_LOAD_X1 * @arg @ref LL_FMAC_FUNC_LOAD_X2 * @arg @ref LL_FMAC_FUNC_LOAD_Y @@ -427,7 +429,8 @@ __STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx) * @brief Configure input parameter R. * @rmtoll PARAM R LL_FMAC_SetParamR * @param FMACx FMAC instance - * @param Param 0x00 .. 0xFF: Parameter R (gain, etc.). + * @param Param Parameter R (gain, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param) @@ -439,7 +442,7 @@ __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param) * @brief Return input parameter R. * @rmtoll PARAM R LL_FMAC_GetParamR * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Parameter R (gain, etc.). + * @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx) { @@ -450,7 +453,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx) * @brief Configure input parameter Q. * @rmtoll PARAM Q LL_FMAC_SetParamQ * @param FMACx FMAC instance - * @param Param 0x00 .. 0xFF: Parameter Q (vector length, etc.). + * @param Param Parameter Q (vector length, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param) @@ -462,7 +466,7 @@ __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param) * @brief Return input parameter Q. * @rmtoll PARAM Q LL_FMAC_GetParamQ * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Parameter Q (vector length, etc.). + * @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx) { @@ -473,23 +477,24 @@ __STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx) * @brief Configure input parameter P. * @rmtoll PARAM P LL_FMAC_SetParamP * @param FMACx FMAC instance - * @param Param 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.). + * @param Param Parameter P (vector length, number of filter taps, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param) { - MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param) << FMAC_PARAM_P_Pos); + MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param)); } /** * @brief Return input parameter P. * @rmtoll PARAM P LL_FMAC_GetParamP * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.). + * @retval uint8_t Parameter P (vector length, number of filter taps, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx) { - return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P) >> FMAC_PARAM_P_Pos); + return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P)); } /** @@ -511,22 +516,11 @@ __STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx) SET_BIT(FMACx->CR, FMAC_CR_RESET); } -/** - * @brief Interrupt the FMAC reset. - * @rmtoll CR RESET LL_FMAC_DisableReset - * @param FMACx FMAC instance - * @retval None - */ -__STATIC_INLINE void LL_FMAC_DisableReset(FMAC_TypeDef *FMACx) -{ - CLEAR_BIT(FMACx->CR, FMAC_CR_RESET); -} - /** * @brief Check the state of the FMAC reset. * @rmtoll CR RESET LL_FMAC_IsEnabledReset * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx) { @@ -567,7 +561,7 @@ __STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx) * @brief Check Clipping State. * @rmtoll CR CLIPEN LL_FMAC_IsEnabledClipping * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx) { @@ -608,7 +602,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx) * @brief Check FMAC DMA write channel request state. * @rmtoll CR DMAWEN LL_FMAC_IsEnabledDMAReq_WRITE * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx) { @@ -641,7 +635,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx) * @brief Check FMAC DMA read channel request state. * @rmtoll CR DMAREN LL_FMAC_IsEnabledDMAReq_READ * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx) { @@ -682,7 +676,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx) * @brief Check FMAC saturation error interrupt state. * @rmtoll CR SATIEN LL_FMAC_IsEnabledIT_SAT * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx) { @@ -715,7 +709,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx) * @brief Check FMAC underflow error interrupt state. * @rmtoll CR UNFLIEN LL_FMAC_IsEnabledIT_UNFL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx) { @@ -748,7 +742,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx) * @brief Check FMAC overflow error interrupt state. * @rmtoll CR OVFLIEN LL_FMAC_IsEnabledIT_OVFL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx) { @@ -781,7 +775,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx) * @brief Check FMAC write interrupt state. * @rmtoll CR WIEN LL_FMAC_IsEnabledIT_WR * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx) { @@ -814,7 +808,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx) * @brief Check FMAC read interrupt state. * @rmtoll CR RIEN LL_FMAC_IsEnabledIT_RD * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx) { @@ -833,7 +827,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx) * @brief Check FMAC saturation error flag state. * @rmtoll SR SAT LL_FMAC_IsActiveFlag_SAT * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx) { @@ -844,7 +838,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx) * @brief Check FMAC underflow error flag state. * @rmtoll SR UNFL LL_FMAC_IsActiveFlag_UNFL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx) { @@ -855,7 +849,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx) * @brief Check FMAC overflow error flag state. * @rmtoll SR OVFL LL_FMAC_IsActiveFlag_OVFL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx) { @@ -866,7 +860,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx) * @brief Check FMAC X1 buffer full flag state. * @rmtoll SR X1FULL LL_FMAC_IsActiveFlag_X1FULL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx) { @@ -877,7 +871,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx) * @brief Check FMAC Y buffer empty flag state. * @rmtoll SR YEMPTY LL_FMAC_IsActiveFlag_YEMPTY * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx) { @@ -896,7 +890,8 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx) * @brief Write 16-bit input data for the FMAC processing. * @rmtoll WDATA WDATA LL_FMAC_WriteData * @param FMACx FMAC instance - * @param InData 0x0000 .. 0xFFFF: 16-bit value to be provided as input data for FMAC processing. + * @param InData 16-bit value to be provided as input data for FMAC processing. + * This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. * @retval None */ __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData) @@ -908,7 +903,7 @@ __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData) * @brief Return 16-bit output data of FMAC processing. * @rmtoll RDATA RDATA LL_FMAC_ReadData * @param FMACx FMAC instance - * @retval 0x0000 .. 0xFFFF: 16-bit output data of FMAC processing. + * @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF). */ __STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx) { @@ -934,8 +929,10 @@ __STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx) * @arg @ref LL_FMAC_WM_1_THRESHOLD_2 * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 * @arg @ref LL_FMAC_WM_3_THRESHOLD_8 - * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory. - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom"). + * @param Base Base address of the input buffer (X1) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom"). + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize) @@ -949,8 +946,10 @@ __STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, u * @rmtoll X2BUFCFG X2_BASE LL_FMAC_ConfigX2\n * X2BUFCFG X2_BUF_SIZE LL_FMAC_ConfigX2 * @param FMACx FMAC instance - * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory. - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer. + * @param Base Base address of the coefficient buffer (X2) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param BufferSize Number of 16-bit words allocated to the coefficient buffer. + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize) @@ -970,8 +969,10 @@ __STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t * @arg @ref LL_FMAC_WM_1_THRESHOLD_2 * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 * @arg @ref LL_FMAC_WM_3_THRESHOLD_8 - * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory. - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom"). + * @param Base Base address of the output buffer (Y) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom"). + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize) @@ -988,16 +989,21 @@ __STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, ui * PARAM Q LL_FMAC_ConfigFunc\n * PARAM R LL_FMAC_ConfigFunc * @param FMACx FMAC instance - * @param Start 0x00 .. 0x01: Enable or disable FMAC processing. + * @param Start This parameter can be one of the following values: + * @arg @ref LL_FMAC_PROCESSING_STOP + * @arg @ref LL_FMAC_PROCESSING_START * @param Function This parameter can be one of the following values: * @arg @ref LL_FMAC_FUNC_LOAD_X1 * @arg @ref LL_FMAC_FUNC_LOAD_X2 * @arg @ref LL_FMAC_FUNC_LOAD_Y * @arg @ref LL_FMAC_FUNC_CONVO_FIR * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1 - * @param ParamP 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.). - * @param ParamQ 0x00 .. 0xFF: Parameter Q (vector length, etc.). - * @param ParamR 0x00 .. 0xFF: Parameter R (gain, etc.). + * @param ParamP Parameter P (vector length, number of filter taps, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param ParamQ Parameter Q (vector length, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param ParamR Parameter R (gain, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP, diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_gpio.c index 2d46dcc4288..229008271cf 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_gpio.c @@ -189,9 +189,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru if (currentpin != 0x00u) { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check Speed mode parameters */ @@ -199,6 +196,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); } /* Pull-up Pull down resistor configuration*/ @@ -219,19 +222,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); } pinpos++; } - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } return (SUCCESS); } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_gpio.h index e241e32edb1..a13ff6c99ef 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_gpio.h @@ -952,7 +952,8 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas */ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_hrtim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_hrtim.h index 9865f1e97ff..2b974b2f19d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_hrtim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_hrtim.h @@ -893,7 +893,7 @@ static const uint32_t REG_MASK_TAB_CPT[] = * @{ * @brief Constants defining the DLL calibration mode. */ -#define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT 0x00000000U /*!sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer); } @@ -2367,7 +2361,7 @@ __STATIC_INLINE void LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); CLEAR_BIT(HRTIMx->sCommonRegs.CR2, (HRTIM_CR2_SWPA << iTimer)); } @@ -2397,7 +2391,7 @@ __STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU); + uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU); return (READ_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer) >> ((HRTIM_CR2_SWPA_Pos + iTimer))); } @@ -2835,9 +2829,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src) { - register __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + + __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + REG_OFFSET_TAB_ADCUR[ADCTrig])); - register __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + + __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCER[ADCTrig])); MODIFY_REG(*padcur, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig])); MODIFY_REG(*padcer, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig])); @@ -2882,7 +2876,7 @@ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCT */ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update) { - register __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + + __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + REG_OFFSET_TAB_ADCUR[ADCTrig])); MODIFY_REG(*preg, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig])); } @@ -2922,7 +2916,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t A */ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { - register const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + + const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) + REG_OFFSET_TAB_ADCUR[ADCTrig])); return (READ_BIT(*preg, (REG_MASK_TAB_ADCUR[ADCTrig])) >> REG_SHIFT_TAB_ADCUR[ADCTrig]); } @@ -3221,7 +3215,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { - register __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + + __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCER[ADCTrig])); MODIFY_REG(*preg, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig])); } @@ -3521,7 +3515,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT */ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { - register const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + + const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCER[ADCTrig])); return (READ_BIT(*preg, (REG_MASK_TAB_ADCER[ADCTrig])) >> REG_SHIFT_TAB_ADCER[ADCTrig]); @@ -3751,8 +3745,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler); } @@ -3781,8 +3775,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC)); } @@ -3809,8 +3803,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode); } @@ -3836,8 +3830,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT))); } @@ -3861,8 +3855,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_HALF); } @@ -3883,8 +3877,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_HALF); CLEAR_BIT(*pReg, HRTIM_MCR_INTLVD << REG_SHIFT_TAB_INTLVD[iTimer]); } @@ -3906,8 +3900,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL); } @@ -3929,8 +3923,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_RSYNCU); /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */ @@ -3953,8 +3947,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_RSYNCU); @@ -3978,8 +3972,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_RSYNCU) == (HRTIM_TIMCR_RSYNCU)) ? 1UL : 0UL); @@ -4011,8 +4005,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(HRTIM_TypeDef *HRTIM */ __STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, REG_MASK_TAB_INTLVD[iTimer], ((Mode & HRTIM_MCR_HALF) | ((Mode & HRTIM_MCR_INTLVD) << REG_SHIFT_TAB_INTLVD[iTimer]))); @@ -4046,8 +4040,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t Mode = READ_BIT(*pReg, (REG_MASK_TAB_INTLVD[iTimer])); return ((Mode & HRTIM_MCR_HALF) | ((Mode >> REG_SHIFT_TAB_INTLVD[iTimer]) & HRTIM_MCR_INTLVD)); @@ -4070,8 +4064,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); } @@ -4092,8 +4086,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); } @@ -4114,8 +4108,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL); } @@ -4137,8 +4131,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx */ __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM); } @@ -4159,8 +4153,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM); } @@ -4181,8 +4175,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL); } @@ -4209,8 +4203,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx */ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig); } @@ -4235,8 +4229,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC)); } @@ -4260,8 +4254,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MCR_PREEN); } @@ -4282,8 +4276,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MCR_PREEN); } @@ -4304,8 +4298,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL); } @@ -4351,8 +4345,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]); } @@ -4395,8 +4389,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]); } @@ -4434,8 +4428,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer])); } @@ -4472,8 +4466,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]); } @@ -4492,8 +4486,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -4513,8 +4507,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -4534,8 +4528,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); } @@ -4566,10 +4560,10 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIM __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); - register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); + uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } @@ -4596,10 +4590,10 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + REG_OFFSET_TAB_TIMER[iTimer])); - register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); + uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); } @@ -4627,8 +4621,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -4650,8 +4644,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -4674,8 +4668,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -4697,8 +4691,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -4721,8 +4715,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -4744,8 +4738,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -4770,8 +4764,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -4795,8 +4789,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -4821,8 +4815,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -4846,8 +4840,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -4872,8 +4866,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -4897,8 +4891,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -4923,8 +4917,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -4948,8 +4942,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -5040,8 +5034,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -5125,8 +5119,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -5146,8 +5140,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -5169,8 +5163,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos); } @@ -5190,8 +5184,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef *HRTIMx */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -5213,8 +5207,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos); } @@ -5311,8 +5305,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(HRTIM_TypeDef *HRTIMx __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit, uint64_t CaptureTrig) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); uint32_t cfg1 = (uint32_t)(CaptureTrig & 0x0000000000000FFFU); @@ -5414,12 +5408,12 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + (uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U))); uint64_t cfg; - register uint32_t CaptureTrig = READ_REG(*pReg); + uint32_t CaptureTrig = READ_REG(*pReg); cfg = (uint64_t)(uint32_t)(((CaptureTrig & 0xFFFFF000U) & (uint32_t)REG_MASK_TAB_CPT[iTimer]) | (((CaptureTrig & 0xFFFFF000U) & (uint32_t)~REG_MASK_TAB_CPT[iTimer]) >> (REG_SHIFT_TAB_CPT[iTimer]))); @@ -5441,8 +5435,8 @@ __STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -5462,8 +5456,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -5483,8 +5477,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); @@ -5529,8 +5523,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -5571,8 +5565,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -5593,8 +5587,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -5615,8 +5609,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -5636,8 +5630,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); } @@ -5658,8 +5652,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_BIAR); } @@ -5680,8 +5674,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_BIAR); } @@ -5701,8 +5695,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_BIAR) == (HRTIM_OUTR_BIAR)) ? 1UL : 0UL); @@ -5735,8 +5729,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -5768,8 +5762,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -5801,8 +5795,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); @@ -5824,8 +5818,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -5856,7 +5850,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption) { - register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); + uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer); } @@ -5884,7 +5878,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); + uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer); } @@ -5984,8 +5978,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t 0x1CU /* BDFUPR ; offset = 0x074 */ }; - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + REG_OFFSET_TAB_BDTUPR[iTimer])); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + REG_OFFSET_TAB_BDTUPR[iTimer])); WRITE_REG(*pReg, Registers); } @@ -6007,8 +6001,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -6030,8 +6024,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HR */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -6130,9 +6124,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIM */ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6228,9 +6222,9 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6275,9 +6269,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t LatchStatus) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6319,9 +6313,9 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6347,8 +6341,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_TRGHLF, Mode); } @@ -6373,8 +6367,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(* pReg, HRTIM_TIMCR2_TRGHLF)); } @@ -6400,8 +6394,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx */ __STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP1, Mode); } @@ -6426,8 +6420,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP1)); } @@ -6453,8 +6447,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP3, (Mode)); } @@ -6479,8 +6473,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP3)); } @@ -6507,8 +6501,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_ROM, (Mode << HRTIM_TIMCR2_ROM_Pos)); } @@ -6531,8 +6525,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_ROM) >> HRTIM_TIMCR2_ROM_Pos); } @@ -6558,8 +6552,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_FEROM, (Mode << HRTIM_TIMCR2_FEROM_Pos)); } @@ -6582,8 +6576,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIM */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_FEROM) >> HRTIM_TIMCR2_FEROM_Pos); } @@ -6609,8 +6603,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(HRTIM_TypeDef *H */ __STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_BMROM, (Mode << HRTIM_TIMCR2_BMROM_Pos)); } @@ -6633,8 +6627,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_BMROM) >> HRTIM_TIMCR2_BMROM_Pos); } @@ -6660,8 +6654,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_ADROM, (Mode << HRTIM_TIMCR2_ADROM_Pos)); } @@ -6684,8 +6678,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_ADROM) >> HRTIM_TIMCR2_ADROM_Pos); } @@ -6693,7 +6687,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef *HRTIMx, /** * @brief Select the ADC roll-over mode. * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()). - * @note Only concerns concerns the Roll-over event which sets and/or resets the ouputs, + * @note Only concerns concerns the Roll-over event which sets and/or resets the outputs, * as per HRTIM_SETxyR and HRTIM_RSTxyR settings (see function @ref LL_HRTIM_OUT_SetOutputSetSrc() * and function @ref LL_HRTIM_OUT_SetOutputResetSrc() respectively). * @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_SetOutputRollOverMode @@ -6713,8 +6707,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_OUTROM, (Mode << HRTIM_TIMCR2_OUTROM_Pos)); } @@ -6737,8 +6731,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_OUTROM) >> HRTIM_TIMCR2_OUTROM_Pos); } @@ -6767,8 +6761,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(HRTIM_TypeDef *HRTIM */ __STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_UDM, Mode); } @@ -6791,8 +6785,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_UDM)); } @@ -6817,8 +6811,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDR, Mode); } @@ -6840,8 +6834,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDR)); } @@ -6864,8 +6858,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(HRTIM_TypeDef *HRTI */ __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDS, Mode); } @@ -6887,8 +6881,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDS)); } @@ -6909,8 +6903,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(HRTIM_TypeDef *HRTIM */ __STATIC_INLINE void LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(* pReg, HRTIM_TIMCR2_DCDE); } @@ -6930,8 +6924,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(* pReg, HRTIM_TIMCR2_DCDE); } @@ -6951,8 +6945,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(* pReg, HRTIM_TIMCR2_DCDE) == (HRTIM_TIMCR2_DCDE)) ? 1UL : 0UL); @@ -6974,16 +6968,16 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(HRTIM_TypeDef *HRT * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=63 * @retval None */ __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter, uint32_t Threshold) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVACNT << EventCounter), Threshold << (HRTIM_EEFR3_EEVACNT_Pos + EventCounter)); } @@ -7001,15 +6995,15 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @retval Threshold Value between Min_Data=0 and Max_Data=63 */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACNT) << EventCounter)) >> ((HRTIM_EEFR3_EEVACNT_Pos + EventCounter))) ; } @@ -7030,8 +7024,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef *HR * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @param Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_1 * @arg @ref LL_HRTIM_EVENT_2 @@ -7048,9 +7042,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef *HR __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter, uint32_t Event) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); - register uint32_t iEvent = (uint32_t)(POSITION_VAL(Event)); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iEvent = (uint32_t)(POSITION_VAL(Event)); /* register SEL value is 0 if LL_HRTIM_EVENT_1, 1 if LL_HRTIM_EVENT_1, etc and 9 if LL_HRTIM_EVENT_10 */ @@ -7071,8 +7065,8 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, u * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @retval Event This parameter can be one of the following values: * @arg @ref LL_HRTIM_EVENT_1 * @arg @ref LL_HRTIM_EVENT_2 @@ -7088,10 +7082,10 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, u __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); - register uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVASEL) << (EventCounter))) >> ((HRTIM_EEFR3_EEVASEL_Pos + EventCounter)); + uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVASEL) << (EventCounter))) >> ((HRTIM_EEFR3_EEVASEL_Pos + EventCounter)); /* returned value is 0 if SEL is LL_HRTIM_EVENT_1, 1 if SEL is LL_HRTIM_EVENT_1, etc and 9 if SEL is LL_HRTIM_EVENT_10 */ @@ -7111,18 +7105,18 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(HRTIM_TypeDef *HRTIM * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @param Mode This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTERRSTMODE_UNCONDITIONAL - * @arg @ref LL_HRTIM_EVENT_COUNTERRSTMODE_CONDITIONAL + * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL + * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL * @retval None */ __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter, uint32_t Mode) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVARSTM << (EventCounter)), Mode << (EventCounter)); } @@ -7140,17 +7134,17 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @retval Mode This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTERRSTMODE_UNCONDITIONAL - * @arg @ref LL_HRTIM_EVENT_COUNTERRSTMODE_CONDITIONAL + * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL + * @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVARSTM) << (EventCounter))) >> (EventCounter)) ; } @@ -7168,14 +7162,14 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(HRTIM_TypeDef *HR * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @retval None */ __STATIC_INLINE void LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACRES) << EventCounter); } @@ -7193,14 +7187,14 @@ __STATIC_INLINE void LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @retval None */ __STATIC_INLINE void LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter); } @@ -7218,14 +7212,14 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @retval None */ __STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); CLEAR_BIT(*pReg, (HRTIM_EEFR3_EEVACE << EventCounter)); } @@ -7244,17 +7238,17 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_TIMER_E * @arg @ref LL_HRTIM_TIMER_F * @param EventCounter This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EVENT_COUNTER_A - * @arg @ref LL_HRTIM_EVENT_COUNTER_B + * @arg @ref LL_HRTIM_EE_COUNTER_A + * @arg @ref LL_HRTIM_EE_COUNTER_B * @retval State of EEVxCE bit in RTIM_EEFxR3 register (1 or 0). */ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3))); - uint32_t temp; /* MISRAC-2012 compliancy */ + uint32_t temp; /* MISRAC-2012 compliance */ temp = READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter); return ((temp == ((uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter)) ? 1UL : 0UL); @@ -7289,8 +7283,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(HRTIM_TypeDef *HRTIM */ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -7319,8 +7313,8 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u */ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -7348,8 +7342,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -7370,8 +7364,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -7391,8 +7385,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -7415,8 +7409,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -7438,8 +7432,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -7460,8 +7454,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -7481,8 +7475,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -7505,8 +7499,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -7528,8 +7522,8 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -7549,8 +7543,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -7570,8 +7564,8 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -7591,8 +7585,8 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -7612,8 +7606,8 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -7649,8 +7643,8 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -7690,8 +7684,8 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, */ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -7727,8 +7721,8 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -7760,8 +7754,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -7789,8 +7783,8 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -7829,8 +7823,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -7866,8 +7860,8 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -7975,48 +7969,48 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMFCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMFCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMFCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 @@ -8038,13 +8032,13 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10 * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE - * (source = TIMy and destination = TIMx, Compare Unit = CMPz). + * (source = TIMy and destination = TIMx, Compare Unit = CMPz). * @retval None */ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -8144,48 +8138,48 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMFCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMFCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMFCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 @@ -8211,8 +8205,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -8312,48 +8306,48 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMFCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMFCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMFCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 @@ -8380,8 +8374,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -8481,48 +8475,48 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMFCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMFCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMFCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMFCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 + * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 @@ -8544,12 +8538,12 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE - * (source = TIMy and destination = TIMx, Compare Unit = CMPz). + * (source = TIMy and destination = TIMx, Compare Unit = CMPz). */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -8593,8 +8587,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); @@ -8625,8 +8619,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, */ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8655,8 +8649,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8687,8 +8681,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); } @@ -8717,8 +8711,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8750,8 +8744,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8780,8 +8774,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8815,8 +8809,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8847,8 +8841,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8879,8 +8873,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8909,8 +8903,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -8941,8 +8935,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -8971,8 +8965,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -9002,8 +8996,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); @@ -9042,8 +9036,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */ }; - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -9072,8 +9066,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) { - register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + + uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); @@ -9153,8 +9147,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t O */ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); @@ -9193,8 +9187,8 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u */ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9231,8 +9225,8 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -9270,8 +9264,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Even */ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9306,8 +9300,8 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -9346,8 +9340,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9384,8 +9378,8 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -9417,8 +9411,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9448,8 +9442,8 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -9489,7 +9483,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -9528,7 +9522,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event) { - register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6)); + uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6)); return (READ_BIT(HRTIMx->sCommonRegs.EECR3, (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -9603,9 +9597,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); - register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); uint64_t cfg; uint64_t mask; @@ -9646,9 +9640,9 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, */ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); - register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); uint64_t cfg = ((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */ (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */ @@ -9682,9 +9676,9 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); - register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); uint64_t Src0; uint32_t Src1; @@ -9727,9 +9721,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fau */ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); - register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); uint64_t cfg = (uint64_t)((uint64_t)Polarity & (uint64_t)(HRTIM_FLTINR1_FLT1P)) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */ uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1P) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */ @@ -9761,9 +9755,9 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); - register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); uint32_t temp1, temp2; /* temp variables used for MISRA-C */ uint64_t cfg; @@ -9816,9 +9810,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); - register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); uint64_t flt = (uint64_t)((uint64_t)Filter & (uint64_t)HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for filter bits */ uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */ @@ -9863,9 +9857,9 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); - register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); + __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); uint32_t temp1, temp2; /* temp variables used for MISRA-C */ uint64_t flt; temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT6F)); @@ -9930,8 +9924,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -9956,8 +9950,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) */ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -9982,8 +9976,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) */ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); @@ -10009,8 +10003,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + REG_OFFSET_TAB_FLTINR[iFault])); return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == (HRTIM_FLTINR1_FLT1E)) ? 1UL : 0UL); @@ -10036,8 +10030,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]); } @@ -10062,8 +10056,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR3_FLT1BLKE << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -10088,10 +10082,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); - uint32_t temp; /* MISRAC-2012 compliancy */ + uint32_t temp; /* MISRAC-2012 compliance */ temp = READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]; return ((temp == (HRTIM_FLTINR3_FLT1BLKE)) ? 1UL : 0UL); @@ -10124,8 +10118,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(HRTIM_TypeDef *HRTIMx, u */ __STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Source) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1BLKS << REG_SHIFT_TAB_FLTxE[iFault]), (Source << REG_SHIFT_TAB_FLTxE[iFault])); @@ -10150,8 +10144,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKS) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault])); } @@ -10178,8 +10172,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Threshold) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -10204,8 +10198,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -10233,8 +10227,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Mode) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1RSTM << REG_SHIFT_TAB_FLTxE[iFault]), Mode << REG_SHIFT_TAB_FLTxE[iFault]); @@ -10262,8 +10256,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t F */ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); return READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]); } @@ -10288,8 +10282,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { - register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + + uint32_t iFault = (uint8_t)POSITION_VAL(Fault); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CRES) << REG_SHIFT_TAB_FLTxE[iFault]); @@ -10488,7 +10482,7 @@ __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx) { - uint32_t temp; /* MISRAC-2012 compliancy */ + uint32_t temp; /* MISRAC-2012 compliance */ temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL); @@ -11011,8 +11005,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -11034,8 +11028,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); @@ -11058,8 +11052,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); @@ -11082,8 +11076,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); @@ -11106,8 +11100,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -11129,8 +11123,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); @@ -11153,8 +11147,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -11176,8 +11170,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); @@ -11200,8 +11194,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -11223,8 +11217,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); @@ -11247,8 +11241,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -11270,8 +11264,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); @@ -11292,8 +11286,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -11313,8 +11307,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); @@ -11335,8 +11329,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -11356,8 +11350,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); @@ -11378,8 +11372,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -11399,8 +11393,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); @@ -11421,8 +11415,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -11442,8 +11436,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); @@ -11464,8 +11458,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -11485,8 +11479,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); @@ -11507,8 +11501,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -11528,8 +11522,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); @@ -11550,8 +11544,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint3 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -11571,8 +11565,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); @@ -11593,8 +11587,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); } @@ -11614,8 +11608,8 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); @@ -11976,8 +11970,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -11999,8 +11993,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -12022,8 +12016,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); @@ -12046,8 +12040,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint */ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -12069,8 +12063,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer */ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -12092,8 +12086,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); @@ -12116,8 +12110,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -12139,8 +12133,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -12162,8 +12156,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); @@ -12186,8 +12180,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -12209,8 +12203,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -12232,8 +12226,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); @@ -12256,8 +12250,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -12279,8 +12273,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -12302,8 +12296,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); @@ -12326,8 +12320,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -12349,8 +12343,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -12372,8 +12366,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); @@ -12394,8 +12388,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -12415,8 +12409,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -12436,8 +12430,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); @@ -12458,8 +12452,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -12479,8 +12473,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -12500,8 +12494,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); @@ -12522,8 +12516,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -12543,8 +12537,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -12564,8 +12558,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); @@ -12586,8 +12580,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -12607,8 +12601,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -12628,8 +12622,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); @@ -12650,8 +12644,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -12671,8 +12665,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -12692,8 +12686,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); @@ -12714,8 +12708,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -12735,8 +12729,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -12756,8 +12750,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); @@ -12778,8 +12772,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -12799,8 +12793,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer */ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -12820,8 +12814,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); @@ -12842,8 +12836,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -12863,8 +12857,8 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti */ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -12884,8 +12878,8 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); @@ -12949,8 +12943,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -12972,8 +12966,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -12995,8 +12989,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); @@ -13019,8 +13013,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -13042,8 +13036,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -13065,8 +13059,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); @@ -13089,8 +13083,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -13112,8 +13106,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -13135,8 +13129,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); @@ -13159,8 +13153,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -13182,8 +13176,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -13205,8 +13199,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); @@ -13229,8 +13223,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -13252,8 +13246,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -13275,8 +13269,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); @@ -13299,8 +13293,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -13322,8 +13316,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -13345,8 +13339,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); @@ -13367,8 +13361,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -13388,8 +13382,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -13409,8 +13403,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); @@ -13431,8 +13425,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -13452,8 +13446,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -13473,8 +13467,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); @@ -13495,8 +13489,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -13516,8 +13510,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -13537,8 +13531,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); @@ -13559,8 +13553,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -13580,8 +13574,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -13601,8 +13595,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); @@ -13623,8 +13617,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -13644,8 +13638,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -13665,8 +13659,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); @@ -13687,8 +13681,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -13708,8 +13702,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -13729,8 +13723,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); @@ -13751,8 +13745,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, ui */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -13772,8 +13766,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -13793,8 +13787,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); @@ -13815,8 +13809,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uin */ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -13836,8 +13830,8 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ */ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -13857,8 +13851,8 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) { - register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + + uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_i2c.h index 8000eb694c0..789f3cd9b6b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_i2c.h @@ -67,38 +67,38 @@ extern "C" { typedef struct { uint32_t PeripheralMode; /*!< Specifies the peripheral mode. - This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and - the helper macro @ref __LL_I2C_CONVERT_TIMINGS() + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. - This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. - This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). - This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ } LL_I2C_InitTypeDef; @@ -360,11 +360,11 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -578,17 +578,17 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) { /* return address of TXDR register */ - data_reg_addr = (uint32_t) & (I2Cx->TXDR); + data_reg_addr = (uint32_t) &(I2Cx->TXDR); } else { /* return address of RXDR register */ - data_reg_addr = (uint32_t) & (I2Cx->RXDR); + data_reg_addr = (uint32_t) &(I2Cx->RXDR); } return data_reg_addr; @@ -664,7 +664,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) /** * @brief Enable Wakeup from STOP. - * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @note This bit can only be programmed when Digital Filter is disabled. * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop @@ -678,7 +678,7 @@ __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Disable Wakeup from STOP. - * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop * @param I2Cx I2C Instance. @@ -691,7 +691,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Check if Wakeup from STOP is enabled or disabled. - * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop * @param I2Cx I2C Instance. @@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) /** * @brief Configure peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n * CR1 SMBDEN LL_I2C_SetMode @@ -960,7 +960,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) /** * @brief Get peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n * CR1 SMBDEN LL_I2C_GetMode @@ -978,7 +978,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -996,7 +996,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -1014,7 +1014,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert * @param I2Cx I2C Instance. @@ -1027,7 +1027,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC * @param I2Cx I2C Instance. @@ -1040,7 +1040,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC * @param I2Cx I2C Instance. @@ -1053,7 +1053,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC * @param I2Cx I2C Instance. @@ -1066,7 +1066,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Clock Timeout. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n @@ -1089,7 +1089,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo /** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA @@ -1104,7 +1104,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout /** * @brief Get the SMBus Clock TimeoutA setting. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA * @param I2Cx I2C Instance. @@ -1117,7 +1117,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) /** * @brief Set the SMBus Clock TimeoutA mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This bit can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode @@ -1134,7 +1134,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim /** * @brief Get the SMBus Clock TimeoutA mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode * @param I2Cx I2C Instance. @@ -1149,7 +1149,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutB is disabled. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB @@ -1163,8 +1163,8 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout } /** - * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB * @param I2Cx I2C Instance. @@ -1177,7 +1177,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) /** * @brief Enable the SMBus Clock Timeout. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout @@ -1195,7 +1195,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Clock /** * @brief Disable the SMBus Clock Timeout. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout @@ -1213,7 +1213,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc /** * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout @@ -1443,7 +1443,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) /** * @brief Enable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1463,7 +1463,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) /** * @brief Disable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1645,7 +1645,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When the received PEC does not match with the PEC register content. @@ -1660,7 +1660,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When a timeout or extended clock timeout occurs. @@ -1675,7 +1675,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When SMBus host configuration, SMBus alert enabled and @@ -1782,7 +1782,7 @@ __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus PEC error flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR * @param I2Cx I2C Instance. @@ -1795,7 +1795,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1808,7 +1808,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -2090,7 +2090,9 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); } @@ -2123,7 +2125,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) /** * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. * This bit has no effect when RELOAD bit is set. @@ -2139,7 +2141,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare * @param I2Cx I2C Instance. @@ -2152,12 +2154,12 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll PECR PEC LL_I2C_GetSMBusPEC * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF -*/ + */ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.c index a04a458b1d1..c7de8d367c7 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.c @@ -4,7 +4,7 @@ * @author MCD Application Team * @brief LPTIM LL module driver. ****************************************************************************** - * @attention + * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

@@ -13,7 +13,8 @@ * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** + * + ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) @@ -171,14 +172,6 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_Ini return result; } -/** - * @} - */ - -/** - * @} - */ - /** * @brief Disable the LPTIM instance * @rmtoll CR ENABLE LL_LPTIM_Disable @@ -207,11 +200,11 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) /* Save LPTIM source clock */ switch ((uint32_t)LPTIMx) { - case LPTIM1_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); - break; - default: - break; + case LPTIM1_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); + break; + default: + break; } /* Save LPTIM configuration registers */ @@ -232,11 +225,11 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) /* Force LPTIM source kernel clock from APB */ switch ((uint32_t)LPTIMx) { - case LPTIM1_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); - break; - default: - break; + case LPTIM1_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); + break; + default: + break; } if (tmpCMP != 0UL) @@ -249,7 +242,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } + while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } @@ -264,11 +258,13 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } + while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } + /* Restore LPTIM source kernel clock */ LL_RCC_SetLPTIMClockSource(tmpclksource); } @@ -286,6 +282,14 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) * @} */ +/** + * @} + */ + +/** + * @} + */ + /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.h index 787490334c9..1b0198add08 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.h @@ -4,7 +4,7 @@ * @author MCD Application Team * @brief Header file of LPTIM LL module. ****************************************************************************** - * @attention + * @attention * *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

@@ -155,7 +155,7 @@ typedef struct /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type * @{ */ -#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } /** @@ -436,7 +435,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); } /** @@ -487,7 +486,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled * @note After a write to the LPTIMx_ARR register a new write operation to the * same register can only be performed when the previous write operation - * is completed. Any successive write before the ARROK flag be set, will + * is completed. Any successive write before the ARROK flag is set, will * lead to unpredictable results. * @note autoreload value be strictly greater than the compare value. * @rmtoll ARR ARR LL_LPTIM_SetAutoReload @@ -515,7 +514,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) * @brief Set the compare value * @note After a write to the LPTIMx_CMP register a new write operation to the * same register can only be performed when the previous write operation - * is completed. Any successive write before the CMPOK flag be set, will + * is completed. Any successive write before the CMPOK flag is set, will * lead to unpredictable results. * @rmtoll CMP CMP LL_LPTIM_SetCompare * @param LPTIMx Low-Power Timer instance @@ -703,7 +702,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) /** * @brief Set LPTIM input 1 source (default GPIO). - * @rmtoll OR IN1 LL_LPTIM_SetInput1Src + * @rmtoll OR IN1 LL_LPTIM_SetInput1Src * @param LPTIMx Low-Power Timer instance * @param Src This parameter can be one of the following values: * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO @@ -716,12 +715,12 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) { - WRITE_REG(LPTIMx->OR, Src); + MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN1, Src); } /** * @brief Set LPTIM input 2 source (default GPIO). - * @rmtoll OR IN2 LL_LPTIM_SetInput2Src + * @rmtoll OR IN2 LL_LPTIM_SetInput2Src * @param LPTIMx Low-Power Timer instance * @param Src This parameter can be one of the following values: * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO @@ -733,7 +732,7 @@ __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) */ __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) { - WRITE_REG(LPTIMx->OR, Src); + MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN2, Src); } /** @@ -783,7 +782,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } /** @@ -1061,7 +1060,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } /** @@ -1091,7 +1090,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** @@ -1106,14 +1105,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occured. + * @brief Inform application whether a autoreload match interrupt has occurred. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } /** @@ -1135,7 +1134,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } /** @@ -1157,7 +1156,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } /** @@ -1179,7 +1178,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } /** @@ -1201,7 +1200,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } /** @@ -1223,7 +1222,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } /** @@ -1264,7 +1263,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } /** @@ -1297,7 +1296,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } /** @@ -1330,7 +1329,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } /** @@ -1363,7 +1362,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } /** @@ -1392,11 +1391,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } /** @@ -1425,11 +1424,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) { - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } /** @@ -1458,11 +1457,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) { - return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL); + return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.c index 7b1564a3831..670fa9b8abe 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.c @@ -153,8 +153,10 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) /** * @brief Initialize LPUART registers according to the specified * parameters in LPUART_InitStruct. - * @note As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0), - * LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in LPUART configuration registers can only be written when + * the LPUART is disabled (USART_CR1_UE bit =0), + * LPUART Peripheral should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. * @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0). * @param LPUARTx LPUART Instance * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure @@ -200,7 +202,8 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART /*---------------------------- LPUART CR3 Configuration ----------------------- * Configure LPUARTx CR3 (Hardware Flow Control) with parameters: - * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value. + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according + * to LPUART_InitStruct->HardwareFlowControl value. */ LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.h index 54d496ff872..5ffe06bc9ea 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.h @@ -100,36 +100,43 @@ typedef struct uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetPrescaler().*/ uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetBaudRate().*/ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetDataWidth().*/ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetStopBitsLength().*/ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref LPUART_LL_EC_PARITY. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetParity().*/ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetTransferDirection().*/ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetHWFlowCtrl().*/ } LL_LPUART_InitTypeDef; @@ -267,18 +274,18 @@ typedef struct /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler * @{ */ -#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */ -#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */ -#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */ -#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */ -#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */ -#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */ -#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */ -#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */ -#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */ -#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */ -#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */ -#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ /** * @} */ @@ -442,8 +449,9 @@ typedef struct * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ -#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\ - + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ + ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ + * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) /** * @} @@ -629,7 +637,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); + MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** @@ -1345,7 +1354,10 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) { - LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + if (BaudRate != 0U) + { + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + } } /** @@ -1372,9 +1384,9 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri */ __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) { - register uint32_t lpuartdiv; - register uint32_t brrresult; - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + uint32_t lpuartdiv; + uint32_t brrresult; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; @@ -2482,7 +2494,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUAR */ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) { diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_opamp.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_opamp.h index c938df4855e..dafdfa28830 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_opamp.h @@ -181,18 +181,18 @@ typedef struct */ #define LL_OPAMP_INPUT_NONINVERT_IO0 (0x00000000UL) /*!< OPAMP non inverting input connected to I/O VINP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_NONINVERT_IO1 OPAMP_CSR_VPSEL_0 /*!< OPAMP non inverting input connected to I/O VINP1 (PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_NONINVERT_IO2 OPAMP_CSR_VPSEL_1 /*!< OPAMP non inverting input connected to I/O VINP2 (PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_NONINVERT_IO3 OPAMP_CSR_VPSEL /*!< OPAMP non inverting input connected to I/O VINP3 (PD14 for OPAMP2) */ #define LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL /*!< OPAMP non inverting input connected internally to DAC channel (DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ /** * @} */ @@ -204,12 +204,12 @@ typedef struct */ #define LL_OPAMP_INPUT_INVERT_IO0 (0x00000000UL) /*!< OPAMP inverting input connected to I/O VINM0 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0 /*!< OPAMP inverting input connected to I/0 VINM1 (PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1 /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA with positive gain without bias). - Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */ + Note: On this STM32 series, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */ /** * @} */ @@ -219,18 +219,18 @@ typedef struct */ #define LL_OPAMP_INPUT_NONINVERT_IO0_SEC (0x00000000UL) /*!< OPAMP secondary non inverting input connected to I/O VINP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_NONINVERT_IO1_SEC OPAMP_TCMR_VPSSEL_0 /*!< OPAMP secondary non inverting input connected to I/O VINP1 (PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_NONINVERT_IO2_SEC OPAMP_TCMR_VPSSEL_1 /*!< OPAMP secondary non inverting input connected to I/O VINP2 (PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_NONINVERT_IO3_SEC OPAMP_TCMR_VPSSEL /*!< OPAMP secondary non inverting input connected to I/O VINP3 (PD14 for OPAMP2) */ #define LL_OPAMP_INPUT_NONINVERT_DAC_SEC OPAMP_TCMR_VPSSEL /*!< OPAMP secondary non inverting input connected internally to DAC channel (DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ /** * @} */ @@ -244,12 +244,12 @@ typedef struct has been configured by call to @ref LL_OPAMP_Init() or @ref LL_OPAMP_SetFunctionalMode(). OPAMP secondary inverting input connected to I/O VINM0. (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_INVERT_IO1_SEC OPAMP_TCMR_VMSSEL /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref LL_OPAMP_MODE_STANDALONE has been configured by call to @ref LL_OPAMP_Init() or @ref LL_OPAMP_SetFunctionalMode(). OPAMP secondary inverting input connected to I/0 VINM1 (PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_INVERT_PGA_SEC (0x00000000UL) /*!< OPAMP secondary mode is PGA mode - Only applicable if configured mode through call to @ref LL_OPAMP_Init() or @ref LL_OPAMP_SetFunctionalMode() is NOT @ref LL_OPAMP_MODE_STANDALONE. OPAMP secondary inverting input is: @@ -274,7 +274,7 @@ typedef struct - OPAMP4 internal output is connected to ADC5/Channel5 - OPAMP5 internal output is connected to ADC5/Channel3 - OPAMP6 internal output is connected to ADC4/Channel17 - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ /** * @} */ @@ -289,7 +289,7 @@ typedef struct #define LL_OPAMP_INPUT_MUX_TIM1_CH6 OPAMP_TCMR_T1CMEN /*!< OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM1 OC6. */ #define LL_OPAMP_INPUT_MUX_TIM8_CH6 OPAMP_TCMR_T8CMEN /*!< OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM8 OC6. */ #define LL_OPAMP_INPUT_MUX_TIM20_CH6 OPAMP_TCMR_T20CMEN /*!< OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM20 OC6. - Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */ /** * @} */ @@ -613,7 +613,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t */ __STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx) { - register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL); + uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL); /* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting */ /* input not connected. */ @@ -697,7 +697,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetInputInvertingSecondary(OPAMP_TypeDef *OPAM * @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6 * @arg @ref LL_OPAMP_INPUT_MUX_TIM8_CH6 * @arg @ref LL_OPAMP_INPUT_MUX_TIM20_CH6 (1) - * On this STM32 serie, this value is not available on all devices. Refer to datasheet for details. + * On this STM32 series, this value is not available on all devices. Refer to datasheet for details. * @retval None */ __STATIC_INLINE void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode) @@ -714,7 +714,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t I * @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6 * @arg @ref LL_OPAMP_INPUT_MUX_TIM8_CH6 * @arg @ref LL_OPAMP_INPUT_MUX_TIM20_CH6 (1) - * On this STM32 serie, this value is not available on all devices. Refer to datasheet for details. + * On this STM32 series, this value is not available on all devices. Refer to datasheet for details. */ __STATIC_INLINE uint32_t LL_OPAMP_GetInputsMuxMode(OPAMP_TypeDef *OPAMPx) { @@ -828,7 +828,7 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin */ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) { - register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); + uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); return (CalibrationSelection | (((CalibrationSelection & OPAMP_CSR_CALSEL_1) == 0UL) ? OPAMP_CSR_TRIMOFFSETP : OPAMP_CSR_TRIMOFFSETN)); @@ -897,7 +897,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32 /** * @brief Enable OPAMP instance. * @note After enable from off state, OPAMP requires a delay - * to fullfill wake up time specification. + * to fulfill wake up time specification. * Refer to device datasheet, parameter "tWAKEUP". * @rmtoll CSR OPAMPXEN LL_OPAMP_Enable * @param OPAMPx OPAMP instance diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_pwr.h index 5133b0cd6fa..64568d8cbe0 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_pwr.h @@ -433,87 +433,85 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) #if defined(PWR_CR3_UCPD_STDBY) /** - * @brief Enable (write 1) the USB Type-C and Power Delivery standby mode. - * @note Enable just before entering standby when using UCPD1. - * @rmtoll CR3 UCPD1_STDBY LL_PWR_EnableUSBStandByModePD + * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode. + * @note This function must be called just before entering Standby mode. + * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode * @retval None */ -__STATIC_INLINE void LL_PWR_EnableUSBStandByModePD(void) +__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void) { SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); } /** - * @brief Disable (write 0) USB Type-C and Power Delivery standby mode. - * @note Disable immediately after standby exit when using UCPD1, - * (and before writing any UCPD1 registers). - * @rmtoll CR3 UCPD1_STDBY LL_PWR_DisableUSBStandByModePD + * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode. + * @note This function must be called after exiting Standby mode and before any + * UCPD configuration update. + * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode * @retval None */ -__STATIC_INLINE void LL_PWR_DisableUSBStandByModePD(void) +__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); } /** - * @brief Check the USB Type-C and Power Delivery standby mode. - * @rmtoll CR3 UCPD1_STDBY LL_PWR_IsEnabledUSBStandByModePD + * @brief Check the USB Type-C and Power Delivery Standby mode memorization state. + * @rmtoll CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBStandByModePD(void) +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void) { - return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY))?1UL:0UL); + return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL); } #endif /* PWR_CR3_UCPD_STDBY */ #if defined(PWR_CR3_UCPD_DBDIS) /** - * @brief Enable (write 0) USB Type-C dead battery pull-down behavior - * on UCPD1_CC1 and UCPD1_CC2 pins. - * @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it - * in all cases, either to stop this pull-down or to hand over control to the UCPD1 - * (which should therefore be initialized before doing the disable). - * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_EnableUSBDeadBattery + * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery * @retval None */ -__STATIC_INLINE void LL_PWR_EnableUSBDeadBattery(void) +__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); } /** - * @brief Disable (write 1) USB Type-C dead battery pull-down behavior - * on UCPD1_CC1 and UCPD1_CC2 pins. - * @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it - * in all cases, either to stop this pull-down or to hand over control to the UCPD1 - * (which should therefore be initialized before doing the disable). - * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_DisableUSBDeadBattery + * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery * @retval None */ -__STATIC_INLINE void LL_PWR_DisableUSBDeadBattery(void) +__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void) { SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); } /** - * @brief Check USB Type-C dead battery pull-down behavior - * on UCPD1_CC1 and UCPD1_CC2 pins. - * @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled, - * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it - * in all cases, either to stop this pull-down or to hand over control to the UCPD1 - * (which should therefore be initialized before doing the disable). - * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_IsEnabledUSBDeadBattery - * @retval State of bit. + * @brief Check the USB Type-C and power delivery dead battery pull-down behavior + * on UCPD CC1 and CC2 pins. + * @note After exiting reset, the USB Type-C dead battery behavior is enabled, + * which may have a pull-down effect on CC1 and CC2 pins. It is recommended + * to disable it in all cases, either to stop this pull-down or to hand over + * control to the UCPD (which should therefore be initialized before doing the disable). + * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery + * @retval State of feature (1 : enabled; 0 : disabled). */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBDeadBattery(void) +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void) { - - return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS))?1UL:0UL); - + return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL); } #endif /* PWR_CR3_UCPD_DBDIS */ @@ -598,7 +596,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_VDDA_COMP (*) * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*) - * @arg @ref LL_PWR_PVM_VDDA_ADC + * @arg @ref LL_PWR_PVM_VDDA_ADC * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC * * (*) value not defined in all devices @@ -618,7 +616,7 @@ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_VDDA_COMP (*) * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*) - * @arg @ref LL_PWR_PVM_VDDA_ADC + * @arg @ref LL_PWR_PVM_VDDA_ADC * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC * * (*) value not defined in all devices @@ -638,7 +636,7 @@ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) * @param PeriphVoltage This parameter can be one of the following values: * @arg @ref LL_PWR_PVM_VDDA_COMP (*) * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*) - * @arg @ref LL_PWR_PVM_VDDA_ADC + * @arg @ref LL_PWR_PVM_VDDA_ADC * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC * * (*) value not defined in all devices @@ -753,50 +751,6 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL); } -#if defined (PWR_CR3_UCPD_DBDIS) -/** - * @brief Enable USB Type-C and Power Delivery Dead Battery disable - * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableDeadBatteryPD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableDeadBatteryPD(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); -} - -/** - * @brief Disable USB Type-C and Power Delivery Dead Battery disable - * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableDeadBatteryPD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableDeadBatteryPD(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); -} -#endif /* PWR_CR3_UCPD_DBDIS */ - -#if defined(PWR_CR3_UCPD_STDBY) -/** - * @brief Enable USB Type-C and Power Delivery standby mode. - * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableStandByModePD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableStandByModePD(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); -} - -/** - * @brief Disable USB Type-C and Power Delivery standby mode. - * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableStandByModePD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableStandByModePD(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY); -} -#endif /* PWR_CR3_UCPD_STDBY */ - /** * @brief Enable pull-up and pull-down configuration * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg @@ -1613,6 +1567,16 @@ ErrorStatus LL_PWR_DeInit(void); /* Old functions name kept for legacy purpose, to be replaced by the */ /* current functions name. */ #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS +#define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery +#define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery +#define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery +#define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery +#define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery +#define LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode +#define LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode +#define LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode +#define LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode +#define LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rtc.c index 317f891e773..f0316ebcf77 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rtc.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rtc.h index b03add7e8c4..28c050e90b7 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rtc.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2019 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the @@ -1346,7 +1346,7 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp; + uint32_t temp; temp = Format12_24 | \ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ @@ -1374,7 +1374,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ @@ -1677,7 +1677,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) { - register uint32_t temp; + uint32_t temp; temp = (WeekDay << RTC_DR_WDU_Pos) | \ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ @@ -1705,7 +1705,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - register uint32_t temp; + uint32_t temp; temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ @@ -2006,7 +2006,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp; + uint32_t temp; temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ @@ -2374,7 +2374,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp; + uint32_t temp; temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ @@ -3180,15 +3180,14 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) { - register uint32_t tmp = 0U; + __IO uint32_t *tmp; UNUSED(RTCx); - tmp = (uint32_t)(&(TAMP->BKP0R)); - tmp += (BackupRegister * 4U); + tmp = &(TAMP->BKP0R) + BackupRegister; /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; + *tmp = Data; } /** @@ -3205,15 +3204,14 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe */ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) { - register uint32_t tmp = 0U; + const __IO uint32_t *tmp; UNUSED(RTCx); - tmp = (uint32_t)(&(TAMP->BKP0R)); - tmp += (BackupRegister * 4U); + tmp = &(TAMP->BKP0R) + BackupRegister; /* Read the specified register */ - return (*(__IO uint32_t *)tmp); + return *tmp; } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_spi.h index 159aba19c84..3fdab8c2576 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_spi.h @@ -266,8 +266,8 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold * @{ */ -#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ -#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ /** * @} */ @@ -848,8 +848,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) */ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) { - register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); - register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); return (Ssm | Ssoe); } @@ -1501,10 +1501,10 @@ typedef struct /** @defgroup I2S_LL_EC_DATA_FORMAT Data format * @{ */ -#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ -#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */ /** * @} */ @@ -1839,7 +1839,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) } /** - * @brief Enable the master clock ouput (Pin MCK) + * @brief Enable the master clock output (Pin MCK) * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock * @param SPIx SPI Instance * @retval None @@ -1850,7 +1850,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) } /** - * @brief Disable the master clock ouput (Pin MCK) + * @brief Disable the master clock output (Pin MCK) * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock * @param SPIx SPI Instance * @retval None @@ -1861,7 +1861,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) } /** - * @brief Check if the master clock ouput (Pin MCK) is enabled + * @brief Check if the master clock output (Pin MCK) is enabled * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock * @param SPIx SPI Instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_system.h index 2f3202cb59a..01781405e67 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_system.h @@ -305,7 +305,7 @@ extern "C" { */ #define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */ #define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */ -#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.8V) */ +#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.c index e3e5f496028..f6f42da9912 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.c @@ -320,7 +320,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; + TIM_InitStruct->RepetitionCounter = 0x00000000U; } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.h index 89b84cdc4f9..c72956b21dd 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.h @@ -126,48 +126,9 @@ static const uint8_t SHIFT_TAB_OISx[] = #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) /* Generic bit definitions for TIMx_AF1 register */ -#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKIN input enable */ -#define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /*!< BRK COMP1 enable */ -#define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /*!< BRK COMP2 enable */ -#define TIMx_AF1_BKCOMP3E TIM1_AF1_BKCMP3E /*!< BRK COMP3 enable */ -#define TIMx_AF1_BKCOMP4E TIM1_AF1_BKCMP4E /*!< BRK COMP4 enable */ -#if defined(COMP5) -#define TIMx_AF1_BKCOMP5E TIM1_AF1_BKCMP5E /*!< BRK COMP5 enable */ -#endif /* COMP5 */ -#if defined(COMP6) -#define TIMx_AF1_BKCOMP6E TIM1_AF1_BKCMP6E /*!< BRK COMP6 enable */ -#endif /* COMP6 */ -#if defined(COMP7) -#define TIMx_AF1_BKCOMP7E TIM1_AF1_BKCMP7E /*!< BRK COMP7 enable */ -#endif /* COMP7 */ #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ -#define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /*!< BRK COMP1 input polarity */ -#define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /*!< BRK COMP2 input polarity */ -#define TIMx_AF1_BKCOMP3P TIM1_AF1_BKCMP3P /*!< BRK COMP3 input polarity */ -#define TIMx_AF1_BKCOMP4P TIM1_AF1_BKCMP4P /*!< BRK COMP4 input polarity */ #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */ -/* Generic bit definitions for TIMx_AF2 register */ -#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK2 BKIN2 input enable */ -#define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /*!< BRK2 COMP1 enable */ -#define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /*!< BRK2 COMP2 enable */ -#define TIMx_AF2_BK2COMP3E TIM1_AF2_BK2CMP3E /*!< BRK2 COMP3 enable */ -#define TIMx_AF2_BK2COMP4E TIM1_AF2_BK2CMP4E /*!< BRK2 COMP4 enable */ -#if defined(COMP5) -#define TIMx_AF2_BK2COMP5E TIM1_AF2_BK2CMP5E /*!< BRK2 COMP5 enable */ -#endif /* COMP5 */ -#if defined(COMP6) -#define TIMx_AF2_BK2COMP6E TIM1_AF2_BK2CMP6E /*!< BRK2 COMP6 enable */ -#endif /* COMP6 */ -#if defined(COMP7) -#define TIMx_AF2_BK2COMP7E TIM1_AF2_BK2CMP7E /*!< BRK2 COMP7 enable */ -#endif /* COMP7 */ -#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK2 BKIN2 input polarity */ -#define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /*!< BRK2 COMP1 input polarity */ -#define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /*!< BRK2 COMP2 input polarity */ -#define TIMx_AF2_BK2COMP3P TIM1_AF2_BK2CMP3P /*!< BRK2 COMP3 input polarity */ -#define TIMx_AF2_BK2COMP4P TIM1_AF2_BK2CMP4P /*!< BRK2 COMP4 input polarity */ - /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ #define DT_DELAY_1 ((uint8_t)0x7F) @@ -273,13 +234,14 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; @@ -654,8 +616,8 @@ typedef struct */ #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR1, TIM_CR1_UIFREMAP); } +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + /** * @brief Enable dithering. * @note Macro @ref IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not @@ -2634,8 +2606,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -2681,8 +2653,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -2722,8 +2694,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -2758,7 +2730,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2792,7 +2764,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -2831,7 +2803,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann */ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); } @@ -2865,7 +2837,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); } @@ -2890,8 +2862,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2916,8 +2888,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2942,9 +2914,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2968,8 +2940,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha */ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2993,8 +2965,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -3018,9 +2990,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -3047,8 +3019,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -3074,8 +3046,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -3103,9 +3075,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -3460,8 +3432,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -3488,8 +3460,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 */ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -3512,8 +3484,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3538,8 +3510,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch */ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -3563,8 +3535,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3601,8 +3573,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -3638,8 +3610,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui */ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3667,7 +3639,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); } @@ -3695,7 +3667,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -4215,7 +4187,6 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u */ __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) { - MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); } @@ -4639,7 +4610,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); SET_BIT(*pReg, Source); } @@ -4682,7 +4653,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); CLEAR_BIT(*pReg, Source); } @@ -4718,7 +4689,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); } /** @@ -4761,7 +4732,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx) } /** - * @brief Set the falling egde dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals). + * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals). * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not * asymmetrical dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter @@ -4778,7 +4749,7 @@ __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadT } /** - * @brief Get the falling egde dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals). + * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals). * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not * asymmetrical dead-time insertion feature is supported by a timer instance. * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed @@ -5027,7 +4998,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx) } /** - * @brief Set index positionning + * @brief Set index positioning * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an index input. * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning @@ -5047,7 +5018,7 @@ __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t Ind } /** - * @brief Get actual index positionning + * @brief Get actual index positioning * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an index input. * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_ucpd.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_ucpd.c index a8757ef5c25..f7736e12bb7 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_ucpd.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_ucpd.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -94,7 +94,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) /* Release reset of ucpd clock */ LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1); - /* Disbale ucpd clock */ + /* Disable ucpd clock */ LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1); status = SUCCESS; @@ -143,10 +143,10 @@ ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStru void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct) { /* Set UCPD_InitStruct fields to default values */ - UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV1; + UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV2; UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */ UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ - UCPD_InitStruct->HbitClockDiv = 0x1A; /* Divide by 27 to produce HBITCLK */ + UCPD_InitStruct->HbitClockDiv = 0x0D; /* Divide by 14 to produce HBITCLK */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_ucpd.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_ucpd.h index 078a677cd1b..c96ee99f0f2 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_ucpd.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_ucpd.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -126,8 +126,7 @@ typedef struct #define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */ #define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */ #define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */ -#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGEND /*!< Enable Rx message received */ -#define LL_UCPD_IMR_RXERR UCPD_IMR_RXMSGENDIE /*!< Enable Rx error */ +#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE /*!< Enable Rx message received */ #define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */ #define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */ #define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE /*!< Enable fast Role Swap detection event */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.c index 911654dbfda..6a64c29a1d2 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.c @@ -191,8 +191,9 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) /** * @brief Initialize USART registers according to the specified * parameters in USART_InitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure @@ -243,7 +244,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /*---------------------------- USART CR3 Configuration --------------------- * Configure USARTx CR3 (Hardware Flow Control) with parameters: - * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to + * USART_InitStruct->HardwareFlowControl value. */ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); @@ -335,13 +337,15 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) /** * @brief Initialize USART Clock related settings according to the * specified parameters in the USART_ClockInitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content + * - SUCCESS: USART registers related to Clock settings are initialized according + * to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) @@ -407,9 +411,12 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { /* Set LL_USART_ClockInitStruct fields with default values */ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; - USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.h index 4f1af73ac01..f716e2eb4cf 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.h @@ -88,41 +88,49 @@ typedef struct uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of @ref USART_LL_EC_PRESCALER. - This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_LL_EC_STOPBITS. - This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_LL_EC_PARITY. - This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_DIRECTION. - This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ } LL_USART_InitTypeDef; @@ -141,20 +149,23 @@ typedef struct uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. This parameter can be a value of @ref USART_LL_EC_POLARITY. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). For more details, refer to description of this function. */ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_LL_EC_PHASE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). For more details, refer to description of this function. */ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function. */ } LL_USART_ClockInitTypeDef; @@ -357,18 +368,18 @@ typedef struct /** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler * @{ */ -#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */ -#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */ -#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */ -#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */ -#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */ -#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */ -#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */ -#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */ -#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */ -#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */ -#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */ -#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ /** * @} */ @@ -563,8 +574,9 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @brief Compute USARTDIV value according to Peripheral Clock and @@ -586,8 +598,9 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @} @@ -645,7 +658,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) /** * @brief FIFO Mode Enable - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO * @param USARTx USART Instance @@ -658,7 +671,7 @@ __STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) /** * @brief FIFO Mode Disable - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO * @param USARTx USART Instance @@ -671,7 +684,7 @@ __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) /** * @brief Indicate if FIFO Mode is enabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO * @param USARTx USART Instance @@ -684,7 +697,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) /** * @brief Configure TX FIFO Threshold - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold * @param USARTx USART Instance @@ -704,7 +717,7 @@ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t /** * @brief Return TX FIFO Threshold Configuration - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold * @param USARTx USART Instance @@ -723,7 +736,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) /** * @brief Configure RX FIFO Threshold - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold * @param USARTx USART Instance @@ -743,7 +756,7 @@ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t /** * @brief Return RX FIFO Threshold Configuration - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold * @param USARTx USART Instance @@ -762,7 +775,7 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) /** * @brief Configure TX and RX FIFOs Threshold - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold @@ -785,14 +798,15 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); + MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** * @brief USART enabled in STOP Mode. * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that * USART clock selection is HSI or LSE in RCC. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_EnableInStopMode * @param USARTx USART Instance @@ -806,7 +820,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) /** * @brief USART disabled in STOP Mode. * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_DisableInStopMode * @param USARTx USART Instance @@ -819,7 +833,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) /** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode * @param USARTx USART Instance @@ -1062,7 +1076,7 @@ __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) /** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput * @param USARTx USART Instance @@ -1079,7 +1093,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 /** * @brief Retrieve Clock pulse of the last data bit output configuration * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput * @param USARTx USART Instance @@ -1094,7 +1108,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) /** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_SetClockPhase * @param USARTx USART Instance @@ -1110,7 +1124,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc /** * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_GetClockPhase * @param USARTx USART Instance @@ -1125,7 +1139,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) /** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_SetClockPolarity * @param USARTx USART Instance @@ -1141,7 +1155,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C /** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_GetClockPolarity * @param USARTx USART Instance @@ -1156,7 +1170,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) /** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function @@ -1184,7 +1198,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, /** * @brief Configure Clock source prescaler for baudrate generator and oversampling - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler * @param USARTx USART Instance @@ -1210,7 +1224,7 @@ __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t Presc /** * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler * @param USARTx USART Instance @@ -1235,7 +1249,7 @@ __STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx) /** * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput * @param USARTx USART Instance @@ -1248,7 +1262,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput * @param USARTx USART Instance @@ -1261,7 +1275,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput * @param USARTx USART Instance @@ -1480,7 +1494,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) /** * @brief Enable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate * @param USARTx USART Instance @@ -1493,7 +1507,7 @@ __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) /** * @brief Disable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate * @param USARTx USART Instance @@ -1506,7 +1520,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) /** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud * @param USARTx USART Instance @@ -1519,7 +1533,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) /** * @brief Set Auto Baud-Rate mode bits - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode * @param USARTx USART Instance @@ -1537,7 +1551,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_ /** * @brief Return Auto Baud-Rate mode - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode * @param USARTx USART Instance @@ -1644,7 +1658,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) /** * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl * @param USARTx USART Instance @@ -1657,7 +1671,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl * @param USARTx USART Instance @@ -1670,7 +1684,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl * @param USARTx USART Instance @@ -1683,7 +1697,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl * @param USARTx USART Instance @@ -1696,7 +1710,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n * CR3 CTSE LL_USART_SetHWFlowCtrl @@ -1715,7 +1729,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard /** * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n * CR3 CTSE LL_USART_GetHWFlowCtrl @@ -1799,7 +1813,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) /** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUS LL_USART_SetWKUPType * @param USARTx USART Instance @@ -1816,7 +1830,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) /** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUS LL_USART_GetWKUPType * @param USARTx USART Instance @@ -1864,12 +1878,16 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph uint32_t BaudRate) { uint32_t usartdiv; - register uint32_t brrtemp; + uint32_t brrtemp; if (PrescalerValue > LL_USART_PRESCALER_DIV256) { /* Do not overstep the size of USART_PRESCALER_TAB */ } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } else if (OverSampling == LL_USART_OVERSAMPLING_8) { usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); @@ -1912,9 +1930,9 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) { - register uint32_t usartdiv; - register uint32_t brrresult = 0x0U; - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); usartdiv = USARTx->BRR; @@ -1996,7 +2014,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) /** * @brief Enable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_EnableIrda * @param USARTx USART Instance @@ -2009,7 +2027,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) /** * @brief Disable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_DisableIrda * @param USARTx USART Instance @@ -2022,7 +2040,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) /** * @brief Indicate if IrDA mode is enabled - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_IsEnabledIrda * @param USARTx USART Instance @@ -2035,7 +2053,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) /** * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode * @param USARTx USART Instance @@ -2051,7 +2069,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P /** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode * @param USARTx USART Instance @@ -2067,7 +2085,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) /** * @brief Set Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler * @param USARTx USART Instance @@ -2082,7 +2100,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P /** * @brief Return Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler * @param USARTx USART Instance @@ -2103,7 +2121,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) /** * @brief Enable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK * @param USARTx USART Instance @@ -2116,7 +2134,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Disable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK * @param USARTx USART Instance @@ -2129,7 +2147,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK * @param USARTx USART Instance @@ -2142,7 +2160,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Enable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_EnableSmartcard * @param USARTx USART Instance @@ -2155,7 +2173,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) /** * @brief Disable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_DisableSmartcard * @param USARTx USART Instance @@ -2168,7 +2186,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard mode is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard * @param USARTx USART Instance @@ -2181,7 +2199,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) /** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. * In transmission mode, it specifies the number of automatic retransmission retries, before @@ -2200,7 +2218,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, /** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount * @param USARTx USART Instance @@ -2214,7 +2232,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR /** * @brief Set Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler * @param USARTx USART Instance @@ -2229,7 +2247,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler * @param USARTx USART Instance @@ -2243,7 +2261,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) /** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime * @param USARTx USART Instance @@ -2258,7 +2276,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime * @param USARTx USART Instance @@ -2279,7 +2297,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) /** * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex * @param USARTx USART Instance @@ -2292,7 +2310,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex * @param USARTx USART Instance @@ -2305,7 +2323,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex * @param USARTx USART Instance @@ -2325,7 +2343,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) */ /** * @brief Enable SPI Synchronous Slave mode - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave * @param USARTx USART Instance @@ -2338,7 +2356,7 @@ __STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) /** * @brief Disable SPI Synchronous Slave mode - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave * @param USARTx USART Instance @@ -2351,7 +2369,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) /** * @brief Indicate if SPI Synchronous Slave mode is enabled - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave * @param USARTx USART Instance @@ -2364,7 +2382,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx) /** * @brief Enable SPI Slave Selection using NSS input pin - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @note SPI Slave Selection depends on NSS input pin * (The slave is selected when NSS is low and deselected when NSS is high). @@ -2379,7 +2397,7 @@ __STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) /** * @brief Disable SPI Slave Selection using NSS input pin - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @note SPI Slave will be always selected and NSS input pin will be ignored. * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect @@ -2393,7 +2411,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) /** * @brief Indicate if SPI Slave Selection depends on NSS input pin - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect * @param USARTx USART Instance @@ -2414,7 +2432,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx) /** * @brief Set LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen * @param USARTx USART Instance @@ -2430,7 +2448,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 /** * @brief Return LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen * @param USARTx USART Instance @@ -2445,7 +2463,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) /** * @brief Enable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_EnableLIN * @param USARTx USART Instance @@ -2458,7 +2476,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) /** * @brief Disable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_DisableLIN * @param USARTx USART Instance @@ -2471,7 +2489,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) /** * @brief Indicate if LIN mode is enabled - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN * @param USARTx USART Instance @@ -2492,7 +2510,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) /** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime * @param USARTx USART Instance @@ -2506,7 +2524,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 /** * @brief Return DEDT (Driver Enable De-Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime * @param USARTx USART Instance @@ -2519,7 +2537,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) /** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime * @param USARTx USART Instance @@ -2533,7 +2551,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t /** * @brief Return DEAT (Driver Enable Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime * @param USARTx USART Instance @@ -2546,7 +2564,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) /** * @brief Enable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_EnableDEMode * @param USARTx USART Instance @@ -2559,7 +2577,7 @@ __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) /** * @brief Disable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_DisableDEMode * @param USARTx USART Instance @@ -2572,7 +2590,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) /** * @brief Indicate if Driver Enable (DE) Mode is enabled - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode * @param USARTx USART Instance @@ -2585,7 +2603,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) /** * @brief Select Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity * @param USARTx USART Instance @@ -2601,7 +2619,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_ /** * @brief Return Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity * @param USARTx USART Instance @@ -2651,7 +2669,8 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) { /* In Asynchronous mode, the following bits must be kept cleared: - LINEN, CLKEN bits in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); } @@ -2664,7 +2683,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2687,7 +2706,8 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) { /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); /* set the UART/USART in Synchronous mode */ @@ -2702,7 +2722,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also set the UART/USART in LIN mode. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function @@ -2727,7 +2747,8 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) { /* In LIN mode, the following bits must be kept cleared: - STOP and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); /* Set the UART/USART in LIN mode */ @@ -2742,7 +2763,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - IREN bit in the USART_CR3 register, * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2765,7 +2786,8 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) { /* In Half Duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ + - SCEN and IREN bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); /* set the UART/USART in Half Duplex mode */ @@ -2781,7 +2803,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) * This function also configures Stop bits to 1.5 bits and * sets the USART in Smartcard mode (SCEN bit). * Clock Output is also enabled (CLKEN). - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2805,7 +2827,8 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) { /* In Smartcard mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - IREN and HDSEL bits in the USART_CR3 register.*/ + - IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); /* Configure Stop bits to 1.5 bits */ @@ -2823,7 +2846,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2848,7 +2871,8 @@ __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) { /* In IRDA mode, the following bits must be kept cleared: - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ + - SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); /* set the UART/USART in IRDA mode */ @@ -2886,7 +2910,8 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) { /* In Multi Processor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); } @@ -2959,7 +2984,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) /** * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE * @param USARTx USART Instance @@ -2986,7 +3011,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) /** * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF * @param USARTx USART Instance @@ -2999,7 +3024,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) /** * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD * @param USARTx USART Instance @@ -3012,7 +3037,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) /** * @brief Check if the USART CTS interrupt Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS * @param USARTx USART Instance @@ -3025,7 +3050,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) /** * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS * @param USARTx USART Instance @@ -3049,7 +3074,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) /** * @brief Check if the USART End Of Block Flag is set or not - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB * @param USARTx USART Instance @@ -3062,7 +3087,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) /** * @brief Check if the SPI Slave Underrun error flag is set or not - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR * @param USARTx USART Instance @@ -3075,7 +3100,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) /** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE * @param USARTx USART Instance @@ -3088,7 +3113,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) /** * @brief Check if the USART Auto-Baud Rate Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR * @param USARTx USART Instance @@ -3145,7 +3170,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) /** * @brief Check if the USART Wake Up from stop mode Flag is set or not - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP * @param USARTx USART Instance @@ -3180,7 +3205,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) /** * @brief Check if the USART TX FIFO Empty Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE * @param USARTx USART Instance @@ -3193,7 +3218,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) /** * @brief Check if the USART RX FIFO Full Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF * @param USARTx USART Instance @@ -3217,7 +3242,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) /** * @brief Check if the USART TX FIFO Threshold Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT * @param USARTx USART Instance @@ -3230,7 +3255,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) /** * @brief Check if the USART RX FIFO Threshold Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT * @param USARTx USART Instance @@ -3298,7 +3323,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) /** * @brief Clear TX FIFO Empty Flag - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE * @param USARTx USART Instance @@ -3333,7 +3358,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) /** * @brief Clear LIN Break Detection Flag - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD * @param USARTx USART Instance @@ -3346,7 +3371,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) /** * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS * @param USARTx USART Instance @@ -3370,7 +3395,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) /** * @brief Clear End Of Block Flag - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB * @param USARTx USART Instance @@ -3383,7 +3408,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) /** * @brief Clear SPI Slave Underrun Flag - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR * @param USARTx USART Instance @@ -3407,7 +3432,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) /** * @brief Clear Wake Up from stop mode Flag - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP * @param USARTx USART Instance @@ -3442,7 +3467,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE * @param USARTx USART Instance @@ -3469,7 +3494,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF * @param USARTx USART Instance @@ -3515,7 +3540,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) /** * @brief Enable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB * @param USARTx USART Instance @@ -3528,7 +3553,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) /** * @brief Enable TX FIFO Empty Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE * @param USARTx USART Instance @@ -3552,7 +3577,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) /** * @brief Enable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD * @param USARTx USART Instance @@ -3580,7 +3605,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS * @param USARTx USART Instance @@ -3593,7 +3618,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) /** * @brief Enable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP * @param USARTx USART Instance @@ -3606,7 +3631,7 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) /** * @brief Enable TX FIFO Threshold Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT * @param USARTx USART Instance @@ -3619,7 +3644,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) /** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT * @param USARTx USART Instance @@ -3632,7 +3657,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) /** * @brief Enable RX FIFO Threshold Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT * @param USARTx USART Instance @@ -3659,7 +3684,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE * @param USARTx USART Instance @@ -3686,7 +3711,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF * @param USARTx USART Instance @@ -3732,7 +3757,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) /** * @brief Disable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB * @param USARTx USART Instance @@ -3745,7 +3770,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) /** * @brief Disable TX FIFO Empty Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE * @param USARTx USART Instance @@ -3758,7 +3783,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) /** * @brief Disable RX FIFO Full Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF * @param USARTx USART Instance @@ -3771,7 +3796,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) /** * @brief Disable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD * @param USARTx USART Instance @@ -3799,7 +3824,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS * @param USARTx USART Instance @@ -3812,7 +3837,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) /** * @brief Disable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP * @param USARTx USART Instance @@ -3825,7 +3850,7 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) /** * @brief Disable TX FIFO Threshold Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT * @param USARTx USART Instance @@ -3838,7 +3863,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) /** * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT * @param USARTx USART Instance @@ -3851,7 +3876,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) /** * @brief Disable RX FIFO Threshold Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT * @param USARTx USART Instance @@ -3878,7 +3903,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) /** * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE * @param USARTx USART Instance @@ -3905,7 +3930,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) /** * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF * @param USARTx USART Instance @@ -3951,7 +3976,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) /** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB * @param USARTx USART Instance @@ -3964,7 +3989,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) /** * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE * @param USARTx USART Instance @@ -3977,7 +4002,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) /** * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF * @param USARTx USART Instance @@ -3990,7 +4015,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD * @param USARTx USART Instance @@ -4014,7 +4039,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) /** * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS * @param USARTx USART Instance @@ -4027,7 +4052,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) /** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP * @param USARTx USART Instance @@ -4040,7 +4065,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) /** * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT * @param USARTx USART Instance @@ -4053,7 +4078,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT * @param USARTx USART Instance @@ -4066,7 +4091,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) /** * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT * @param USARTx USART Instance @@ -4196,7 +4221,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx */ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { @@ -4276,7 +4301,7 @@ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Valu /** * @brief Request an Automatic Baud Rate measurement on next received data frame - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate * @param USARTx USART Instance @@ -4311,7 +4336,7 @@ __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) /** * @brief Request a Receive Data and FIFO flush - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @note Allows to discard the received data without reading them, and avoid an overrun * condition. @@ -4326,7 +4351,7 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) /** * @brief Request a Transmit data and FIFO flush - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush * @param USARTx USART Instance diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.c index f2cef5abb83..3611ad27910 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.c @@ -83,7 +83,10 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) { - uint16_t winterruptmask; + uint32_t winterruptmask; + + /* Clear pending interrupts */ + USBx->ISTR = 0U; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | @@ -92,7 +95,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Set interrupt mask */ - USBx->CNTR |= winterruptmask; + USBx->CNTR = (uint16_t)winterruptmask; return HAL_OK; } @@ -102,10 +105,10 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) * Disable the controller's Global Int in the AHB Config reg * @param USBx : Selected device * @retval HAL status -*/ + */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) { - uint16_t winterruptmask; + uint32_t winterruptmask; /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | @@ -114,7 +117,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) USB_CNTR_RESETM | USB_CNTR_L1REQM; /* Clear interrupt mask */ - USBx->CNTR &= ~winterruptmask; + USBx->CNTR &= (uint16_t)(~winterruptmask); return HAL_OK; } @@ -124,7 +127,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) * @param USBx : Selected device * @param mode : current core mode * This parameter can be one of the these values: - * @arg USB_DEVICE_MODE: Peripheral mode mode + * @arg USB_DEVICE_MODE: Peripheral mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) @@ -155,20 +158,17 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) /* Init Device */ /*CNTR_FRES = 1*/ - USBx->CNTR = USB_CNTR_FRES; + USBx->CNTR = (uint16_t)USB_CNTR_FRES; /*CNTR_FRES = 0*/ - USBx->CNTR = 0; + USBx->CNTR = 0U; /*Clear pending interrupts*/ - USBx->ISTR = 0; + USBx->ISTR = 0U; /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; - /* Enable USB Device Interrupt mask */ - (void)USB_EnableGlobalInt(USBx); - return HAL_OK; } @@ -270,7 +270,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) break; } - PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX); + PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); @@ -318,9 +318,6 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - /* Reset value of the data toggle bits for the endpoint out */ - PCD_TX_DTOG(USBx, ep->num); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -329,7 +326,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* Clear the data toggle bits for the endpoint IN/OUT */ PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_RX_DTOG(USBx, ep->num); + if (ep->type != EP_TYPE_ISOC) { @@ -412,6 +409,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { uint16_t pmabuffer; uint32_t len; + uint16_t wEPVal; /* IN endpoint */ if (ep->is_in == 1U) @@ -420,12 +418,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; - ep->xfer_len -= len; } else { len = ep->xfer_len; - ep->xfer_len = 0U; } /* configure and validate Tx endpoint */ @@ -436,49 +432,168 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) } else { - /* Write the data to the USB endpoint */ - if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + /*double buffer bulk management */ + if (ep->type == EP_TYPE_BULK) { - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; - } + if (ep->xfer_len_db > ep->maxpacket) + { + /*enable double buffer */ + PCD_SET_EP_DBUF(USBx, ep->num); + len = ep->maxpacket; + /*each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the two first buffer in the Buffer0 & Buffer1*/ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /*Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0; + } + + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + /*Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + /*Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0; + } + + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + /*Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + } + /*auto Switch to single buffer mode when transfer xfer_len_db; + /*disable double buffer mode */ + PCD_CLEAR_EP_DBUF(USBx, ep->num); + /*Set Tx count with nbre of byte to be transmitted */ + PCD_SET_EP_TX_CNT(USBx, ep->num, len); + pmabuffer = ep->pmaaddr0; + /*Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + }/*end if bulk double buffer */ + + /*mange isochronous double buffer IN mode */ else { - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; + /* Write the data to the USB endpoint */ + if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + } + else + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + } + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); } - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); } PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); } else /* OUT endpoint */ { - /* Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - - /* configure and validate Rx endpoint */ if (ep->doublebuffer == 0U) { + /* Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len -= len; + } + else + { + len = ep->xfer_len; + ep->xfer_len = 0U; + } + /* configure and validate Rx endpoint */ /*Set RX buffer count*/ PCD_SET_EP_RX_CNT(USBx, ep->num, len); } else { + /*First Transfer Coming From HAL_PCD_EP_Receive & From ISR*/ /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + if (ep->type == EP_TYPE_BULK) + { + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + /*Coming from ISR*/ + if (ep->xfer_count != 0U) + { + /* update last value to check if there is blocking state*/ + wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); + /*Blocking State */ + if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || + (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) + { + PCD_FreeUserBuffer(USBx, ep->num, 0U); + } + } + } + /*iso out double */ + else if (ep->type == EP_TYPE_ISOC) + { + /* Multi packet transfer*/ + if (ep->xfer_len > ep->maxpacket) + { + len = ep->maxpacket; + ep->xfer_len -= len; + } + else + { + len = ep->xfer_len; + ep->xfer_len = 0U; + } + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + } + else + { + return HAL_ERROR; + } } PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); @@ -591,13 +706,13 @@ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) { /* disable all interrupts and force USB reset */ - USBx->CNTR = USB_CNTR_FRES; + USBx->CNTR = (uint16_t)USB_CNTR_FRES; /* clear interrupt status register */ - USBx->ISTR = 0; + USBx->ISTR = 0U; /* switch-off device */ - USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); + USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN); return HAL_OK; } @@ -614,7 +729,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) if (address == 0U) { /* set device address and enable function */ - USBx->DADDR = USB_DADDR_EF; + USBx->DADDR = (uint16_t)USB_DADDR_EF; } return HAL_OK; @@ -628,7 +743,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) { /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ - USBx->BCDR |= USB_BCDR_DPPU; + USBx->BCDR |= (uint16_t)USB_BCDR_DPPU; return HAL_OK; } @@ -732,7 +847,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) /** * @brief USB_ClearInterrupts: clear a USB interrupt * @param USBx Selected device - * @param interrupt interrupt flag + * @param interrupt flag * @retval None */ void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt) @@ -771,7 +886,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) { - USBx->CNTR |= USB_CNTR_RESUME; + USBx->CNTR |= (uint16_t)USB_CNTR_RESUME; return HAL_OK; } @@ -783,7 +898,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) { - USBx->CNTR &= ~(USB_CNTR_RESUME); + USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME); return HAL_OK; } @@ -822,7 +937,7 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui } /** - * @brief Copy a buffer from user memory area to packet memory area (PMA) + * @brief Copy data from packet memory area (PMA) to user memory buffer * @param USBx: USB peripheral instance register address. * @param pbUsrBuf pointer to user memory area. * @param wPMABufAddr address into PMA. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.h index 2539da8e88c..2620a8dd471 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.h @@ -118,6 +118,10 @@ typedef struct uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ + + uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ + } USB_EPTypeDef; @@ -131,10 +135,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0U -#define DEP0CTL_MPS_32 1U -#define DEP0CTL_MPS_16 2U -#define DEP0CTL_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -159,10 +163,10 @@ typedef struct * @} */ -#define BTABLE_ADDRESS 0x000U +#define BTABLE_ADDRESS 0x000U #define PMA_ACCESS 1U -#define EP_ADDR_MSK 0x7U +#define EP_ADDR_MSK 0x7U /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_utils.c index ea78949aadc..f6cbb922e46 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_utils.c @@ -142,7 +142,6 @@ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency); static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -268,6 +267,118 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) SystemCoreClock = HCLKFrequency; } +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param HCLKFrequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency) +{ + uint32_t timeout; + uint32_t getlatency; + ErrorStatus status = SUCCESS; + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 or greater than max clock */ + if((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY9_FREQ)) + { + status = ERROR; + } + else + { + if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY8_FREQ) + { + /* 160 < HCLK <= 170 => 8WS (9 CPU cycles) */ + latency = LL_FLASH_LATENCY_8; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY7_FREQ) + { + /* 140 < HCLK <= 160 => 7WS (8 CPU cycles) */ + latency = LL_FLASH_LATENCY_7; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY6_FREQ) + { + /* 120 < HCLK <= 140 => 6WS (7 CPU cycles) */ + latency = LL_FLASH_LATENCY_6; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY5_FREQ) + { + /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ) + { + /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ) + { + /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ) + { + /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + else /* SCALE2 */ + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLKFrequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + + if (status != ERROR) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2U; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0U)); + + if(getlatency != latency) + { + status = ERROR; + } + } + } + + return status; +} + /** * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL * @note The application need to ensure that PLL is disabled. @@ -289,7 +400,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS { ErrorStatus status; uint32_t pllfreq; - uint32_t hpre = 0U; + uint32_t hpre = LL_RCC_SYSCLK_DIV_1; /* Check if one of the PLL is enabled */ if(UTILS_PLL_IsBusy() == SUCCESS) @@ -314,10 +425,10 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } @@ -325,10 +436,16 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if (status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } } else @@ -365,7 +482,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa { ErrorStatus status; uint32_t pllfreq; - uint32_t hpre = 0U; + uint32_t hpre = LL_RCC_SYSCLK_DIV_1; /* Check the parameters */ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); @@ -405,10 +522,10 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */ if(pllfreq > 80000000U) { - hpre = UTILS_ClkInitStruct->AHBCLKDivider; - if(hpre == LL_RCC_SYSCLK_DIV_1) + if (UTILS_ClkInitStruct->AHBCLKDivider == LL_RCC_SYSCLK_DIV_1) { UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2; + hpre = LL_RCC_SYSCLK_DIV_2; } } @@ -416,10 +533,16 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); /* Apply definitive AHB prescaler value if necessary */ - if((status == SUCCESS) && (hpre != 0U)) + if ((status == SUCCESS) && (hpre != LL_RCC_SYSCLK_DIV_1)) { - UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(pllfreq); + if (status == SUCCESS) + { + UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_SetSystemCoreClock(pllfreq); + } } } else @@ -442,103 +565,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa /** @addtogroup UTILS_LL_Private_Functions * @{ */ -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @param HCLK_Frequency HCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) -{ - ErrorStatus status = SUCCESS; - - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - - /* Frequency cannot be equal to 0 */ - if(HCLK_Frequency == 0U) - { - status = ERROR; - } - else - { - if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY8_FREQ) - { - /* 160 < HCLK <= 170 => 8WS (9 CPU cycles) */ - latency = LL_FLASH_LATENCY_8; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ) - { - /* 140 < HCLK <= 160 => 7WS (8 CPU cycles) */ - latency = LL_FLASH_LATENCY_7; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) - { - /* 120 < HCLK <= 140 => 6WS (7 CPU cycles) */ - latency = LL_FLASH_LATENCY_6; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) - { - /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */ - latency = LL_FLASH_LATENCY_5; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) - { - /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) - { - /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) - { - /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) - { - /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - else /* SCALE2 */ - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) - { - /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) - { - /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(LL_FLASH_GetLatency() != latency) - { - status = ERROR; - } - } - return status; -} /** * @brief Function to check that PLL can be modified @@ -617,7 +643,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock < hclk_frequency) { /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update system clock configuration */ @@ -648,7 +674,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock > hclk_frequency) { /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update SystemCoreClock variable */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_utils.h index f8cd1b940a8..5543fcecd90 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_utils.h @@ -288,6 +288,7 @@ void LL_mDelay(uint32_t Delay); */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency); ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_wwdg.h index 11966b8bbfa..6e314363088 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_wwdg.h @@ -326,6 +326,6 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) } #endif -#endif /* __STM32G4xx_LL_WWDG_H */ +#endif /* STM32G4xx_LL_WWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/system_stm32g4xx.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/system_stm32g4xx.c index 8293d3e920e..cb1a0751c75 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/system_stm32g4xx.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/system_stm32g4xx.c @@ -79,7 +79,7 @@ #include "stm32g4xx.h" #if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) @@ -201,7 +201,7 @@ void SystemInit(void) * in voltage and temperature. * * (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * 24 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_ARM_STD/startup_stm32g431xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_ARM/startup_stm32g431xx.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_ARM_STD/startup_stm32g431xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_ARM/startup_stm32g431xx.S index 960f0d8bf67..80fd1743b85 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_ARM_STD/startup_stm32g431xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_ARM/startup_stm32g431xx.S @@ -111,7 +111,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of DCD UART4_IRQHandler ; UART4 DCD 0 ; Reserved DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors - DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors + DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 @@ -273,7 +273,7 @@ Default_Handler PROC EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK] @@ -344,7 +344,7 @@ LPTIM1_IRQHandler SPI3_IRQHandler UART4_IRQHandler TIM6_DAC_IRQHandler -TIM7_DAC_IRQHandler +TIM7_IRQHandler DMA2_Channel1_IRQHandler DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_ARM_STD/stm32g431xx.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_ARM/stm32g431xb.sct similarity index 90% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_ARM_STD/stm32g431xx.sct rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_ARM/stm32g431xb.sct index a27952372d4..331351213d6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_ARM_STD/stm32g431xx.sct +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_ARM/stm32g431xb.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_GCC_ARM/startup_stm32g431xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_GCC_ARM/startup_stm32g431xx.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_GCC_ARM/startup_stm32g431xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_GCC_ARM/startup_stm32g431xx.S index 18b3945c3e4..7093397be47 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_GCC_ARM/startup_stm32g431xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_GCC_ARM/startup_stm32g431xx.S @@ -94,7 +94,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit bl _start bx lr diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_GCC_ARM/stm32g474xx.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_GCC_ARM/stm32g431xb.ld similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_GCC_ARM/stm32g474xx.ld rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_GCC_ARM/stm32g431xb.ld diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_IAR/startup_stm32g431xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_IAR/startup_stm32g431xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_IAR/startup_stm32g431xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_IAR/startup_stm32g431xx.S diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_IAR/stm32g431xx.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_IAR/stm32g431xb.icf similarity index 97% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_IAR/stm32g431xx.icf rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_IAR/stm32g431xb.icf index 1ea8072dd98..988901ff6fd 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_IAR/stm32g431xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/TOOLCHAIN_IAR/stm32g431xb.icf @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/cmsis_nvic.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/cmsis_nvic.h diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431KB/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431KB/PeripheralPins.c deleted file mode 100644 index 25ba6c1b532..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431KB/PeripheralPins.c +++ /dev/null @@ -1,258 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32G431K(6-8-B)Tx.xml - */ - -#include "PeripheralPins.h" -#include "mbed_toolchain.h" - -//============================================================================== -// Notes -// -// - The pins mentioned Px_y_ALTz are alternative possibilities which use other -// HW peripheral instances. You can use them the same way as any other "normal" -// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board -// pinout image on mbed.org. -// -// - The pins which are connected to other components present on the board have -// the comment "Connected to xxx". The pin function may not work properly in this -// case. These pins may not be displayed on the board pinout image on mbed.org. -// Please read the board reference manual and schematic for more information. -// -// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented -// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. -// -//============================================================================== - - -//*** ADC *** - -MBED_WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 -// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX -// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to STDIO_UART_TX - {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 - {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - {PF_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - {PF_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - {NC, NC, 0} -}; - -// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL -MBED_WEAK const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -MBED_WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {NC, NC, 0} -}; - -//*** I2C *** - -MBED_WEAK const PinMap PinMap_I2C_SDA[] = { - {PA_8, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to T_SWCLK - {PB_5, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C3)}, - {PA_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PA_13, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to T_SWDIO - {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [green] - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N -// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_RX -// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 // Connected to STDIO_UART_RX -// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_TX -// {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 // Connected to STDIO_UART_TX - {PA_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 - {PA_9_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 - {PA_10_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N - {PA_11_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 - {PA_11_ALT1, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)}, // TIM4_CH1 - {PA_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N - {PA_12_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)}, // TIM4_CH2 - {PA_12_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PA_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)}, // TIM4_CH3 // Connected to T_SWDIO - {PA_13_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N // Connected to T_SWDIO - {PA_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)}, // TIM8_CH2 // Connected to T_SWCLK - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to T_SWO - {PB_3_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N // Connected to T_SWO - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_4_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N - {PB_4_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_5_ALT1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)}, // TIM8_CH1 - {PB_6_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 - {PB_7_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to LD2 [green] - {PB_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)}, // TIM8_CH2 // Connected to LD2 [green] - {PB_8_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 // Connected to LD2 [green] - {PF_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N - {NC, NC, 0} -}; - -//*** SERIAL *** - -MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_RX - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to T_SWCLK - {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to T_SWO - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_TX - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} -}; - -//*** SPI *** - -MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to T_SWO - {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to T_SWO - {PF_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PF_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -//*** CAN *** - -MBED_WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to LD2 [green] - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NC, 0} -}; - -//*** USBDEVICE *** - -MBED_WEAK const PinMap PinMap_USB_FS[] = { - {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM - {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431KB/PinNames.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431KB/PinNames.h deleted file mode 100644 index e7687ff7838..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431KB/PinNames.h +++ /dev/null @@ -1,79 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32G431K(6-8-B)Tx.xml - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 -} ALTx; - -typedef enum { - - - /**** USB pins ****/ - USB_DM = PA_11, - USB_DP = PA_12, - - /**** OSCILLATOR pins ****/ - RCC_OSC_IN = PF_0, - RCC_OSC_OUT = PF_1, - - /**** DEBUG pins ****/ - SYS_JTCK_SWCLK = PA_14, - SYS_JTDI = PA_15, - SYS_JTDO_SWO = PB_3, - SYS_JTMS_SWDIO = PA_13, - SYS_JTRST = PB_4, - SYS_PVD_IN = PB_7, - SYS_WKUP1 = PA_0, - SYS_WKUP4 = PA_2, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431RB/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431RB/PeripheralPins.c deleted file mode 100644 index e3691e7ac73..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431RB/PeripheralPins.c +++ /dev/null @@ -1,343 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32G431R(6-8-B)Tx.xml - */ - -#include "PeripheralPins.h" -#include "mbed_toolchain.h" - -//============================================================================== -// Notes -// -// - The pins mentioned Px_y_ALTz are alternative possibilities which use other -// HW peripheral instances. You can use them the same way as any other "normal" -// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board -// pinout image on mbed.org. -// -// - The pins which are connected to other components present on the board have -// the comment "Connected to xxx". The pin function may not work properly in this -// case. These pins may not be displayed on the board pinout image on mbed.org. -// Please read the board reference manual and schematic for more information. -// -// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented -// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. -// -//============================================================================== - - -//*** ADC *** - -MBED_WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 -// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX -// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to STDIO_UART_TX - {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 - {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 // Connected to LD2 [green] - {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - {PB_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 - {PB_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 - {PB_11_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 - {PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - {PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 - {PB_15, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 - {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 - {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 - {PC_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - {PC_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 -// {PF_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to RCC_OSC_IN -// {PF_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to RCC_OSC_OUT - {NC, NC, 0} -}; - -// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL -MBED_WEAK const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -MBED_WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // Connected to LD2 [green] - {NC, NC, 0} -}; - -//*** I2C *** - -MBED_WEAK const PinMap PinMap_I2C_SDA[] = { - {PA_8, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to T_SWCLK - {PB_5, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, - {PC_11, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, -// {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to RCC_OSC_IN - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C3)}, - {PA_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PA_13, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to T_SWDIO - {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PC_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {PC_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N -// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_RX -// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 // Connected to STDIO_UART_RX -// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_TX -// {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 // Connected to STDIO_UART_TX - {PA_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to LD2 [green] - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N - {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N - {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 - {PA_9_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 - {PA_10_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N - {PA_11_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 - {PA_11_ALT1, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)}, // TIM4_CH1 - {PA_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N - {PA_12_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)}, // TIM4_CH2 - {PA_12_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PA_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)}, // TIM4_CH3 // Connected to T_SWDIO - {PA_13_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N // Connected to T_SWDIO - {PA_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)}, // TIM8_CH2 // Connected to T_SWCLK - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N - {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to T_SWO - {PB_3_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N // Connected to T_SWO - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_4_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N - {PB_4_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - {PB_5_ALT1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - {PB_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)}, // TIM8_CH1 - {PB_6_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 - {PB_7_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - {PB_7_ALT1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)}, // TIM8_CH2 - {PB_8_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM1_COMP1, 3, 1)}, // TIM1_CH3N - {PB_9_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 3, 0)}, // TIM8_CH3 - {PB_9_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N - {PB_14_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 1, 0)}, // TIM15_CH1 - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 3, 1)}, // TIM1_CH3N - {PB_15_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N - {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 2, 0)}, // TIM15_CH2 - {PC_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 - {PC_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 - {PC_2, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 - {PC_3, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 - {PC_5, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 4, 1)}, // TIM1_CH4N - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 0)}, // TIM8_CH1 - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 0)}, // TIM8_CH2 - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 0)}, // TIM8_CH3 - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 4, 0)}, // TIM8_CH4 - {PC_10, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N - {PC_11, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N - {PC_12, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N - {PC_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 1, 1)}, // TIM1_CH1N // Connected to B1 [blue push button] - {PC_13_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM8, 4, 1)}, // TIM8_CH4N // Connected to B1 [blue push button] -// {PF_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N // Connected to RCC_OSC_IN - {NC, NC, 0} -}; - -//*** SERIAL *** - -MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_RX - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to T_SWCLK - {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to T_SWO - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_TX - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_5, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to T_SWDIO - {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART4)}, - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {NC, NC, 0} -}; - -//*** SPI *** - -MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD2 [green] - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to T_SWO - {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to T_SWO - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, -// {PF_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to RCC_OSC_OUT - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, -// {PF_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to RCC_OSC_IN - {NC, NC, 0} -}; - -//*** CAN *** - -MBED_WEAK const PinMap PinMap_CAN_RD[] = { - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {NC, NC, 0} -}; - -//*** USBDEVICE *** - -MBED_WEAK const PinMap PinMap_USB_FS[] = { - {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM - {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431RB/PinNames.h deleted file mode 100644 index bde8bb4a2a0..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TARGET_NUCLEO_G431RB/PinNames.h +++ /dev/null @@ -1,83 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32G431R(6-8-B)Tx.xml - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 -} ALTx; - -typedef enum { - - - /**** USB pins ****/ - USB_DM = PA_11, - USB_DP = PA_12, - - /**** OSCILLATOR pins ****/ - RCC_OSC32_IN = PC_14, - RCC_OSC32_OUT = PC_15, - RCC_OSC_IN = PF_0, - RCC_OSC_OUT = PF_1, - - /**** DEBUG pins ****/ - SYS_JTCK_SWCLK = PA_14, - SYS_JTDI = PA_15, - SYS_JTDO_SWO = PB_3, - SYS_JTMS_SWDIO = PA_13, - SYS_JTRST = PB_4, - SYS_PVD_IN = PB_7, - SYS_WKUP1 = PA_0, - SYS_WKUP2 = PC_13, - SYS_WKUP4 = PA_2, - SYS_WKUP5 = PC_5, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_ARM_STD/startup_stm32g441xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_ARM/startup_stm32g441xx.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_ARM_STD/startup_stm32g441xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_ARM/startup_stm32g441xx.S index 86f76d56373..10f8c1fb25f 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_ARM_STD/startup_stm32g441xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_ARM/startup_stm32g441xx.S @@ -111,7 +111,7 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of DCD UART4_IRQHandler ; UART4 DCD 0 ; Reserved DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors - DCD TIM7_DAC_IRQHandler ; TIM7 and DAC2&4 underrun errors + DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 @@ -273,7 +273,7 @@ Default_Handler PROC EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Channel1_IRQHandler [WEAK] EXPORT DMA2_Channel2_IRQHandler [WEAK] EXPORT DMA2_Channel3_IRQHandler [WEAK] @@ -345,7 +345,7 @@ LPTIM1_IRQHandler SPI3_IRQHandler UART4_IRQHandler TIM6_DAC_IRQHandler -TIM7_DAC_IRQHandler +TIM7_IRQHandler DMA2_Channel1_IRQHandler DMA2_Channel2_IRQHandler DMA2_Channel3_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_ARM_STD/stm32g441xx.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_ARM/stm32g441xb.sct similarity index 90% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_ARM_STD/stm32g441xx.sct rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_ARM/stm32g441xb.sct index a27952372d4..331351213d6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_ARM_STD/stm32g441xx.sct +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_ARM/stm32g441xb.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_GCC_ARM/startup_stm32g441xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_GCC_ARM/startup_stm32g441xx.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_GCC_ARM/startup_stm32g441xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_GCC_ARM/startup_stm32g441xx.S index 4ec3534b677..21e9bb7a5d7 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_GCC_ARM/startup_stm32g441xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_GCC_ARM/startup_stm32g441xx.S @@ -94,7 +94,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit bl _start bx lr diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_GCC_ARM/stm32g431xx.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_GCC_ARM/stm32g441xb.ld similarity index 95% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_GCC_ARM/stm32g431xx.ld rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_GCC_ARM/stm32g441xb.ld index 0a93b7b56bf..5f479936c85 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/TOOLCHAIN_GCC_ARM/stm32g431xx.ld +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_GCC_ARM/stm32g441xb.ld @@ -111,10 +111,7 @@ SECTIONS } > FLASH __exidx_end = .; - /* Location counter can end up 2byte aligned with narrow Thumb code but - __etext is assumed by startup code to be the LMA of a section in RAM - which must be 8-byte aligned */ - __etext = ALIGN (8); + __etext = .; _sidata = .; .data : AT (__etext) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_IAR/startup_stm32g441xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_IAR/startup_stm32g441xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_IAR/startup_stm32g441xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_IAR/startup_stm32g441xx.S diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_IAR/stm32g441xx.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_IAR/stm32g441xb.icf similarity index 97% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_IAR/stm32g441xx.icf rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_IAR/stm32g441xb.icf index 1ea8072dd98..988901ff6fd 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_IAR/stm32g441xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/TOOLCHAIN_IAR/stm32g441xb.icf @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/cmsis_nvic.h similarity index 71% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/cmsis_nvic.h index 672abbeffbc..308d0de2f21 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xB/cmsis_nvic.h @@ -23,10 +23,6 @@ #if !defined(MBED_ROM_SIZE) #define MBED_ROM_SIZE 0x20000 // 128 KB - // 0x8000 STM32G431M6Tx STM32G431K6Tx STM32G431C6Ux STM32G431R6Tx STM32G431V6Tx STM32G431K6Ux STM32G431C6Tx STM32G431R6Ix - // 0x20000 STM32G431KBTx STM32G431CBTx STM32G431RBIx STM32G431CBYx STM32G431KBUx STM32G431VBTx STM32G431CBUx STM32G431RBTx - // 0x10000 STM32G431V8Tx STM32G431R8Tx STM32G431K8Tx STM32G431C8Tx STM32G431R8Ix STM32G431C8Ux STM32G431K8Ux STM32G431M8Tx -#warning "check MBED_ROM_SIZE value in cmsis_nvic.h" #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_ARM_STD/startup_stm32g471xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_ARM/startup_stm32g471xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_ARM_STD/startup_stm32g471xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_ARM/startup_stm32g471xx.S diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_ARM_STD/stm32g471xx.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_ARM/stm32g471xe.sct similarity index 90% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_ARM_STD/stm32g471xx.sct rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_ARM/stm32g471xe.sct index a27952372d4..331351213d6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_ARM_STD/stm32g471xx.sct +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_ARM/stm32g471xe.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_GCC_ARM/startup_stm32g471xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_GCC_ARM/startup_stm32g471xx.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_GCC_ARM/startup_stm32g471xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_GCC_ARM/startup_stm32g471xx.S index dbc0c02a798..5954da28897 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_GCC_ARM/startup_stm32g471xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_GCC_ARM/startup_stm32g471xx.S @@ -94,7 +94,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit bl _start bx lr diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_GCC_ARM/stm32g441xx.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_GCC_ARM/stm32g471xe.ld similarity index 95% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_GCC_ARM/stm32g441xx.ld rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_GCC_ARM/stm32g471xe.ld index 0a93b7b56bf..5f479936c85 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G441xx/TOOLCHAIN_GCC_ARM/stm32g441xx.ld +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_GCC_ARM/stm32g471xe.ld @@ -111,10 +111,7 @@ SECTIONS } > FLASH __exidx_end = .; - /* Location counter can end up 2byte aligned with narrow Thumb code but - __etext is assumed by startup code to be the LMA of a section in RAM - which must be 8-byte aligned */ - __etext = ALIGN (8); + __etext = .; _sidata = .; .data : AT (__etext) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_IAR/startup_stm32g471xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_IAR/startup_stm32g471xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_IAR/startup_stm32g471xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_IAR/startup_stm32g471xx.S diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_IAR/stm32g473xx.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_IAR/stm32g471xe.icf similarity index 97% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_IAR/stm32g473xx.icf rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_IAR/stm32g471xe.icf index 64170e81d13..d3bf9e3cd3a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_IAR/stm32g473xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/TOOLCHAIN_IAR/stm32g471xe.icf @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/cmsis_nvic.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xE/cmsis_nvic.h diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_ARM_STD/startup_stm32g473xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_ARM/startup_stm32g473xx.S similarity index 95% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_ARM_STD/startup_stm32g473xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_ARM/startup_stm32g473xx.S index b4324affd5a..571662764f8 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_ARM_STD/startup_stm32g473xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_ARM/startup_stm32g473xx.S @@ -77,8 +77,8 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of DCD ADC1_2_IRQHandler ; ADC1 and ADC2 DCD USB_HP_IRQHandler ; USB Device High Priority DCD USB_LP_IRQHandler ; USB Device Low Priority - DCD 0 ; Reserved - DCD 0 ; Reserved + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 @@ -142,10 +142,10 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of DCD I2C4_ER_IRQHandler ; I2C4 error DCD SPI4_IRQHandler ; SPI4 DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 DCD RNG_IRQHandler ; RNG global interrupt DCD LPUART1_IRQHandler ; LP UART 1 interrupt DCD I2C3_EV_IRQHandler ; I2C3 Event @@ -244,6 +244,8 @@ Default_Handler PROC EXPORT ADC1_2_IRQHandler [WEAK] EXPORT USB_HP_IRQHandler [WEAK] EXPORT USB_LP_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] @@ -298,6 +300,10 @@ Default_Handler PROC EXPORT I2C4_EV_IRQHandler [WEAK] EXPORT I2C4_ER_IRQHandler [WEAK] EXPORT SPI4_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT FDCAN3_IT0_IRQHandler [WEAK] + EXPORT FDCAN3_IT1_IRQHandler [WEAK] EXPORT RNG_IRQHandler [WEAK] EXPORT LPUART1_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] @@ -332,6 +338,8 @@ DMA1_Channel7_IRQHandler ADC1_2_IRQHandler USB_HP_IRQHandler USB_LP_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN1_IT1_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM15_IRQHandler TIM1_UP_TIM16_IRQHandler @@ -386,6 +394,10 @@ FPU_IRQHandler I2C4_EV_IRQHandler I2C4_ER_IRQHandler SPI4_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN2_IT1_IRQHandler +FDCAN3_IT0_IRQHandler +FDCAN3_IT1_IRQHandler RNG_IRQHandler LPUART1_IRQHandler I2C3_EV_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_ARM_STD/stm32g473xx.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_ARM/stm32g473xe.sct similarity index 90% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_ARM_STD/stm32g473xx.sct rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_ARM/stm32g473xe.sct index a27952372d4..331351213d6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_ARM_STD/stm32g473xx.sct +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_ARM/stm32g473xe.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_GCC_ARM/startup_stm32g473xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_GCC_ARM/startup_stm32g473xx.S similarity index 95% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_GCC_ARM/startup_stm32g473xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_GCC_ARM/startup_stm32g473xx.S index 2fe3b3fa423..89b34cd38b9 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_GCC_ARM/startup_stm32g473xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_GCC_ARM/startup_stm32g473xx.S @@ -94,7 +94,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit bl _start bx lr @@ -167,8 +167,8 @@ g_pfnVectors: .word ADC1_2_IRQHandler .word USB_HP_IRQHandler .word USB_LP_IRQHandler - .word 0 - .word 0 + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler .word EXTI9_5_IRQHandler .word TIM1_BRK_TIM15_IRQHandler .word TIM1_UP_TIM16_IRQHandler @@ -232,10 +232,10 @@ g_pfnVectors: .word I2C4_ER_IRQHandler .word SPI4_IRQHandler .word 0 - .word 0 - .word 0 - .word 0 - .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word FDCAN3_IT0_IRQHandler + .word FDCAN3_IT1_IRQHandler .word RNG_IRQHandler .word LPUART1_IRQHandler .word I2C3_EV_IRQHandler @@ -347,6 +347,12 @@ g_pfnVectors: .weak USB_LP_IRQHandler .thumb_set USB_LP_IRQHandler,Default_Handler + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler @@ -509,6 +515,18 @@ g_pfnVectors: .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + .weak RNG_IRQHandler .thumb_set RNG_IRQHandler,Default_Handler diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_GCC_ARM/stm32g471xx.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_GCC_ARM/stm32g473xe.ld similarity index 95% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_GCC_ARM/stm32g471xx.ld rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_GCC_ARM/stm32g473xe.ld index 0a93b7b56bf..5f479936c85 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_GCC_ARM/stm32g471xx.ld +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_GCC_ARM/stm32g473xe.ld @@ -111,10 +111,7 @@ SECTIONS } > FLASH __exidx_end = .; - /* Location counter can end up 2byte aligned with narrow Thumb code but - __etext is assumed by startup code to be the LMA of a section in RAM - which must be 8-byte aligned */ - __etext = ALIGN (8); + __etext = .; _sidata = .; .data : AT (__etext) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_IAR/startup_stm32g473xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_IAR/startup_stm32g473xx.S similarity index 94% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_IAR/startup_stm32g473xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_IAR/startup_stm32g473xx.S index 1ddbd420275..7340942088f 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_IAR/startup_stm32g473xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_IAR/startup_stm32g473xx.S @@ -94,8 +94,8 @@ __vector_table DCD ADC1_2_IRQHandler ; ADC1 and ADC2 DCD USB_HP_IRQHandler ; USB Device High Priority DCD USB_LP_IRQHandler ; USB Device Low Priority - DCD 0 ; Reserved - DCD 0 ; Reserved + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 @@ -159,10 +159,10 @@ __vector_table DCD I2C4_ER_IRQHandler ; I2C4 error DCD SPI4_IRQHandler ; SPI4 DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 DCD RNG_IRQHandler ; RNG global interrupt DCD LPUART1_IRQHandler ; LP UART 1 interrupt DCD I2C3_EV_IRQHandler ; I2C3 Event @@ -339,6 +339,16 @@ USB_HP_IRQHandler USB_LP_IRQHandler B USB_LP_IRQHandler + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + PUBWEAK EXTI9_5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) EXTI9_5_IRQHandler @@ -609,6 +619,26 @@ I2C4_ER_IRQHandler SPI4_IRQHandler B SPI4_IRQHandler + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler + B FDCAN3_IT0_IRQHandler + + PUBWEAK FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler + B FDCAN3_IT1_IRQHandler + PUBWEAK RNG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) RNG_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_IAR/stm32g471xx.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_IAR/stm32g473xe.icf similarity index 97% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_IAR/stm32g471xx.icf rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_IAR/stm32g473xe.icf index 64170e81d13..d3bf9e3cd3a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/TOOLCHAIN_IAR/stm32g471xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/TOOLCHAIN_IAR/stm32g473xe.icf @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/cmsis_nvic.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xE/cmsis_nvic.h diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/PeripheralPins.c rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PinNames.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/PinNames.h rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PinNames.h diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_ARM_STD/startup_stm32g474xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_ARM/startup_stm32g474xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_ARM_STD/startup_stm32g474xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_ARM/startup_stm32g474xx.S diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_ARM/stm32g474xe.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_ARM/stm32g474xe.sct new file mode 100644 index 00000000000..331351213d6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_ARM/stm32g474xe.sct @@ -0,0 +1,57 @@ +#! armcc -E +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_GCC_ARM/startup_stm32g474xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_GCC_ARM/startup_stm32g474xx.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_GCC_ARM/startup_stm32g474xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_GCC_ARM/startup_stm32g474xx.S index 6a6f09e04a0..924c7fb98a0 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_GCC_ARM/startup_stm32g474xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_GCC_ARM/startup_stm32g474xx.S @@ -94,7 +94,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit bl _start bx lr diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_GCC_ARM/stm32g473xx.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_GCC_ARM/stm32g474xe.ld similarity index 95% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_GCC_ARM/stm32g473xx.ld rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_GCC_ARM/stm32g474xe.ld index 0a93b7b56bf..5f479936c85 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/TOOLCHAIN_GCC_ARM/stm32g473xx.ld +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_GCC_ARM/stm32g474xe.ld @@ -111,10 +111,7 @@ SECTIONS } > FLASH __exidx_end = .; - /* Location counter can end up 2byte aligned with narrow Thumb code but - __etext is assumed by startup code to be the LMA of a section in RAM - which must be 8-byte aligned */ - __etext = ALIGN (8); + __etext = .; _sidata = .; .data : AT (__etext) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_IAR/startup_stm32g474xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_IAR/startup_stm32g474xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_IAR/startup_stm32g474xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_IAR/startup_stm32g474xx.S diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_IAR/stm32g474xx.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_IAR/stm32g474xe.icf similarity index 97% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_IAR/stm32g474xx.icf rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_IAR/stm32g474xe.icf index 64170e81d13..d3bf9e3cd3a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_IAR/stm32g474xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TOOLCHAIN_IAR/stm32g474xe.icf @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/cmsis_nvic.h similarity index 77% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/cmsis_nvic.h index afd9918b844..6bbb29dd081 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G471xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/cmsis_nvic.h @@ -23,9 +23,6 @@ #if !defined(MBED_ROM_SIZE) #define MBED_ROM_SIZE 0x80000 // 512 KB - // 0x40000 STM32G471RCTx STM32G471CCUx STM32G471VCHx STM32G471CCTx STM32G471VCIx STM32G471VCTx STM32G471MCTx STM32G471QCTx - // 0x80000 STM32G471RE STM32G471VETx STM32G471METx STM32G471VEHx STM32G471CEUx STM32G471QETx STM32G471MEYx STM32G471VEIx STM32G471CETx -#warning "check MBED_ROM_SIZE value in cmsis_nvic.h" #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/system_clock.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_NUCLEO_G474RE/system_clock.c rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_DISCO_G474RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_DISCO_G474RE/PeripheralPins.c deleted file mode 100644 index e322afad902..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_DISCO_G474RE/PeripheralPins.c +++ /dev/null @@ -1,411 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32G474R(B-C-E)Tx.xml - */ - -#include "PeripheralPins.h" -#include "mbed_toolchain.h" - -//============================================================================== -// Notes -// -// - The pins mentioned Px_y_ALTz are alternative possibilities which use other -// HW peripheral instances. You can use them the same way as any other "normal" -// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board -// pinout image on mbed.org. -// -// - The pins which are connected to other components present on the board have -// the comment "Connected to xxx". The pin function may not work properly in this -// case. These pins may not be displayed on the board pinout image on mbed.org. -// Please read the board reference manual and schematic for more information. -// -// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented -// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. -// -//============================================================================== - - -//*** ADC *** - -MBED_WEAK const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to BUCK_GREEN_SENSE - {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to BUCK_GREEN_SENSE - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to BUCKBOOST_VIN - {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to BUCKBOOST_VIN - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to BUCKBOOST_I_IN_AVG - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to BUCKBOOST_VOUT - {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 - {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // Connected to BUCK_RED_SENSE - {PA_8, ADC_5, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC5_IN1 // Connected to BUCK_BLUE_DRIVE - {PA_9, ADC_5, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC5_IN2 // Connected to UCPD1_DBCC1 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to BUCK_BLUE_SENSE - {PB_0_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 // Connected to BUCK_BLUE_SENSE - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Connected to LD3 [Orange Led] - {PB_1_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to LD3 [Orange Led] - {PB_2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // Connected to JOYSTICK_RIGHT - {PB_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to BUCKBOOST_I_IN_SENSE - {PB_11_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to BUCKBOOST_I_IN_SENSE - {PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to BUCKBOOST_P1_DRIVE - {PB_12_ALT0, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 // Connected to BUCKBOOST_P1_DRIVE - {PB_13, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 // Connected to BUCKBOOST_N1_DRIVE - {PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to BUCKBOOST_N2_DRIVE - {PB_14_ALT0, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 // Connected to BUCKBOOST_N2_DRIVE - {PB_15, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to BUCKBOOST_P2_DRIVE - {PB_15_ALT0, ADC_4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC4_IN5 // Connected to BUCKBOOST_P2_DRIVE - {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 - {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to USBPD_VIN - {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to USBPD_VIN - {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // Connected to BUCKBOOST_USBPD_EN - {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 // Connected to BUCKBOOST_USBPD_EN - {PC_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // Connected to JOYSTICK_LEFT - {PC_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to JOYSTICK_DOWN - {PF_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - {PF_1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - {NC, NC, 0} -}; - -// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL -MBED_WEAK const PinMap PinMap_ADC_Internal[] = { - {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, - {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, - {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, - {NC, NC, 0} -}; - -//*** DAC *** - -MBED_WEAK const PinMap PinMap_DAC[] = { - {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - {PA_6, DAC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC2_OUT1 - {NC, NC, 0} -}; - -//*** I2C *** - -MBED_WEAK const PinMap PinMap_I2C_SDA[] = { - {PA_8, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to BUCK_BLUE_DRIVE - {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to SYS_JTCK-SWCLK - {PB_5, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, // Connected to LD5 [Red Led] - {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD4 [Green Led] - {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, // Connected to LD4 [Green Led] - {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PC_7, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C4)}, // Connected to RC_TP4 - {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, -// {PC_11, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, // Connected to STDIO_UART_RX - {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_I2C_SCL[] = { - {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C3)}, // Connected to BUCK_BLUE_DRIVE - {PA_9, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to UCPD1_DBCC1 - {PA_13, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to SYS_JTMS-SWDIO - {PA_13_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, // Connected to SYS_JTMS-SWDIO - {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue Led] - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {PC_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to JOYSTICK_LEFT - {PC_6, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C4)}, // Connected to BUCK_RED_DRIVE - {PC_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C3)}, // Connected to BUCK_GREEN_DRIVE - {NC, NC, 0} -}; - -//*** PWM *** - -// TIM5 cannot be used because already used by the us_ticker -MBED_WEAK const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to BUCK_GREEN_SENSE -// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to BUCK_GREEN_SENSE - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to BUCKBOOST_VIN -// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to BUCKBOOST_VIN - {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N // Connected to BUCKBOOST_VIN - {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to BUCKBOOST_I_IN_AVG -// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to BUCKBOOST_I_IN_AVG - {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 // Connected to BUCKBOOST_I_IN_AVG - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to BUCKBOOST_VOUT -// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to BUCKBOOST_VOUT - {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 // Connected to BUCKBOOST_VOUT - {PA_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N // Connected to BUCK_RED_SENSE - {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to BUCK_RED_SENSE - {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N // Connected to BUCK_RED_SENSE - {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 // Connected to BUCK_RED_SENSE - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 // Connected to BUCK_BLUE_DRIVE - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 // Connected to UCPD1_DBCC1 - {PA_9_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 // Connected to UCPD1_DBCC1 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 // Connected to UCPD1_DBCC2 - {PA_10_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 // Connected to UCPD1_DBCC2 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N // Connected to USB_DM - {PA_11_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM - {PA_11_ALT1, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 1, 0)}, // TIM4_CH1 // Connected to USB_DM - {PA_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N // Connected to USB_DP - {PA_12_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 2, 0)}, // TIM4_CH2 // Connected to USB_DP - {PA_12_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 // Connected to USB_DP - {PA_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM4, 3, 0)}, // TIM4_CH3 // Connected to SYS_JTMS-SWDIO - {PA_13_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N // Connected to SYS_JTMS-SWDIO - {PA_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 2, 0)}, // TIM8_CH2 // Connected to SYS_JTCK-SWCLK - {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to LD2 [Blue Led] - {PA_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM8, 1, 0)}, // TIM8_CH1 // Connected to LD2 [Blue Led] - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N // Connected to BUCK_BLUE_SENSE - {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to BUCK_BLUE_SENSE - {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N // Connected to BUCK_BLUE_SENSE - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N // Connected to LD3 [Orange Led] - {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to LD3 [Orange Led] - {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N // Connected to LD3 [Orange Led] -// {PB_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to JOYSTICK_RIGHT - {PB_2, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM20, 1, 0)}, // TIM20_CH1 // Connected to JOYSTICK_RIGHT - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SYS_JTDO-SWO - {PB_3_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N // Connected to SYS_JTDO-SWO - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to UCPD1_CC2 - {PB_4_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N // Connected to UCPD1_CC2 - {PB_4_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 // Connected to UCPD1_CC2 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to LD5 [Red Led] - {PB_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to LD5 [Red Led] - {PB_5_ALT1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)}, // TIM17_CH1 // Connected to LD5 [Red Led] - {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to UCPD1_CC1 - {PB_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM8, 1, 0)}, // TIM8_CH1 // Connected to UCPD1_CC1 - {PB_6_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N // Connected to UCPD1_CC1 - {PB_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 // Connected to LD4 [Green Led] - {PB_7_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD4 [Green Led] - {PB_7_ALT1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N // Connected to LD4 [Green Led] - {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - {PB_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 2, 0)}, // TIM8_CH2 - {PB_8_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 - {PB_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM1_COMP1, 3, 1)}, // TIM1_CH3N - {PB_9_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - {PB_9_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM8, 3, 0)}, // TIM8_CH3 - {PB_9_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 - {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to JOYSTICK_UP - {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to BUCKBOOST_I_IN_SENSE - {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N // Connected to BUCKBOOST_N1_DRIVE - {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N // Connected to BUCKBOOST_N2_DRIVE - {PB_14_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 1, 0)}, // TIM15_CH1 // Connected to BUCKBOOST_N2_DRIVE - {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 3, 1)}, // TIM1_CH3N // Connected to BUCKBOOST_P2_DRIVE - {PB_15_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N // Connected to BUCKBOOST_P2_DRIVE - {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM15, 2, 0)}, // TIM15_CH2 // Connected to BUCKBOOST_P2_DRIVE - {PC_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 - {PC_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 - {PC_2, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USBPD_VIN - {PC_2_ALT0, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 2, 0)}, // TIM20_CH2 // Connected to USBPD_VIN - {PC_3, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 // Connected to BUCKBOOST_USBPD_EN - {PC_5, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 4, 1)}, // TIM1_CH4N // Connected to JOYSTICK_DOWN - {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to BUCK_RED_DRIVE - {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 0)}, // TIM8_CH1 // Connected to BUCK_RED_DRIVE - {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to RC_TP4 - {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 0)}, // TIM8_CH2 // Connected to RC_TP4 - {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to BUCK_GREEN_DRIVE - {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 0)}, // TIM8_CH3 // Connected to BUCK_GREEN_DRIVE - {PC_8_ALT1, PWM_20, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM20, 3, 0)}, // TIM20_CH3 // Connected to BUCK_GREEN_DRIVE - {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 4, 0)}, // TIM8_CH4 -// {PC_10, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 1, 1)}, // TIM8_CH1N // Connected to STDIO_UART_TX -// {PC_11, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 2, 1)}, // TIM8_CH2N // Connected to STDIO_UART_RX -// {PC_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM5, 2, 0)}, // TIM5_CH2 // Connected to USBPD_1A_PROTECT - {PC_12, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM8, 3, 1)}, // TIM8_CH3N // Connected to USBPD_1A_PROTECT - {PC_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM1, 1, 1)}, // TIM1_CH1N // Connected to JOYSTICK_SEL - {PC_13_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM8, 4, 1)}, // TIM8_CH4N // Connected to JOYSTICK_SEL - {PF_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N - {NC, NC, 0} -}; - -//*** SERIAL *** - -MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to BUCKBOOST_I_IN_AVG - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to BUCKBOOST_I_IN_AVG - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to UCPD1_DBCC1 - {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to SYS_JTCK-SWCLK - {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to SYS_JTDO-SWO - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to UCPD1_CC1 - {PB_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to JOYSTICK_UP - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to BUCKBOOST_I_IN_SENSE - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to JOYSTICK_LEFT - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX - {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, // Connected to STDIO_UART_TX - {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)}, // Connected to USBPD_1A_PROTECT - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to BUCKBOOST_VOUT - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to BUCKBOOST_VOUT - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to UCPD1_DBCC2 - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to LD2 [Blue Led] - {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to UCPD1_CC2 - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD4 [Green Led] - {PB_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to JOYSTICK_UP - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to BUCKBOOST_I_IN_SENSE - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_5, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to JOYSTICK_DOWN - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX - {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, // Connected to STDIO_UART_RX - {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART5)}, // Connected to USBPD_550mA_PROTECT - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to BUCKBOOST_VIN - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP - {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD2 [Blue Led] - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to LD3 [Orange Led] - {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to UCPD1_CC2 - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to BUCKBOOST_P1_DRIVE - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to BUCKBOOST_N2_DRIVE - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to BUCK_GREEN_SENSE - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM - {PA_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SYS_JTMS-SWDIO - {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to LD5 [Red Led] - {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART4)}, // Connected to LD4 [Green Led] - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to BUCKBOOST_N1_DRIVE - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to BUCKBOOST_N1_DRIVE - {NC, NC, 0} -}; - -//*** SPI *** - -MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to BUCK_RED_SENSE - {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_DM - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD5 [Red Led] - {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to LD5 [Red Led] - {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to BUCKBOOST_P2_DRIVE - {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to USBPD_1A_PROTECT - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to UCPD1_DBCC2 - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to UCPD1_CC2 - {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to UCPD1_CC2 - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to BUCKBOOST_N2_DRIVE -// {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to STDIO_UART_RX - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SYS_JTDO-SWO - {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SYS_JTDO-SWO - {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to BUCKBOOST_N1_DRIVE -// {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to STDIO_UART_TX - {PF_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { - {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD2 [Blue Led] - {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to LD2 [Blue Led] - {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to BUCKBOOST_P1_DRIVE - {PF_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - {NC, NC, 0} -}; - -//*** CAN *** - -MBED_WEAK const PinMap PinMap_CAN_RD[] = { - {PA_8, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_FDCAN3)}, // Connected to BUCK_BLUE_DRIVE - {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to USB_DM - {PB_3, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_FDCAN3)}, // Connected to SYS_JTDO-SWO - {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to LD5 [Red Led] - {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to BUCKBOOST_P1_DRIVE - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to USB_DP - {PA_15, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_FDCAN3)}, // Connected to LD2 [Blue Led] - {PB_4, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_FDCAN3)}, // Connected to UCPD1_CC2 - {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to UCPD1_CC1 - {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, - {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to BUCKBOOST_N1_DRIVE - {NC, NC, 0} -}; - -//*** QUADSPI *** - -MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { - {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_IO0 // Connected to LD3 [Orange Led] - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { - {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_IO1 // Connected to BUCK_BLUE_SENSE - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { - {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_IO2 // Connected to BUCK_RED_SENSE - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { - {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_IO3 - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { - {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_CLK // Connected to BUCKBOOST_VOUT - {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_CLK // Connected to JOYSTICK_UP - {NC, NC, 0} -}; - -MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { - {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_NCS // Connected to BUCKBOOST_I_IN_AVG - {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI1_BK1_NCS // Connected to BUCKBOOST_I_IN_SENSE - {NC, NC, 0} -}; - -//*** USBDEVICE *** - -MBED_WEAK const PinMap PinMap_USB_FS[] = { - {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM // Connected to USB_DM - {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP // Connected to USB_DP - {NC, NC, 0} -}; diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_DISCO_G474RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_DISCO_G474RE/PinNames.h deleted file mode 100644 index 4d36896fab9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TARGET_DISCO_G474RE/PinNames.h +++ /dev/null @@ -1,83 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32G474R(B-C-E)Tx.xml - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" -#include "PinNamesTypes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ALT0 = 0x100, - ALT1 = 0x200, - ALT2 = 0x300, - ALT3 = 0x400 -} ALTx; - -typedef enum { - - - /**** USB pins ****/ - USB_DM = PA_11, - USB_DP = PA_12, - - /**** OSCILLATOR pins ****/ - RCC_OSC32_IN = PC_14, - RCC_OSC32_OUT = PC_15, - RCC_OSC_IN = PF_0, - RCC_OSC_OUT = PF_1, - - /**** DEBUG pins ****/ - SYS_JTCK_SWCLK = PA_14, - SYS_JTDI = PA_15, - SYS_JTDO_SWO = PB_3, - SYS_JTMS_SWDIO = PA_13, - SYS_JTRST = PB_4, - SYS_PVD_IN = PB_7, - SYS_WKUP1 = PA_0, - SYS_WKUP2 = PC_13, - SYS_WKUP4 = PA_2, - SYS_WKUP5 = PC_5, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_ARM_STD/stm32g474xx.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_ARM_STD/stm32g474xx.sct deleted file mode 100644 index a27952372d4..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/TOOLCHAIN_ARM_STD/stm32g474xx.sct +++ /dev/null @@ -1,57 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -; -; SPDX-License-Identifier: BSD-3-Clause -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2016-2020 STMicroelectronics. -;* All rights reserved. -;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause -;* -;****************************************************************************** - -#include "../cmsis_nvic.h" - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up - } - - ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down - } -} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_ARM_STD/startup_stm32g483xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_ARM/startup_stm32g483xx.S similarity index 95% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_ARM_STD/startup_stm32g483xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_ARM/startup_stm32g483xx.S index ceaae6e778c..722dde1fbdd 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_ARM_STD/startup_stm32g483xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_ARM/startup_stm32g483xx.S @@ -141,11 +141,11 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of DCD I2C4_EV_IRQHandler ; I2C4 event DCD I2C4_ER_IRQHandler ; I2C4 error DCD SPI4_IRQHandler ; SPI4 - DCD AES_IRQHandler ; AES global interrupt DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved + DCD AES_IRQHandler ; AES global interrupt + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 DCD RNG_IRQHandler ; RNG global interrupt DCD LPUART1_IRQHandler ; LP UART 1 interrupt DCD I2C3_EV_IRQHandler ; I2C3 Event @@ -244,6 +244,8 @@ Default_Handler PROC EXPORT ADC1_2_IRQHandler [WEAK] EXPORT USB_HP_IRQHandler [WEAK] EXPORT USB_LP_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] @@ -299,6 +301,10 @@ Default_Handler PROC EXPORT I2C4_ER_IRQHandler [WEAK] EXPORT SPI4_IRQHandler [WEAK] EXPORT AES_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT FDCAN3_IT0_IRQHandler [WEAK] + EXPORT FDCAN3_IT1_IRQHandler [WEAK] EXPORT RNG_IRQHandler [WEAK] EXPORT LPUART1_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] @@ -333,6 +339,8 @@ DMA1_Channel7_IRQHandler ADC1_2_IRQHandler USB_HP_IRQHandler USB_LP_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN1_IT1_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM15_IRQHandler TIM1_UP_TIM16_IRQHandler @@ -388,6 +396,10 @@ I2C4_EV_IRQHandler I2C4_ER_IRQHandler SPI4_IRQHandler AES_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN2_IT1_IRQHandler +FDCAN3_IT0_IRQHandler +FDCAN3_IT1_IRQHandler RNG_IRQHandler LPUART1_IRQHandler I2C3_EV_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_ARM/stm32g483xe.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_ARM/stm32g483xe.sct new file mode 100644 index 00000000000..331351213d6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_ARM/stm32g483xe.sct @@ -0,0 +1,57 @@ +#! armcc -E +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_GCC_ARM/startup_stm32g483xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_GCC_ARM/startup_stm32g483xx.S similarity index 95% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_GCC_ARM/startup_stm32g483xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_GCC_ARM/startup_stm32g483xx.S index 867f379856a..7440e88757a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_GCC_ARM/startup_stm32g483xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_GCC_ARM/startup_stm32g483xx.S @@ -94,7 +94,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit bl _start bx lr @@ -167,8 +167,8 @@ g_pfnVectors: .word ADC1_2_IRQHandler .word USB_HP_IRQHandler .word USB_LP_IRQHandler - .word 0 - .word 0 + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler .word EXTI9_5_IRQHandler .word TIM1_BRK_TIM15_IRQHandler .word TIM1_UP_TIM16_IRQHandler @@ -232,10 +232,10 @@ g_pfnVectors: .word I2C4_ER_IRQHandler .word SPI4_IRQHandler .word AES_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word FDCAN3_IT0_IRQHandler + .word FDCAN3_IT1_IRQHandler .word RNG_IRQHandler .word LPUART1_IRQHandler .word I2C3_EV_IRQHandler @@ -347,6 +347,12 @@ g_pfnVectors: .weak USB_LP_IRQHandler .thumb_set USB_LP_IRQHandler,Default_Handler + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler @@ -512,6 +518,17 @@ g_pfnVectors: .weak AES_IRQHandler .thumb_set AES_IRQHandler,Default_Handler + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler .weak RNG_IRQHandler .thumb_set RNG_IRQHandler,Default_Handler diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_GCC_ARM/stm32g483xe.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_GCC_ARM/stm32g483xe.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_GCC_ARM/stm32g483xe.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_IAR/startup_stm32g483xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_IAR/startup_stm32g483xx.S similarity index 94% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_IAR/startup_stm32g483xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_IAR/startup_stm32g483xx.S index 6dbea0578a3..05b1e5bd309 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_IAR/startup_stm32g483xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_IAR/startup_stm32g483xx.S @@ -94,8 +94,8 @@ __vector_table DCD ADC1_2_IRQHandler ; ADC1 and ADC2 DCD USB_HP_IRQHandler ; USB Device High Priority DCD USB_LP_IRQHandler ; USB Device Low Priority - DCD 0 ; Reserved - DCD 0 ; Reserved + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 @@ -158,11 +158,11 @@ __vector_table DCD I2C4_EV_IRQHandler ; I2C4 event DCD I2C4_ER_IRQHandler ; I2C4 error DCD SPI4_IRQHandler ; SPI4 - DCD AES_IRQHandler ; AES global interrupt DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved + DCD AES_IRQHandler ; AES global interrupt + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 DCD RNG_IRQHandler ; RNG global interrupt DCD LPUART1_IRQHandler ; LP UART 1 interrupt DCD I2C3_EV_IRQHandler ; I2C3 Event @@ -339,6 +339,16 @@ USB_HP_IRQHandler USB_LP_IRQHandler B USB_LP_IRQHandler + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + PUBWEAK EXTI9_5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) EXTI9_5_IRQHandler @@ -614,6 +624,26 @@ SPI4_IRQHandler AES_IRQHandler B AES_IRQHandler + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler + B FDCAN3_IT0_IRQHandler + + PUBWEAK FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler + B FDCAN3_IT1_IRQHandler + PUBWEAK RNG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) RNG_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_IAR/stm32g483xx.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_IAR/stm32g483xe.icf similarity index 97% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_IAR/stm32g483xx.icf rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_IAR/stm32g483xe.icf index 64170e81d13..d3bf9e3cd3a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_IAR/stm32g483xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/TOOLCHAIN_IAR/stm32g483xe.icf @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/cmsis_nvic.h similarity index 70% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/cmsis_nvic.h index 30891318eb6..6bbb29dd081 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G473xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xE/cmsis_nvic.h @@ -23,10 +23,6 @@ #if !defined(MBED_ROM_SIZE) #define MBED_ROM_SIZE 0x80000 // 512 KB - // 0x40000 STM32G473CCUx STM32G473MCTx STM32G473VCHx STM32G473CCTx STM32G473VCTx STM32G473QCTx STM32G473RCTx STM32G473VCIx - // 0x20000 STM32G473RBTx STM32G473QBTx STM32G473MBTx STM32G473VBIx STM32G473CBUx STM32G473VBTx STM32G473VBHx STM32G473CBTx - // 0x80000 STM32G473CETx STM32G473RETx STM32G473MEUx STM32G473VEIx STM32G473CEUx STM32G473METx STM32G473VEHx STM32G473VETx STM32G473QETx -#warning "check MBED_ROM_SIZE value in cmsis_nvic.h" #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_ARM_STD/stm32g483xx.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_ARM_STD/stm32g483xx.sct deleted file mode 100644 index a27952372d4..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_ARM_STD/stm32g483xx.sct +++ /dev/null @@ -1,57 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -; -; SPDX-License-Identifier: BSD-3-Clause -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2016-2020 STMicroelectronics. -;* All rights reserved. -;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause -;* -;****************************************************************************** - -#include "../cmsis_nvic.h" - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up - } - - ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down - } -} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_GCC_ARM/stm32g483xx.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_GCC_ARM/stm32g483xx.ld deleted file mode 100644 index 0a93b7b56bf..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G483xx/TOOLCHAIN_GCC_ARM/stm32g483xx.ld +++ /dev/null @@ -1,206 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Location counter can end up 2byte aligned with narrow Thumb code but - __etext is assumed by startup code to be the LMA of a section in RAM - which must be 8-byte aligned */ - __etext = ALIGN (8); - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_ARM_STD/startup_stm32g484xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_ARM/startup_stm32g484xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_ARM_STD/startup_stm32g484xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_ARM/startup_stm32g484xx.S diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_ARM/stm32g484xe.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_ARM/stm32g484xe.sct new file mode 100644 index 00000000000..331351213d6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_ARM/stm32g484xe.sct @@ -0,0 +1,57 @@ +#! armcc -E +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_GCC_ARM/startup_stm32g484xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_GCC_ARM/startup_stm32g484xx.S similarity index 99% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_GCC_ARM/startup_stm32g484xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_GCC_ARM/startup_stm32g484xx.S index bd74690b1ea..6877f771958 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_GCC_ARM/startup_stm32g484xx.S +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_GCC_ARM/startup_stm32g484xx.S @@ -93,7 +93,7 @@ LoopFillZerobss: cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit bl _start bx lr diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_GCC_ARM/stm32g484xe.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_GCC_ARM/stm32g484xe.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_GCC_ARM/stm32g484xe.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_IAR/startup_stm32g484xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_IAR/startup_stm32g484xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_IAR/startup_stm32g484xx.S rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_IAR/startup_stm32g484xx.S diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_IAR/stm32g484xe.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_IAR/stm32g484xe.icf new file mode 100644 index 00000000000..d3bf9e3cd3a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/TOOLCHAIN_IAR/stm32g484xe.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 118; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0xa000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/cmsis_nvic.h similarity index 70% rename from targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/cmsis_nvic.h index 0badcaa4a01..6bbb29dd081 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xE/cmsis_nvic.h @@ -23,10 +23,6 @@ #if !defined(MBED_ROM_SIZE) #define MBED_ROM_SIZE 0x80000 // 512 KB - // 0x40000 STM32G474VCIx STM32G474CCTx STM32G474QCTx STM32G474VCHx STM32G474CCUx STM32G474MCTx STM32G474VCTx STM32G474RCTx - // 0x20000 STM32G474VBIx STM32G474MBTx STM32G474CBTx STM32G474RBTx STM32G474QBTx STM32G474VBHx STM32G474VBTx STM32G474CBUx - // 0x80000 STM32G474CEUx STM32G474VEHx STM32G474RETx STM32G474QETx STM32G474METx STM32G474CETx STM32G474VEIx STM32G474VETx STM32G474MEYx -#warning "check MBED_ROM_SIZE value in cmsis_nvic.h" #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_ARM_STD/stm32g484xx.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_ARM_STD/stm32g484xx.sct deleted file mode 100644 index a27952372d4..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_ARM_STD/stm32g484xx.sct +++ /dev/null @@ -1,57 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -; -; SPDX-License-Identifier: BSD-3-Clause -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2016-2020 STMicroelectronics. -;* All rights reserved. -;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause -;* -;****************************************************************************** - -#include "../cmsis_nvic.h" - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up - } - - ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down - } -} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_GCC_ARM/stm32g484xx.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_GCC_ARM/stm32g484xx.ld deleted file mode 100644 index 0a93b7b56bf..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_GCC_ARM/stm32g484xx.ld +++ /dev/null @@ -1,206 +0,0 @@ -/* Linker script to configure memory regions. */ -/* - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#include "../cmsis_nvic.h" - - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) - -MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * _estack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* Location counter can end up 2byte aligned with narrow Thumb code but - __etext is assumed by startup code to be the LMA of a section in RAM - which must be 8-byte aligned */ - __etext = ALIGN (8); - _sidata = .; - - .data : AT (__etext) - { - __data_start__ = .; - _sdata = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - _edata = .; - - } > RAM - - /* Uninitialized data section - * This region is not initialized by the C/C++ library and can be used to - * store state across soft reboots. */ - .uninitialized (NOLOAD): - { - . = ALIGN(32); - __uninitialized_start = .; - *(.uninitialized) - KEEP(*(.keep.uninitialized)) - . = ALIGN(32); - __uninitialized_end = .; - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - _sbss = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - _ebss = .; - } > RAM - - .heap (COPY): - { - __end__ = .; - PROVIDE(end = .); - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (COPY): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - _estack = __StackTop; - __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_IAR/stm32g484xx.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_IAR/stm32g484xx.icf deleted file mode 100644 index 64170e81d13..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G484xx/TOOLCHAIN_IAR/stm32g484xx.icf +++ /dev/null @@ -1,59 +0,0 @@ -/* Linker script to configure memory regions. - * - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ -/* Device specific values */ - -/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ - -define symbol VECTORS = 118; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ -define symbol HEAP_SIZE = 0xa000; - -/* Common - Do not change */ - -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; -} - -/* Round up VECTORS_SIZE to 8 bytes */ -define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; -define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; -define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; - -define memory mem with size = 4G; -define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; -define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; - -define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; -define block HEAP with alignment = 8, size = HEAP_SIZE { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem: MBED_APP_START { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G4/analogin_device.c b/targets/TARGET_STM/TARGET_STM32G4/analogin_device.c index f8f1fab36e3..2b887b7c9c6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32G4/analogin_device.c @@ -1,30 +1,18 @@ /* mbed Microcontroller Library - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** */ + #include "mbed_assert.h" #include "analogin_api.h" @@ -313,12 +301,11 @@ void analogin_free(analogin_t *obj) #if defined(ADC1) if ((ADCName)obj->handle.Instance == ADC_1) { adc1_en_counter--; - if(ADC1_EN_CTR == 0) - { + if (ADC1_EN_CTR == 0) { HAL_ADC_DeInit(&obj->handle); // Disable clock if ADC2 is also unused - if(ADC2_EN_CTR == 0) { + if (ADC2_EN_CTR == 0) { LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC12); } } @@ -327,12 +314,11 @@ void analogin_free(analogin_t *obj) #if defined(ADC2) if ((ADCName)obj->handle.Instance == ADC_2) { adc2_en_counter--; - if(ADC2_EN_CTR == 0) - { + if (ADC2_EN_CTR == 0) { HAL_ADC_DeInit(&obj->handle); // Disable clock if ADC1 is also unused - if(ADC1_EN_CTR == 0) { + if (ADC1_EN_CTR == 0) { LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC12); } } @@ -341,12 +327,11 @@ void analogin_free(analogin_t *obj) #if defined(ADC3) if ((ADCName)obj->handle.Instance == ADC_3) { adc3_en_counter--; - if(ADC3_EN_CTR == 0) - { + if (ADC3_EN_CTR == 0) { HAL_ADC_DeInit(&obj->handle); // Disable clock if ADC4 and ADC5 are also unused - if((ADC4_EN_CTR + ADC5_EN_CTR) == 0) { + if ((ADC4_EN_CTR + ADC5_EN_CTR) == 0) { LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC345); } } @@ -355,12 +340,11 @@ void analogin_free(analogin_t *obj) #if defined(ADC4) if ((ADCName)obj->handle.Instance == ADC_4) { adc4_en_counter--; - if(ADC4_EN_CTR == 0) - { + if (ADC4_EN_CTR == 0) { HAL_ADC_DeInit(&obj->handle); // Disable clock if ADC3 and ADC5 are also unused - if((ADC3_EN_CTR + ADC5_EN_CTR) == 0) { + if ((ADC3_EN_CTR + ADC5_EN_CTR) == 0) { LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC345); } } @@ -370,12 +354,11 @@ void analogin_free(analogin_t *obj) #if defined(ADC5) if ((ADCName)obj->handle.Instance == ADC_5) { adc5_en_counter--; - if(ADC5_EN_CTR == 0) - { + if (ADC5_EN_CTR == 0) { HAL_ADC_DeInit(&obj->handle); // Disable clock if ADC3 and ADC4 are also unused - if((ADC3_EN_CTR + ADC4_EN_CTR) == 0) { + if ((ADC3_EN_CTR + ADC4_EN_CTR) == 0) { LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC345); } } diff --git a/targets/TARGET_STM/TARGET_STM32G4/analogout_device.c b/targets/TARGET_STM/TARGET_STM32G4/analogout_device.c index 7ee22c2caa0..46efa9a25ff 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32G4/analogout_device.c @@ -1,30 +1,18 @@ /* mbed Microcontroller Library - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** */ + #include "mbed_assert.h" #include "analogout_api.h" diff --git a/targets/TARGET_STM/TARGET_STM32G4/cmsis.h b/targets/TARGET_STM/TARGET_STM32G4/cmsis.h index 1e97949ba45..aaa02fc80d2 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/cmsis.h +++ b/targets/TARGET_STM/TARGET_STM32G4/cmsis.h @@ -1,18 +1,16 @@ /* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ #ifndef MBED_CMSIS_H diff --git a/targets/TARGET_STM/TARGET_STM32G4/flash_api.c b/targets/TARGET_STM/TARGET_STM32G4/flash_api.c index 826e15e6967..4b12ce0b9c3 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32G4/flash_api.c @@ -1,19 +1,16 @@ /* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited - * Copyright (c) 2017 STMicroelectronics - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ #include "flash_api.h" @@ -51,7 +48,7 @@ static uint32_t GetPage(uint32_t Addr) static uint32_t GetBank(uint32_t Addr) { uint32_t bank = 0; -#if defined(SYSCFG_MEMRMP_FB_MODE) +#if defined(SYSCFG_MEMRMP_FB_MODE) && defined(FLASH_OPTR_DBANK) if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) { /* No Bank swap */ if (Addr < (FLASH_BASE + FLASH_BANK_SIZE)) { @@ -68,7 +65,6 @@ static uint32_t GetBank(uint32_t Addr) } } #else - /* Device like L432KC */ bank = FLASH_BANK_1; #endif diff --git a/targets/TARGET_STM/TARGET_STM32G4/gpio_irq_device.c b/targets/TARGET_STM/TARGET_STM32G4/gpio_irq_device.c index e18dfba047d..e082e06e722 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/gpio_irq_device.c +++ b/targets/TARGET_STM/TARGET_STM32G4/gpio_irq_device.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2015-2020 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -12,6 +12,7 @@ * ****************************************************************************** */ + #include "cmsis.h" #include "gpio_irq_device.h" diff --git a/targets/TARGET_STM/TARGET_STM32G4/gpio_irq_device.h b/targets/TARGET_STM/TARGET_STM32G4/gpio_irq_device.h index cf99296891a..556fcd57e14 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/gpio_irq_device.h +++ b/targets/TARGET_STM/TARGET_STM32G4/gpio_irq_device.h @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2015-2020 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -12,6 +12,7 @@ * ****************************************************************************** */ + #ifndef MBED_GPIO_IRQ_DEVICE_H #define MBED_GPIO_IRQ_DEVICE_H diff --git a/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h b/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h index 087d9e43a31..35f5c320e11 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2015 STMicroelectronics. + * Copyright (c) 2015-2020 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -12,6 +12,7 @@ * ****************************************************************************** */ + #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H diff --git a/targets/TARGET_STM/TARGET_STM32G4/objects.h b/targets/TARGET_STM/TARGET_STM32G4/objects.h index 5c7f62db295..5ca363a00c6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/objects.h +++ b/targets/TARGET_STM/TARGET_STM32G4/objects.h @@ -1,19 +1,18 @@ /* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ + #ifndef MBED_OBJECTS_H #define MBED_OBJECTS_H diff --git a/targets/TARGET_STM/TARGET_STM32G4/pin_device.h b/targets/TARGET_STM/TARGET_STM32G4/pin_device.h index ca16058f5d9..da826c9ff38 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32G4/pin_device.h @@ -12,6 +12,7 @@ * ****************************************************************************** */ + #ifndef MBED_PIN_DEVICE_H #define MBED_PIN_DEVICE_H diff --git a/targets/TARGET_STM/TARGET_STM32G4/pwmout_device.c b/targets/TARGET_STM/TARGET_STM32G4/pwmout_device.c index cea9afaf06b..c831071a48f 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/pwmout_device.c +++ b/targets/TARGET_STM/TARGET_STM32G4/pwmout_device.c @@ -1,32 +1,18 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + ****************************************************************************** */ + #include "cmsis.h" #include "pwmout_api.h" #include "pwmout_device.h" diff --git a/targets/TARGET_STM/TARGET_STM32G4/pwmout_device.h b/targets/TARGET_STM/TARGET_STM32G4/pwmout_device.h index bc6f761f181..f12945df768 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/pwmout_device.h +++ b/targets/TARGET_STM/TARGET_STM32G4/pwmout_device.h @@ -1,32 +1,18 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + ****************************************************************************** */ + #ifndef MBED_PWMOUT_DEVICE_H #define MBED_PWMOUT_DEVICE_H diff --git a/targets/TARGET_STM/TARGET_STM32G4/serial_device.c b/targets/TARGET_STM/TARGET_STM32G4/serial_device.c index 6cd86387510..7f4e06ec4a8 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32G4/serial_device.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2015-2020 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, diff --git a/targets/TARGET_STM/TARGET_STM32G4/spi_api.c b/targets/TARGET_STM/TARGET_STM32G4/spi_api.c index b714ba9bde4..63af2042eb3 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32G4/spi_api.c @@ -1,32 +1,18 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2020, STMicroelectronics - * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + ****************************************************************************** */ + #include "mbed_assert.h" #include "mbed_error.h" #include "spi_api.h" diff --git a/targets/TARGET_STM/TARGET_STM32G4/spi_device.h b/targets/TARGET_STM/TARGET_STM32G4/spi_device.h index c8b7567a03f..6eef23df0a4 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/spi_device.h +++ b/targets/TARGET_STM/TARGET_STM32G4/spi_device.h @@ -1,32 +1,18 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + ****************************************************************************** */ + #ifndef MBED_SPI_DEVICE_H #define MBED_SPI_DEVICE_H diff --git a/targets/TARGET_STM/TARGET_STM32G4/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32G4/us_ticker_data.h index 928d55ee270..1dba0fcbf5c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32G4/us_ticker_data.h @@ -2,27 +2,30 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2015-2020 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ + #ifndef __US_TICKER_DATA_H #define __US_TICKER_DATA_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #include "stm32g4xx.h" #include "stm32g4xx_ll_tim.h" #include "cmsis_nvic.h" - + +#if defined TIM5_BASE + #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() @@ -31,6 +34,18 @@ #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() +#else + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() + +#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() + +#endif + #define TIM_MST_BIT_WIDTH 32 // 16 or 32 #define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) diff --git a/targets/targets.json b/targets/targets.json index 2d752db72dd..40c30ffc772 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2454,6 +2454,11 @@ "value": "USE_PLL_HSE_EXTC", "macro_name": "CLOCK_SOURCE" }, + "hse_value": { + "help": "HSE default value is 8MHz in stm32g4xx_hal_conf.h", + "value": "8000000", + "macro_name": "HSE_VALUE" + }, "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", "value": 1 @@ -2479,33 +2484,129 @@ "CAN" ] }, - "NUCLEO_G474RE": { + "MCU_STM32G431xB": { + "inherits": [ + "MCU_STM32G4" + ], + "public": false, + "extra_labels_add": [ + "STM32G431xB" + ], + "macros_add": [ + "STM32G431xx" + ] + }, + "MCU_STM32G441xB": { + "inherits": [ + "MCU_STM32G4" + ], + "public": false, + "extra_labels_add": [ + "STM32G441xB" + ], + "macros_add": [ + "STM32G441xx" + ] + }, + "MCU_STM32G471xE": { + "inherits": [ + "MCU_STM32G4" + ], + "public": false, + "extra_labels_add": [ + "STM32G471xE" + ], + "macros_add": [ + "STM32G471xx" + ] + }, + "MCU_STM32G473xE": { + "inherits": [ + "MCU_STM32G4" + ], + "public": false, + "extra_labels_add": [ + "STM32G473xE" + ], + "macros_add": [ + "STM32G473xx" + ] + }, + "MCU_STM32G474xE": { "inherits": [ "MCU_STM32G4" ], + "public": false, + "extra_labels_add": [ + "STM32G474xE" + ], + "macros_add": [ + "STM32G474xx" + ] + }, + "NUCLEO_G474RE": { + "inherits": [ + "MCU_STM32G474xE" + ], "supported_form_factors": [ "ARDUINO", "MORPHO" ], - "config": { - "hse_value": { - "help": "HSE default value is 25MHz in HAL", - "value": "24000000", - "macro_name": "HSE_VALUE" - } + "overrides": { + "hse_value": 24000000 }, + "detect_code": [ + "0841" + ], + "device_name": "STM32G474RETx" + }, + "MCU_STM32G483xE": { + "inherits": [ + "MCU_STM32G4" + ], + "public": false, "extra_labels_add": [ - "STM32G474xx", - "STM32G474RE" + "STM32G483xE" ], "macros_add": [ - "STM32G474xx", - "STM32G474RE" + "STM32G483xx" + ] + }, + "MCU_STM32G484xE": { + "inherits": [ + "MCU_STM32G4" ], - "detect_code": [ - "0841" + "public": false, + "extra_labels_add": [ + "STM32G484xE" ], - "device_name": "STM32G474RETx" + "macros_add": [ + "STM32G484xx" + ] + }, + "MCU_STM32G491xE": { + "inherits": [ + "MCU_STM32G4" + ], + "public": false, + "extra_labels_add": [ + "STM32G491xE" + ], + "macros_add": [ + "STM32G491xx" + ] + }, + "MCU_STM32G4A1xE": { + "inherits": [ + "MCU_STM32G4" + ], + "public": false, + "extra_labels_add": [ + "STM32G4A1xE" + ], + "macros_add": [ + "STM32G4A1xx" + ] }, "MCU_STM32H7": { "inherits": [