From 904d4e4d2baa5128a0b0466a9f7c4927b4e68fa4 Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Mon, 12 Apr 2021 09:34:18 +0300 Subject: [PATCH] Make ticker computation use shift-by-0 Runtime code that analysed clock frequency to determine numerator and denominator for conversion to standard 1MHz failed to handle the case of either being 1 correctly. Although it would spot other values that could be performed as shifts, it failed to spot that 1 is "shift by 0", so would end up doing runtime multiply and/or divide by 1. The runtime divide by 1 could be slow on a Cortex-M0 device, increasing interrupt latency. UART character loss on STM32F0 devices has been traced to this incorrect code. Correct the `exact_log2` routine so that `exact_log2(1)` returns 0 to fix this. Original code had a single special no-multiply-or-divide case for hardware clock frequency being exactly 1MHz, as USTICKER is on STM32F0 - this code lacks that but has a more general special case that covers all shift-convertible frequencies like 500kHz or 8MHz, which should be similar speed as shifts are cheap. --- hal/source/mbed_ticker_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hal/source/mbed_ticker_api.c b/hal/source/mbed_ticker_api.c index 736b90dc08d..999e464fccd 100644 --- a/hal/source/mbed_ticker_api.c +++ b/hal/source/mbed_ticker_api.c @@ -110,7 +110,7 @@ static inline uint32_t gcd(uint32_t a, uint32_t b) static int exact_log2(uint32_t n) { - for (int i = 31; i > 0; --i) { + for (int i = 31; i >= 0; --i) { if ((1U << i) == n) { return i; }