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Add v128.load/storeN_lane SIMD instructions to C/JS API (#3784)
Adds C/JS APIs for the SIMD instructions * Load8LaneVec128 (was LoadLaneVec8x16) * Load16LaneVec128 (was LoadLaneVec16x8) * Load32LaneVec128 (was LoadLaneVec32x4) * Load64LaneVec128 (was LoadLaneVec64x2) * Store8LaneVec128 (was StoreLaneVec8x16) * Store16LaneVec128 (was StoreLaneVec16x8) * Store32LaneVec128 (was StoreLaneVec32x4) * Store64LaneVec128 (was StoreLaneVec64x2)
1 parent 6921dd3 commit 0efebfe

17 files changed

+435
-88
lines changed

‎scripts/gen-s-parser.py

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -357,14 +357,14 @@
357357
("v128.andnot", "makeBinary(s, BinaryOp::AndNotVec128)"),
358358
("v128.any_true", "makeUnary(s, UnaryOp::AnyTrueVec128)"),
359359
("v128.bitselect", "makeSIMDTernary(s, SIMDTernaryOp::Bitselect)"),
360-
("v128.load8_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec8x16)"),
361-
("v128.load16_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec16x8)"),
362-
("v128.load32_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec32x4)"),
363-
("v128.load64_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec64x2)"),
364-
("v128.store8_lane", "makeSIMDLoadStoreLane(s, StoreLaneVec8x16)"),
365-
("v128.store16_lane", "makeSIMDLoadStoreLane(s, StoreLaneVec16x8)"),
366-
("v128.store32_lane", "makeSIMDLoadStoreLane(s, StoreLaneVec32x4)"),
367-
("v128.store64_lane", "makeSIMDLoadStoreLane(s, StoreLaneVec64x2)"),
360+
("v128.load8_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load8LaneVec128)"),
361+
("v128.load16_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load16LaneVec128)"),
362+
("v128.load32_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load32LaneVec128)"),
363+
("v128.load64_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load64LaneVec128)"),
364+
("v128.store8_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store8LaneVec128)"),
365+
("v128.store16_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store16LaneVec128)"),
366+
("v128.store32_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store32LaneVec128)"),
367+
("v128.store64_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store64LaneVec128)"),
368368
("i8x16.popcnt", "makeUnary(s, UnaryOp::PopcntVecI8x16)"),
369369
("i8x16.abs", "makeUnary(s, UnaryOp::AbsVecI8x16)"),
370370
("i8x16.neg", "makeUnary(s, UnaryOp::NegVecI8x16)"),

‎src/binaryen-c.cpp

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -689,6 +689,14 @@ BinaryenOp BinaryenLoadExtUVec32x2ToVecI64x2(void) {
689689
}
690690
BinaryenOp BinaryenLoad32Zero(void) { return Load32Zero; }
691691
BinaryenOp BinaryenLoad64Zero(void) { return Load64Zero; }
692+
BinaryenOp BinaryenLoad8LaneVec128(void) { return Load8LaneVec128; }
693+
BinaryenOp BinaryenLoad16LaneVec128(void) { return Load16LaneVec128; }
694+
BinaryenOp BinaryenLoad32LaneVec128(void) { return Load32LaneVec128; }
695+
BinaryenOp BinaryenLoad64LaneVec128(void) { return Load64LaneVec128; }
696+
BinaryenOp BinaryenStore8LaneVec128(void) { return Store8LaneVec128; }
697+
BinaryenOp BinaryenStore16LaneVec128(void) { return Store16LaneVec128; }
698+
BinaryenOp BinaryenStore32LaneVec128(void) { return Store32LaneVec128; }
699+
BinaryenOp BinaryenStore64LaneVec128(void) { return Store64LaneVec128; }
692700
BinaryenOp BinaryenNarrowSVecI16x8ToVecI8x16(void) {
693701
return NarrowSVecI16x8ToVecI8x16;
694702
}
@@ -1176,6 +1184,22 @@ BinaryenExpressionRef BinaryenSIMDLoad(BinaryenModuleRef module,
11761184
.makeSIMDLoad(
11771185
SIMDLoadOp(op), Address(offset), Address(align), (Expression*)ptr));
11781186
}
1187+
BinaryenExpressionRef BinaryenSIMDLoadStoreLane(BinaryenModuleRef module,
1188+
BinaryenOp op,
1189+
uint32_t offset,
1190+
uint32_t align,
1191+
uint8_t index,
1192+
BinaryenExpressionRef ptr,
1193+
BinaryenExpressionRef vec) {
1194+
return static_cast<Expression*>(
1195+
Builder(*(Module*)module)
1196+
.makeSIMDLoadStoreLane(SIMDLoadStoreLaneOp(op),
1197+
Address(offset),
1198+
Address(align),
1199+
index,
1200+
(Expression*)ptr,
1201+
(Expression*)vec));
1202+
}
11791203
BinaryenExpressionRef BinaryenMemoryInit(BinaryenModuleRef module,
11801204
uint32_t segment,
11811205
BinaryenExpressionRef dest,

‎src/binaryen-c.h

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -560,6 +560,14 @@ BINARYEN_API BinaryenOp BinaryenLoadExtSVec32x2ToVecI64x2(void);
560560
BINARYEN_API BinaryenOp BinaryenLoadExtUVec32x2ToVecI64x2(void);
561561
BINARYEN_API BinaryenOp BinaryenLoad32Zero(void);
562562
BINARYEN_API BinaryenOp BinaryenLoad64Zero(void);
563+
BINARYEN_API BinaryenOp BinaryenLoad8LaneVec128(void);
564+
BINARYEN_API BinaryenOp BinaryenLoad16LaneVec128(void);
565+
BINARYEN_API BinaryenOp BinaryenLoad32LaneVec128(void);
566+
BINARYEN_API BinaryenOp BinaryenLoad64LaneVec128(void);
567+
BINARYEN_API BinaryenOp BinaryenStore8LaneVec128(void);
568+
BINARYEN_API BinaryenOp BinaryenStore16LaneVec128(void);
569+
BINARYEN_API BinaryenOp BinaryenStore32LaneVec128(void);
570+
BINARYEN_API BinaryenOp BinaryenStore64LaneVec128(void);
563571
BINARYEN_API BinaryenOp BinaryenNarrowSVecI16x8ToVecI8x16(void);
564572
BINARYEN_API BinaryenOp BinaryenNarrowUVecI16x8ToVecI8x16(void);
565573
BINARYEN_API BinaryenOp BinaryenNarrowSVecI32x4ToVecI16x8(void);
@@ -803,6 +811,14 @@ BINARYEN_API BinaryenExpressionRef BinaryenSIMDLoad(BinaryenModuleRef module,
803811
uint32_t align,
804812
BinaryenExpressionRef ptr);
805813
BINARYEN_API BinaryenExpressionRef
814+
BinaryenSIMDLoadStoreLane(BinaryenModuleRef module,
815+
BinaryenOp op,
816+
uint32_t offset,
817+
uint32_t align,
818+
uint8_t index,
819+
BinaryenExpressionRef ptr,
820+
BinaryenExpressionRef vec);
821+
BINARYEN_API BinaryenExpressionRef
806822
BinaryenMemoryInit(BinaryenModuleRef module,
807823
uint32_t segment,
808824
BinaryenExpressionRef dest,

‎src/gen-s-parser.inc

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2998,7 +2998,7 @@ switch (op[0]) {
29982998
case '_': {
29992999
switch (op[12]) {
30003000
case 'l':
3001-
if (strcmp(op, "v128.load16_lane") == 0) { return makeSIMDLoadStoreLane(s, LoadLaneVec16x8); }
3001+
if (strcmp(op, "v128.load16_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load16LaneVec128); }
30023002
goto parse_error;
30033003
case 's':
30043004
if (strcmp(op, "v128.load16_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec16x8); }
@@ -3025,7 +3025,7 @@ switch (op[0]) {
30253025
case '_': {
30263026
switch (op[12]) {
30273027
case 'l':
3028-
if (strcmp(op, "v128.load32_lane") == 0) { return makeSIMDLoadStoreLane(s, LoadLaneVec32x4); }
3028+
if (strcmp(op, "v128.load32_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load32LaneVec128); }
30293029
goto parse_error;
30303030
case 's':
30313031
if (strcmp(op, "v128.load32_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec32x4); }
@@ -3053,7 +3053,7 @@ switch (op[0]) {
30533053
case '6': {
30543054
switch (op[12]) {
30553055
case 'l':
3056-
if (strcmp(op, "v128.load64_lane") == 0) { return makeSIMDLoadStoreLane(s, LoadLaneVec64x2); }
3056+
if (strcmp(op, "v128.load64_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load64LaneVec128); }
30573057
goto parse_error;
30583058
case 's':
30593059
if (strcmp(op, "v128.load64_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec64x2); }
@@ -3069,7 +3069,7 @@ switch (op[0]) {
30693069
case '_': {
30703070
switch (op[11]) {
30713071
case 'l':
3072-
if (strcmp(op, "v128.load8_lane") == 0) { return makeSIMDLoadStoreLane(s, LoadLaneVec8x16); }
3072+
if (strcmp(op, "v128.load8_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load8LaneVec128); }
30733073
goto parse_error;
30743074
case 's':
30753075
if (strcmp(op, "v128.load8_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec8x16); }
@@ -3106,16 +3106,16 @@ switch (op[0]) {
31063106
if (strcmp(op, "v128.store") == 0) { return makeStore(s, Type::v128, /*isAtomic=*/false); }
31073107
goto parse_error;
31083108
case '1':
3109-
if (strcmp(op, "v128.store16_lane") == 0) { return makeSIMDLoadStoreLane(s, StoreLaneVec16x8); }
3109+
if (strcmp(op, "v128.store16_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store16LaneVec128); }
31103110
goto parse_error;
31113111
case '3':
3112-
if (strcmp(op, "v128.store32_lane") == 0) { return makeSIMDLoadStoreLane(s, StoreLaneVec32x4); }
3112+
if (strcmp(op, "v128.store32_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store32LaneVec128); }
31133113
goto parse_error;
31143114
case '6':
3115-
if (strcmp(op, "v128.store64_lane") == 0) { return makeSIMDLoadStoreLane(s, StoreLaneVec64x2); }
3115+
if (strcmp(op, "v128.store64_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store64LaneVec128); }
31163116
goto parse_error;
31173117
case '8':
3118-
if (strcmp(op, "v128.store8_lane") == 0) { return makeSIMDLoadStoreLane(s, StoreLaneVec8x16); }
3118+
if (strcmp(op, "v128.store8_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store8LaneVec128); }
31193119
goto parse_error;
31203120
default: goto parse_error;
31213121
}

‎src/js/binaryen.js-post.js

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -492,6 +492,14 @@ function initializeConstants() {
492492
'LoadExtUVec32x2ToVecI64x2',
493493
'Load32Zero',
494494
'Load64Zero',
495+
'Load8LaneVec128',
496+
'Load16LaneVec128',
497+
'Load32LaneVec128',
498+
'Load64LaneVec128',
499+
'Store8LaneVec128',
500+
'Store16LaneVec128',
501+
'Store32LaneVec128',
502+
'Store64LaneVec128',
495503
'NarrowSVecI16x8ToVecI8x16',
496504
'NarrowUVecI16x8ToVecI8x16',
497505
'NarrowSVecI32x4ToVecI16x8',
@@ -1498,6 +1506,30 @@ function wrapModule(module, self = {}) {
14981506
'load64_zero'(offset, align, ptr) {
14991507
return Module['_BinaryenSIMDLoad'](module, Module['Load64Zero'], offset, align, ptr);
15001508
},
1509+
'load8_lane'(offset, align, index, ptr, vec) {
1510+
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Load8LaneVec128'], offset, align, index, ptr, vec);
1511+
},
1512+
'load16_lane'(offset, align, index, ptr, vec) {
1513+
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Load16LaneVec128'], offset, align, index, ptr, vec);
1514+
},
1515+
'load32_lane'(offset, align, index, ptr, vec) {
1516+
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Load32LaneVec128'], offset, align, index, ptr, vec);
1517+
},
1518+
'load64_lane'(offset, align, index, ptr, vec) {
1519+
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Load64LaneVec128'], offset, align, index, ptr, vec);
1520+
},
1521+
'store8_lane'(offset, align, index, ptr, vec) {
1522+
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Store8LaneVec128'], offset, align, index, ptr, vec);
1523+
},
1524+
'store16_lane'(offset, align, index, ptr, vec) {
1525+
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Store16LaneVec128'], offset, align, index, ptr, vec);
1526+
},
1527+
'store32_lane'(offset, align, index, ptr, vec) {
1528+
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Store32LaneVec128'], offset, align, index, ptr, vec);
1529+
},
1530+
'store64_lane'(offset, align, index, ptr, vec) {
1531+
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Store64LaneVec128'], offset, align, index, ptr, vec);
1532+
},
15011533
'store'(offset, align, ptr, value) {
15021534
return Module['_BinaryenStore'](module, 16, offset, align, ptr, value, Module['v128']);
15031535
},

‎src/passes/Print.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -747,28 +747,28 @@ struct PrintExpressionContents
747747
void visitSIMDLoadStoreLane(SIMDLoadStoreLane* curr) {
748748
prepareColor(o);
749749
switch (curr->op) {
750-
case LoadLaneVec8x16:
750+
case Load8LaneVec128:
751751
o << "v128.load8_lane";
752752
break;
753-
case LoadLaneVec16x8:
753+
case Load16LaneVec128:
754754
o << "v128.load16_lane";
755755
break;
756-
case LoadLaneVec32x4:
756+
case Load32LaneVec128:
757757
o << "v128.load32_lane";
758758
break;
759-
case LoadLaneVec64x2:
759+
case Load64LaneVec128:
760760
o << "v128.load64_lane";
761761
break;
762-
case StoreLaneVec8x16:
762+
case Store8LaneVec128:
763763
o << "v128.store8_lane";
764764
break;
765-
case StoreLaneVec16x8:
765+
case Store16LaneVec128:
766766
o << "v128.store16_lane";
767767
break;
768-
case StoreLaneVec32x4:
768+
case Store32LaneVec128:
769769
o << "v128.store32_lane";
770770
break;
771-
case StoreLaneVec64x2:
771+
case Store64LaneVec128:
772772
o << "v128.store64_lane";
773773
break;
774774
}

‎src/wasm-interpreter.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2821,8 +2821,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
28212821
}
28222822
Literal vec = flow.getSingleValue();
28232823
switch (curr->op) {
2824-
case LoadLaneVec8x16:
2825-
case StoreLaneVec8x16: {
2824+
case Load8LaneVec128:
2825+
case Store8LaneVec128: {
28262826
std::array<Literal, 16> lanes = vec.getLanesUI8x16();
28272827
if (curr->isLoad()) {
28282828
lanes[curr->index] =
@@ -2834,8 +2834,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
28342834
return {};
28352835
}
28362836
}
2837-
case LoadLaneVec16x8:
2838-
case StoreLaneVec16x8: {
2837+
case Load16LaneVec128:
2838+
case Store16LaneVec128: {
28392839
std::array<Literal, 8> lanes = vec.getLanesUI16x8();
28402840
if (curr->isLoad()) {
28412841
lanes[curr->index] =
@@ -2847,8 +2847,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
28472847
return {};
28482848
}
28492849
}
2850-
case LoadLaneVec32x4:
2851-
case StoreLaneVec32x4: {
2850+
case Load32LaneVec128:
2851+
case Store32LaneVec128: {
28522852
std::array<Literal, 4> lanes = vec.getLanesI32x4();
28532853
if (curr->isLoad()) {
28542854
lanes[curr->index] =
@@ -2860,8 +2860,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
28602860
return {};
28612861
}
28622862
}
2863-
case StoreLaneVec64x2:
2864-
case LoadLaneVec64x2: {
2863+
case Store64LaneVec128:
2864+
case Load64LaneVec128: {
28652865
std::array<Literal, 2> lanes = vec.getLanesI64x2();
28662866
if (curr->isLoad()) {
28672867
lanes[curr->index] =

‎src/wasm.h

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -515,14 +515,14 @@ enum SIMDLoadOp {
515515
};
516516

517517
enum SIMDLoadStoreLaneOp {
518-
LoadLaneVec8x16,
519-
LoadLaneVec16x8,
520-
LoadLaneVec32x4,
521-
LoadLaneVec64x2,
522-
StoreLaneVec8x16,
523-
StoreLaneVec16x8,
524-
StoreLaneVec32x4,
525-
StoreLaneVec64x2,
518+
Load8LaneVec128,
519+
Load16LaneVec128,
520+
Load32LaneVec128,
521+
Load64LaneVec128,
522+
Store8LaneVec128,
523+
Store16LaneVec128,
524+
Store32LaneVec128,
525+
Store64LaneVec128,
526526
};
527527

528528
enum SIMDTernaryOp {

‎src/wasm/wasm-binary.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5897,35 +5897,35 @@ bool WasmBinaryBuilder::maybeVisitSIMDLoadStoreLane(Expression*& out,
58975897
size_t lanes;
58985898
switch (code) {
58995899
case BinaryConsts::V128Load8Lane:
5900-
op = LoadLaneVec8x16;
5900+
op = Load8LaneVec128;
59015901
lanes = 16;
59025902
break;
59035903
case BinaryConsts::V128Load16Lane:
5904-
op = LoadLaneVec16x8;
5904+
op = Load16LaneVec128;
59055905
lanes = 8;
59065906
break;
59075907
case BinaryConsts::V128Load32Lane:
5908-
op = LoadLaneVec32x4;
5908+
op = Load32LaneVec128;
59095909
lanes = 4;
59105910
break;
59115911
case BinaryConsts::V128Load64Lane:
5912-
op = LoadLaneVec64x2;
5912+
op = Load64LaneVec128;
59135913
lanes = 2;
59145914
break;
59155915
case BinaryConsts::V128Store8Lane:
5916-
op = StoreLaneVec8x16;
5916+
op = Store8LaneVec128;
59175917
lanes = 16;
59185918
break;
59195919
case BinaryConsts::V128Store16Lane:
5920-
op = StoreLaneVec16x8;
5920+
op = Store16LaneVec128;
59215921
lanes = 8;
59225922
break;
59235923
case BinaryConsts::V128Store32Lane:
5924-
op = StoreLaneVec32x4;
5924+
op = Store32LaneVec128;
59255925
lanes = 4;
59265926
break;
59275927
case BinaryConsts::V128Store64Lane:
5928-
op = StoreLaneVec64x2;
5928+
op = Store64LaneVec128;
59295929
lanes = 2;
59305930
break;
59315931
default:

‎src/wasm/wasm-s-parser.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2067,23 +2067,23 @@ SExpressionWasmBuilder::makeSIMDLoadStoreLane(Element& s,
20672067
Address defaultAlign;
20682068
size_t lanes;
20692069
switch (op) {
2070-
case LoadLaneVec8x16:
2071-
case StoreLaneVec8x16:
2070+
case Load8LaneVec128:
2071+
case Store8LaneVec128:
20722072
defaultAlign = 1;
20732073
lanes = 16;
20742074
break;
2075-
case LoadLaneVec16x8:
2076-
case StoreLaneVec16x8:
2075+
case Load16LaneVec128:
2076+
case Store16LaneVec128:
20772077
defaultAlign = 2;
20782078
lanes = 8;
20792079
break;
2080-
case LoadLaneVec32x4:
2081-
case StoreLaneVec32x4:
2080+
case Load32LaneVec128:
2081+
case Store32LaneVec128:
20822082
defaultAlign = 4;
20832083
lanes = 4;
20842084
break;
2085-
case LoadLaneVec64x2:
2086-
case StoreLaneVec64x2:
2085+
case Load64LaneVec128:
2086+
case Store64LaneVec128:
20872087
defaultAlign = 8;
20882088
lanes = 2;
20892089
break;

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