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Merge pull request #4 from electro-smith/astyle_fixes
fixed style errors
2 parents ee09f0a + a399d89 commit e5fe89f

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2 files changed

+29
-32
lines changed

2 files changed

+29
-32
lines changed

variants/DAISY_SEED/variant.cpp

Lines changed: 27 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -52,19 +52,19 @@ const PinName digitalPin[] = {
5252
};
5353

5454
const uint32_t analogInputPin[] = {
55-
// PXn, // Ax = Dx
56-
15, // A0 = D15
57-
16, // A1 = D16
58-
17, // A2 = D17
59-
18, // A3 = D18
60-
19, // A4 = D19
61-
20, // A5 = D20
62-
21, // A6 = D21
63-
22, // A7 = D22
64-
23, // A8 = D23
65-
24, // A9 = D24
66-
25, // A10 = D25
67-
28, // A11 = D28
55+
// PXn, // Ax = Dx
56+
15, // A0 = D15
57+
16, // A1 = D16
58+
17, // A2 = D17
59+
18, // A3 = D18
60+
19, // A4 = D19
61+
20, // A5 = D20
62+
21, // A6 = D21
63+
22, // A7 = D22
64+
23, // A8 = D23
65+
24, // A9 = D24
66+
25, // A10 = D25
67+
28, // A11 = D28
6868
};
6969

7070
#ifdef __cplusplus
@@ -89,19 +89,19 @@ WEAK void SystemClock_Config(void)
8989
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
9090

9191
/** Supply configuration update enable
92-
*/
92+
*/
9393
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
9494
/** Configure the main internal regulator output voltage
95-
*/
95+
*/
9696
//__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); // 400MHz Mode.
9797
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); // 480MHz
9898

9999
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
100100
/** Macro to configure the PLL clock source
101-
*/
101+
*/
102102
__HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
103103
/** Initializes the CPU, AHB and APB busses clocks
104-
*/
104+
*/
105105
RCC_OscInitStruct.OscillatorType
106106
= RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
107107
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -112,20 +112,19 @@ WEAK void SystemClock_Config(void)
112112
RCC_OscInitStruct.PLL.PLLN = 200; // 400MHz Mode
113113
//RCC_OscInitStruct.PLL.PLLN = 240; // 480MHz Mode
114114
RCC_OscInitStruct.PLL.PLLP = 2;
115-
RCC_OscInitStruct.PLL.PLLQ = 5;
115+
RCC_OscInitStruct.PLL.PLLQ = 5;
116116
RCC_OscInitStruct.PLL.PLLR = 2;
117117
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
118118
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
119119
RCC_OscInitStruct.PLL.PLLFRACN = 0;
120-
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
121-
{
120+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
122121
Error_Handler();
123122
}
124123
/** Initializes the CPU, AHB and APB busses clocks
125-
*/
124+
*/
126125
RCC_ClkInitStruct.ClockType
127126
= RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
128-
| RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
127+
| RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
129128
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
130129
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
131130
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
@@ -134,15 +133,14 @@ WEAK void SystemClock_Config(void)
134133
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
135134
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
136135

137-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
138-
{
136+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
139137
Error_Handler();
140138
}
141139
PeriphClkInitStruct.PeriphClockSelection
142140
= RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SPI1
143-
| RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SDMMC
144-
| RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_I2C1
145-
| RCC_PERIPHCLK_USB | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_FMC;
141+
| RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SDMMC
142+
| RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_I2C1
143+
| RCC_PERIPHCLK_USB | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_FMC;
146144
// PLL 2
147145
PeriphClkInitStruct.PLL2.PLL2M = 4;
148146
// PeriphClkInitStruct.PLL2.PLL2N = 115; // Max Freq @ 3v3 (overclocked SDRAM)
@@ -175,12 +173,11 @@ WEAK void SystemClock_Config(void)
175173
PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PLL3;
176174
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
177175
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL3;
178-
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
179-
{
176+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
180177
Error_Handler();
181178
}
182179
/** Enable USB Voltage detector
183-
*/
180+
*/
184181
HAL_PWREx_EnableUSBVoltageDetector();
185182
}
186183

variants/DAISY_SEED/variant.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ extern "C" {
4949
//#define NUM_ANALOG_FIRST 15 // commented out to use analogInputPin[]
5050

5151
// On-board LED pin number
52-
#define LED_BUILTIN PC7
52+
#define LED_BUILTIN PC7
5353
#define LED_RED LED_BUILTIN
5454

5555
// Below SPI and I2C definitions already done in the core
@@ -91,7 +91,7 @@ extern "C" {
9191

9292
// HSE default value is 25MHz in HAL
9393
// HSE_BYPASS is 8MHz ?
94-
// HSE is 16MHz on Daisy Seed.
94+
// HSE is 16MHz on Daisy Seed.
9595
#ifndef HSE_BYPASS_NOT_USED
9696
#define HSE_VALUE 16000000
9797
#endif

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