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suda-morrissuda-morris
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Merge branch 'test/break_esp_hw_support_static_analyzer_issues' into 'master'
change(hw_support): temporarily ignore gcc static analyzer issues Closes IDF-10229 See merge request espressif/esp-idf!31727
2 parents 69da130 + b1dee4e commit f0bd096

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+57
-57
lines changed

4 files changed

+57
-57
lines changed

‎components/esp_hw_support/CMakeLists.txt

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -163,10 +163,6 @@ idf_build_get_property(target IDF_TARGET)
163163
add_subdirectory(port/${target})
164164
add_subdirectory(lowpower)
165165

166-
if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10229
167-
target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-analyzer")
168-
endif()
169-
170166
if(CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND OR CONFIG_PM_SLP_DISABLE_GPIO)
171167
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_sleep_gpio_include")
172168
endif()

‎components/esp_hw_support/port/regdma_link.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include "esp_heap_caps.h"
1616
#include "esp_log.h"
1717
#include "esp_regdma.h"
18+
#include "esp_compiler.h"
1819

1920

2021

@@ -419,6 +420,7 @@ static void * regdma_link_get_instance(void *link)
419420

420421
return container_memaddr[it];
421422
}
423+
ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-null-dereference") // TODO IDF-11384
422424
static regdma_link_stats_t * regdma_link_get_stats(void *link)
423425
{
424426
const static size_t stats_offset[] = {
@@ -437,6 +439,7 @@ static regdma_link_stats_t * regdma_link_get_stats(void *link)
437439

438440
return (regdma_link_stats_t *)(regdma_link_get_instance(link) + stats_offset[it]);
439441
}
442+
ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-null-dereference")
440443

441444
static void regdma_link_update_stats_wrapper(void *link, int entry, int depth)
442445
{

‎components/esp_hw_support/sleep_modes.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212

1313
#include "esp_attr.h"
1414
#include "esp_rom_caps.h"
15+
#include "esp_macros.h"
1516
#include "esp_memory_utils.h"
1617
#include "esp_sleep.h"
1718
#include "esp_private/esp_sleep_internal.h"
@@ -1215,9 +1216,7 @@ static esp_err_t IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection)
12151216
} else {
12161217
// Because RTC is in a slower clock domain than the CPU, it
12171218
// can take several CPU cycles for the sleep mode to start.
1218-
while (1) {
1219-
;
1220-
}
1219+
ESP_INFINITE_LOOP();
12211220
}
12221221
// Never returns here, except that the sleep is rejected.
12231222
esp_ipc_isr_stall_resume();

‎components/hal/esp32h2/include/hal/uart_ll.h

Lines changed: 52 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -94,14 +94,14 @@ typedef enum {
9494
*/
9595
FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
9696
{
97-
uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
98-
(uart_num == 1) ? PCR_UART1_CONF_REG : 0);
99-
uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
100-
(uart_num == 1) ? PCR_UART1_RST_EN : 0);
101-
uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN :
102-
(uart_num == 1) ? PCR_UART1_CLK_EN : 0);
103-
return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
104-
REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
97+
switch (uart_num) {
98+
case 0:
99+
return PCR.uart0_conf.uart0_clk_en && !PCR.uart0_conf.uart0_rst_en;
100+
case 1:
101+
return PCR.uart1_conf.uart1_clk_en && !PCR.uart1_conf.uart1_rst_en;
102+
default:
103+
return false;
104+
}
105105
}
106106

107107
/**
@@ -194,18 +194,18 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
194194
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
195195
{
196196
switch (source_clk) {
197-
case UART_SCLK_PLL_F48M:
198-
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1);
199-
break;
200-
case UART_SCLK_RTC:
201-
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2);
202-
break;
203-
case UART_SCLK_XTAL:
204-
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3);
205-
break;
206-
default:
207-
// Invalid UART clock source
208-
abort();
197+
case UART_SCLK_PLL_F48M:
198+
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1);
199+
break;
200+
case UART_SCLK_RTC:
201+
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2);
202+
break;
203+
case UART_SCLK_XTAL:
204+
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3);
205+
break;
206+
default:
207+
// Invalid UART clock source
208+
abort();
209209
}
210210
}
211211

@@ -220,16 +220,16 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
220220
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
221221
{
222222
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
223-
default:
224-
case 1:
225-
*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M;
226-
break;
227-
case 2:
228-
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
229-
break;
230-
case 3:
231-
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
232-
break;
223+
default:
224+
case 1:
225+
*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M;
226+
break;
227+
case 2:
228+
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
229+
break;
230+
case 3:
231+
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
232+
break;
233233
}
234234
}
235235

@@ -248,7 +248,9 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
248248
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
249249
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
250250

251-
if (sclk_div == 0) abort();
251+
if (sclk_div == 0) {
252+
abort();
253+
}
252254

253255
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
254256
// The baud rate configuration register is divided into
@@ -844,22 +846,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
844846
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
845847
{
846848
switch (mode) {
847-
default:
848-
case UART_MODE_UART:
849-
uart_ll_set_mode_normal(hw);
850-
break;
851-
case UART_MODE_RS485_COLLISION_DETECT:
852-
uart_ll_set_mode_collision_detect(hw);
853-
break;
854-
case UART_MODE_RS485_APP_CTRL:
855-
uart_ll_set_mode_rs485_app_ctrl(hw);
856-
break;
857-
case UART_MODE_RS485_HALF_DUPLEX:
858-
uart_ll_set_mode_rs485_half_duplex(hw);
859-
break;
860-
case UART_MODE_IRDA:
861-
uart_ll_set_mode_irda(hw);
862-
break;
849+
default:
850+
case UART_MODE_UART:
851+
uart_ll_set_mode_normal(hw);
852+
break;
853+
case UART_MODE_RS485_COLLISION_DETECT:
854+
uart_ll_set_mode_collision_detect(hw);
855+
break;
856+
case UART_MODE_RS485_APP_CTRL:
857+
uart_ll_set_mode_rs485_app_ctrl(hw);
858+
break;
859+
case UART_MODE_RS485_HALF_DUPLEX:
860+
uart_ll_set_mode_rs485_half_duplex(hw);
861+
break;
862+
case UART_MODE_IRDA:
863+
uart_ll_set_mode_irda(hw);
864+
break;
863865
}
864866
}
865867

@@ -957,7 +959,7 @@ FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
957959
{
958960
hw->swfc_conf0_sync.force_xon = 1;
959961
uart_ll_update(hw);
960-
if(!always_on) {
962+
if (!always_on) {
961963
hw->swfc_conf0_sync.force_xon = 0;
962964
uart_ll_update(hw);
963965
}
@@ -1003,7 +1005,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
10031005
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
10041006
{
10051007
uint16_t tout_val = tout_thrd;
1006-
if(tout_thrd > 0) {
1008+
if (tout_thrd > 0) {
10071009
hw->tout_conf_sync.rx_tout_thrhd = tout_val;
10081010
hw->tout_conf_sync.rx_tout_en = 1;
10091011
} else {
@@ -1022,7 +1024,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
10221024
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
10231025
{
10241026
uint16_t tout_thrd = 0;
1025-
if(hw->tout_conf_sync.rx_tout_en > 0) {
1027+
if (hw->tout_conf_sync.rx_tout_en > 0) {
10261028
tout_thrd = hw->tout_conf_sync.rx_tout_thrhd;
10271029
}
10281030
return tout_thrd;

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