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author
Jiang Jiang Jian
committed
Merge branch 'fix/esp32p4_lightsleep_fixes_v5.4' into 'release/v5.4'
fix(esp_hw_support): some fixes of esp32p4 lightsleep retention & power switch process (v5.4) See merge request espressif/esp-idf!37086
2 parents e9285cc + b654a78 commit f9ae8df

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15 files changed

+113
-103
lines changed

15 files changed

+113
-103
lines changed

‎components/esp_hw_support/include/esp_private/esp_pmu.h

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -279,11 +279,6 @@ void pmu_sleep_increase_ldo_volt(void);
279279
* power in the sleep and wake-up processes.
280280
*/
281281
void pmu_sleep_shutdown_dcdc(void);
282-
283-
/**
284-
* @brief DCDC has taken over power supply, shut down LDO to save power consumption
285-
*/
286-
void pmu_sleep_shutdown_ldo(void);
287282
#endif // SOC_DCDC_SUPPORTED
288283

289284
/**

‎components/esp_hw_support/lowpower/port/esp32p4/rvsleep-frames.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,7 @@ STRUCT_END(RvCoreCriticalSleepFrame)
113113
STRUCT_BEGIN
114114
STRUCT_FIELD (long, 4, RV_SLP_CTX_MSCRATCH, mscratch)
115115
STRUCT_FIELD (long, 4, RV_SLP_CTX_MISA, misa)
116+
STRUCT_FIELD (long, 4, RV_SLP_CTX_MHCR, mhcr)
116117
STRUCT_FIELD (long, 4, RV_SLP_CTX_TSELECT, tselect)
117118
STRUCT_FIELD (long, 4, RV_SLP_CTX_TDATA1, tdata1)
118119
STRUCT_FIELD (long, 4, RV_SLP_CTX_TDATA2, tdata2)

‎components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c

Lines changed: 8 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@
2020
#include "freertos/task.h"
2121
#include "esp_heap_caps.h"
2222
#include "riscv/csr.h"
23-
#include "soc/cache_reg.h"
2423
#include "soc/clic_reg.h"
2524
#include "soc/rtc_periph.h"
2625
#include "soc/soc_caps.h"
@@ -32,7 +31,6 @@
3231

3332
#include "esp32p4/rom/ets_sys.h"
3433
#include "esp32p4/rom/rtc.h"
35-
#include "esp32p4/rom/cache.h"
3634
#include "rvsleep-frames.h"
3735

3836
#if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
@@ -76,7 +74,6 @@ typedef struct {
7674
struct {
7775
RvCoreCriticalSleepFrame *critical_frame[portNUM_PROCESSORS];
7876
RvCoreNonCriticalSleepFrame *non_critical_frame[portNUM_PROCESSORS];
79-
cpu_domain_dev_sleep_frame_t *cache_config_frame;
8077
cpu_domain_dev_sleep_frame_t *clic_frame[portNUM_PROCESSORS];
8178
} retent;
8279
} sleep_cpu_retention_t;
@@ -107,15 +104,6 @@ static void * cpu_domain_dev_sleep_frame_alloc_and_init(const cpu_domain_dev_reg
107104
return frame;
108105
}
109106

110-
static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void)
111-
{
112-
const static cpu_domain_dev_regs_region_t regions[] = {
113-
{ .start = CACHE_L1_ICACHE_CTRL_REG, .end = CACHE_L1_BYPASS_CACHE_CONF_REG + 4 },
114-
{ .start = CACHE_L2_CACHE_CTRL_REG, .end = CACHE_L2_CACHE_BLOCKSIZE_CONF_REG + 4 }
115-
};
116-
return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0]));
117-
}
118-
119107
static inline void * cpu_domain_clic_sleep_frame_alloc_and_init(uint8_t core_id)
120108
{
121109
const static cpu_domain_dev_regs_region_t regions[portNUM_PROCESSORS][2] = {
@@ -146,13 +134,6 @@ static esp_err_t esp_sleep_cpu_retention_init_impl(void)
146134
s_cpu_retention.retent.non_critical_frame[core_id] = (RvCoreNonCriticalSleepFrame *)frame;
147135
}
148136
}
149-
if (s_cpu_retention.retent.cache_config_frame == NULL) {
150-
void *frame = cpu_domain_cache_config_sleep_frame_alloc_and_init();
151-
if (frame == NULL) {
152-
goto err;
153-
}
154-
s_cpu_retention.retent.cache_config_frame = (cpu_domain_dev_sleep_frame_t *)frame;
155-
}
156137
for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {
157138
if (s_cpu_retention.retent.clic_frame[core_id] == NULL) {
158139
void *frame = cpu_domain_clic_sleep_frame_alloc_and_init(core_id);
@@ -186,10 +167,6 @@ static esp_err_t esp_sleep_cpu_retention_deinit_impl(void)
186167
s_cpu_retention.retent.non_critical_frame[core_id] = NULL;
187168
}
188169
}
189-
if (s_cpu_retention.retent.cache_config_frame) {
190-
heap_caps_free((void *)s_cpu_retention.retent.cache_config_frame);
191-
s_cpu_retention.retent.cache_config_frame = NULL;
192-
}
193170
for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {
194171
if (s_cpu_retention.retent.clic_frame[core_id]) {
195172
heap_caps_free((void *)s_cpu_retention.retent.clic_frame[core_id]);
@@ -215,6 +192,7 @@ static TCM_IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save
215192

216193
frame->mscratch = RV_READ_CSR(mscratch);
217194
frame->misa = RV_READ_CSR(misa);
195+
frame->mhcr = RV_READ_CSR(MHCR);
218196
frame->tselect = RV_READ_CSR(tselect);
219197
frame->tdata1 = RV_READ_CSR(tdata1);
220198
frame->tdata2 = RV_READ_CSR(tdata2);
@@ -283,6 +261,7 @@ static TCM_IRAM_ATTR void rv_core_noncritical_regs_restore(void)
283261

284262
RV_WRITE_CSR(mscratch, frame->mscratch);
285263
RV_WRITE_CSR(misa, frame->misa);
264+
RV_WRITE_CSR(MHCR, frame->mhcr);
286265
RV_WRITE_CSR(tselect, frame->tselect);
287266
RV_WRITE_CSR(tdata1, frame->tdata1);
288267
RV_WRITE_CSR(tdata2, frame->tdata2);
@@ -403,6 +382,8 @@ static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
403382
uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
404383
{
405384
uint8_t core_id = esp_cpu_get_core_id();
385+
/* mstatus is core privated CSR, do it near the core critical regs restore */
386+
uint32_t mstatus = save_mstatus_and_disable_global_int();
406387
rv_core_critical_regs_save();
407388

408389
RvCoreCriticalSleepFrame * frame = s_cpu_retention.retent.critical_frame[core_id];
@@ -428,21 +409,19 @@ static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
428409
validate_retention_frame_crc((uint32_t*)frame, RV_SLEEP_CTX_SZ1 - 2 * sizeof(long), (uint32_t *)(&frame->frame_crc));
429410
}
430411
#endif
431-
412+
restore_mstatus(mstatus);
432413
return pmu_sleep_finish(dslp);
433414
}
434415

435416
esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uint32_t, uint32_t, bool),
436417
uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
437418
{
438419
esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_START, (void *)0);
439-
uint32_t mstatus = save_mstatus_and_disable_global_int();
440420
uint8_t core_id = esp_cpu_get_core_id();
441421
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
442422
atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_START);
443423
#endif
444424
cpu_domain_dev_regs_save(s_cpu_retention.retent.clic_frame[core_id]);
445-
cpu_domain_dev_regs_save(s_cpu_retention.retent.cache_config_frame);
446425
rv_core_noncritical_regs_save();
447426

448427
#if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
@@ -467,10 +446,8 @@ esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t,
467446
atomic_store(&s_smp_retention_state[core_id], SMP_RESTORE_START);
468447
#endif
469448

470-
rv_core_noncritical_regs_restore();
471-
cpu_domain_dev_regs_restore(s_cpu_retention.retent.cache_config_frame);
472449
cpu_domain_dev_regs_restore(s_cpu_retention.retent.clic_frame[core_id]);
473-
restore_mstatus(mstatus);
450+
rv_core_noncritical_regs_restore();
474451

475452
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
476453
atomic_store(&s_smp_retention_state[core_id], SMP_RESTORE_DONE);
@@ -495,7 +472,6 @@ bool cpu_domain_pd_allowed(void)
495472
allowed &= (s_cpu_retention.retent.critical_frame[core_id] != NULL);
496473
allowed &= (s_cpu_retention.retent.non_critical_frame[core_id] != NULL);
497474
}
498-
allowed &= (s_cpu_retention.retent.cache_config_frame != NULL);
499475
for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {
500476
allowed &= (s_cpu_retention.retent.clic_frame[core_id] != NULL);
501477
}
@@ -544,6 +520,7 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void)
544520
atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_START);
545521
rv_core_noncritical_regs_save();
546522
cpu_domain_dev_regs_save(s_cpu_retention.retent.clic_frame[core_id]);
523+
uint32_t mstatus = save_mstatus_and_disable_global_int();
547524
rv_core_critical_regs_save();
548525
RvCoreCriticalSleepFrame *frame_critical = s_cpu_retention.retent.critical_frame[core_id];
549526
if ((frame_critical->pmufunc & 0x3) == 0x1) {
@@ -563,6 +540,7 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void)
563540
REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL);
564541
}
565542
atomic_store(&s_smp_retention_state[core_id], SMP_RESTORE_START);
543+
restore_mstatus(mstatus);
566544
cpu_domain_dev_regs_restore(s_cpu_retention.retent.clic_frame[core_id]);
567545
rv_core_noncritical_regs_restore();
568546
atomic_store(&s_smp_retention_state[core_id], SMP_RESTORE_DONE);

‎components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_asm.S

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -149,31 +149,6 @@ _rv_core_critical_regs_restore: /* export a strong symbol to jump to here, used
149149
nop
150150

151151
rv_core_critical_regs_restore:
152-
/* Invalidate L1 Cache by Core 0*/
153-
csrr t0, mhartid
154-
bnez t0, start_restore
155-
/* Core 0 is wakeup core, Invalidate L1 Cache here */
156-
/* Invalidate L1 cache is required here!!! */
157-
la t0, CACHE_SYNC_MAP_REG
158-
li t1, CACHE_MAP_L1_CACHE_MASK /* map l1 i/dcache */
159-
sw t1, 0x0(t0) /* set EXTMEM_CACHE_SYNC_MAP_REG bit 4 */
160-
la t2, CACHE_SYNC_ADDR_REG
161-
sw zero, 0x0(t2) /* clear EXTMEM_CACHE_SYNC_ADDR_REG */
162-
la t0, CACHE_SYNC_SIZE_REG
163-
sw zero, 0x0(t0) /* clear EXTMEM_CACHE_SYNC_SIZE_REG */
164-
165-
la t1, CACHE_SYNC_CTRL_REG
166-
lw t2, 0x0(t1)
167-
ori t2, t2, 0x1
168-
sw t2, 0x0(t1)
169-
170-
li t0, 0x10 /* SYNC_DONE bit */
171-
wait_cache_sync_done1:
172-
lw t2, 0x0(t1)
173-
and t2, t0, t2
174-
beqz t2, wait_cache_sync_done1
175-
176-
start_restore:
177152
la t0, rv_core_critical_regs_frame
178153
csrr t1, mhartid
179154
slli t1, t1, 2

‎components/esp_hw_support/port/esp32p4/pmu_init.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -149,8 +149,8 @@ static inline void pmu_power_domain_force_default(pmu_context_t *ctx)
149149
pmu_ll_lp_set_power_force_power_down(ctx->hal->dev, false);
150150
pmu_ll_lp_set_power_force_isolate (ctx->hal->dev, false);
151151
pmu_ll_lp_set_power_force_reset (ctx->hal->dev, false);
152-
pmu_ll_set_dcdc_force_power_up(ctx->hal->dev, false);
153-
pmu_ll_set_dcdc_force_power_down(ctx->hal->dev, false);
152+
pmu_ll_set_dcdc_switch_force_power_up(ctx->hal->dev, false);
153+
pmu_ll_set_dcdc_switch_force_power_down(ctx->hal->dev, false);
154154
}
155155

156156
static inline void pmu_hp_system_param_default(pmu_hp_mode_t mode, pmu_hp_system_param_t *param)

‎components/esp_hw_support/port/esp32p4/pmu_sleep.c

Lines changed: 27 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -338,21 +338,31 @@ void pmu_sleep_increase_ldo_volt(void) {
338338
}
339339

340340
void pmu_sleep_shutdown_dcdc(void) {
341-
SET_PERI_REG_MASK(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_DCDC_SWITCH); //0: enable, 1: disable
342-
REG_SET_BIT(PMU_DCM_CTRL_REG, PMU_DCDC_OFF_REQ);
341+
pmu_ll_set_dcdc_switch_force_power_down(&PMU, true);
342+
pmu_ll_set_dcdc_en(&PMU, false);
343343
// Decrease hp_ldo voltage.
344344
pmu_ll_hp_set_regulator_dbias(&PMU, PMU_MODE_HP_ACTIVE, HP_CALI_ACTIVE_DBIAS_DEFAULT);
345345
}
346346

347-
void pmu_sleep_enable_dcdc(void) {
348-
CLEAR_PERI_REG_MASK(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_DCDC_SWITCH); //0: enable, 1: disable
349-
SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_ON_REQ);
350-
REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCM_VSET, HP_CALI_ACTIVE_DCM_VSET_DEFAULT);
347+
FORCE_INLINE_ATTR void pmu_sleep_enable_dcdc(void) {
348+
pmu_ll_set_dcdc_switch_force_power_down(&PMU, false);
349+
pmu_ll_set_dcdc_en(&PMU, true);
350+
pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, HP_CALI_ACTIVE_DCM_VSET_DEFAULT);
351351
}
352352

353-
void pmu_sleep_shutdown_ldo(void) {
354-
CLEAR_PERI_REG_MASK(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_DCDC_SWITCH); //0: enable, 1: disable
355-
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD);
353+
FORCE_INLINE_ATTR void pmu_sleep_shutdown_ldo(void) {
354+
pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, 0);
355+
}
356+
357+
FORCE_INLINE_ATTR void pmu_sleep_cache_sync_items(uint32_t gid, uint32_t type, uint32_t map, uint32_t addr, uint32_t bytes)
358+
{
359+
REG_WRITE(CACHE_SYNC_ADDR_REG, addr);
360+
REG_WRITE(CACHE_SYNC_SIZE_REG, bytes);
361+
REG_WRITE(CACHE_SYNC_MAP_REG, map);
362+
REG_SET_FIELD(CACHE_SYNC_CTRL_REG, CACHE_SYNC_RGID, gid);
363+
REG_SET_BIT(CACHE_SYNC_CTRL_REG, type);
364+
while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE))
365+
;
356366
}
357367

358368
static TCM_DRAM_ATTR uint32_t s_mpll_freq_mhz_before_sleep = 0;
@@ -369,11 +379,12 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
369379
pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
370380
pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
371381

372-
// For the sleep where powered down the TOP domain, the L1 cache data memory will be lost and needs to be written back here.
373-
// For the sleep without power down the TOP domain, regdma retention may still be enabled, and dirty data in the L1 cache needs
374-
// to be written back so that regdma can get the correct link. So we always need to write back to L1 DCache here.
375-
// !!! Need to manually check that data in L2 memory will not be modified from now on. !!!
376-
Cache_WriteBack_All(CACHE_MAP_L1_DCACHE);
382+
// 1. For the sleep where powered down the TOP domain, the L1 cache data memory will be lost and needs to be written back here.
383+
// 2. For the sleep without power down the TOP domain, regdma retention may still be enabled, and dirty data in the L1 cache needs
384+
// to be written back so that regdma can get the correct link.
385+
// 3. We cannot use the API provided by ROM to invalidate the cache, since it is a function calling that writes data to the stack during
386+
// the return process, which results in dirty cachelines in L1 Cache again.
387+
pmu_sleep_cache_sync_items(SMMU_GID_DEFAULT, CACHE_SYNC_WRITEBACK, CACHE_MAP_L1_DCACHE, 0, 0);
377388

378389
#if CONFIG_SPIRAM
379390
psram_ctrlr_ll_wait_all_transaction_done();
@@ -434,10 +445,10 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
434445
#endif
435446
{
436447
pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, HP_CALI_ACTIVE_DCM_VSET_DEFAULT);
448+
pmu_sleep_enable_dcdc();
437449
if (pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev)) {
438450
// If sleep is rejected, the hardware wake-up process that turns on DCDC
439-
// is skipped, and software is used to enable DCDC here.
440-
pmu_sleep_enable_dcdc();
451+
// is skipped, and wait DCDC volt rise up by software here.
441452
esp_rom_delay_us(950);
442453
}
443454
pmu_sleep_shutdown_ldo();

‎components/esp_hw_support/port/esp32p4/rtc_clk_init.c

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -54,14 +54,13 @@ void rtc_clk_init(rtc_clk_config_t cfg)
5454
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_OR_FORCE_XPD_IPH, 0);
5555
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_OR_FORCE_XPD_VGATE_BUF, 0);
5656

57-
REG_SET_FIELD(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, LP_CALI_DBIAS);
58-
57+
pmu_ll_lp_set_regulator_dbias(&PMU, PMU_MODE_LP_ACTIVE, LP_CALI_DBIAS);
5958
// Switch to DCDC
60-
SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_ON_REQ);
61-
CLEAR_PERI_REG_MASK(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_DCDC_SWITCH); //0: enable, 1: disable
62-
REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCM_VSET, HP_CALI_ACTIVE_DCM_VSET_DEFAULT);
59+
pmu_ll_set_dcdc_en(&PMU, true);
60+
pmu_ll_set_dcdc_switch_force_power_down(&PMU, false);
61+
pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, HP_CALI_ACTIVE_DCM_VSET_DEFAULT);
6362
esp_rom_delay_us(1000);
64-
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD);
63+
pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, false);
6564

6665
soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
6766
esp_rom_output_tx_wait_idle(0);

‎components/esp_hw_support/sleep_system_peripheral.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -101,11 +101,11 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_systimer_retention_ini
101101
return ESP_OK;
102102
}
103103

104-
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
105-
esp_err_t sleep_sys_periph_l2_cache_retention_init(void)
104+
#if SOC_PM_CACHE_RETENTION_BY_PAU
105+
esp_err_t sleep_sys_periph_cache_retention_init(void)
106106
{
107-
esp_err_t err = sleep_retention_entries_create(l2_cache_regs_retention, ARRAY_SIZE(l2_cache_regs_retention), REGDMA_LINK_PRI_SYS_PERIPH_HIGH, SLEEP_RETENTION_MODULE_SYS_PERIPH);
108-
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for digital peripherals (L2 Cache) retention");
107+
esp_err_t err = sleep_retention_entries_create(cache_regs_retention, ARRAY_SIZE(cache_regs_retention), REGDMA_LINK_PRI_SYS_PERIPH_HIGH, SLEEP_RETENTION_MODULE_SYS_PERIPH);
108+
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for digital peripherals (Cache) retention");
109109
ESP_LOGI(TAG, "L2 Cache sleep retention initialization");
110110
return ESP_OK;
111111
}
@@ -128,8 +128,8 @@ static __attribute__((unused)) esp_err_t sleep_sys_periph_retention_init(void *a
128128
if(err) goto error;
129129
err = sleep_sys_periph_hp_system_retention_init(arg);
130130
if(err) goto error;
131-
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
132-
err = sleep_sys_periph_l2_cache_retention_init();
131+
#if SOC_PM_CACHE_RETENTION_BY_PAU
132+
err = sleep_sys_periph_cache_retention_init();
133133
if(err) goto error;
134134
#endif
135135
#if SOC_APM_SUPPORTED

‎components/esp_rom/esp32p4/include/esp32p4/rom/cache.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -231,6 +231,7 @@ typedef enum {
231231
#define CACHE_MAP_L2_CACHE BIT(5)
232232

233233
#define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1)
234+
#define CACHE_MAP_L1_CACHE_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE)
234235
#define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE)
235236

236237
struct cache_internal_stub_table {

‎components/hal/esp32p4/include/hal/pmu_ll.h

Lines changed: 14 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -663,16 +663,27 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *
663663
return hw->power.wait_timer0.powerup_timer;
664664
}
665665

666-
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_force_power_up(pmu_dev_t *hw, bool fpu)
666+
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_switch_force_power_up(pmu_dev_t *hw, bool fpu)
667667
{
668+
hw->power.dcdc_switch.force_pd = 0;
668669
hw->power.dcdc_switch.force_pu = fpu;
669670
}
670671

671-
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_force_power_down(pmu_dev_t *hw, bool fpd)
672+
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_switch_force_power_down(pmu_dev_t *hw, bool fpd)
672673
{
674+
hw->power.dcdc_switch.force_pu = 0;
673675
hw->power.dcdc_switch.force_pd = fpd;
674676
}
675677

678+
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_en(pmu_dev_t *hw, bool en)
679+
{
680+
if (en) {
681+
hw->dcm_ctrl.on_req = 1;
682+
} else {
683+
hw->dcm_ctrl.off_req = 1;
684+
}
685+
}
686+
676687
/**
677688
* @brief Get ext1 wakeup source status
678689
* @return The lower 8 bits of the returned value are the bitmap of

‎components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1923,6 +1923,10 @@ config SOC_PM_CPU_RETENTION_BY_SW
19231923
bool
19241924
default y
19251925

1926+
config SOC_PM_CACHE_RETENTION_BY_PAU
1927+
bool
1928+
default y
1929+
19261930
config SOC_PM_PAU_LINK_NUM
19271931
int
19281932
default 4

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