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maximdimakovmaximdimakov
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[SYCL] Replace using of ONEAPI/INTEL namespaces with ext::oneapi/intel (#442)
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117 files changed

+384
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lines changed

‎SYCL/AOT/spec_const_aot.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,8 @@ int main(int argc, char **argv) {
3636
<< "\n";
3737
cl::sycl::program prog(q.get_context());
3838

39-
cl::sycl::ONEAPI::experimental::spec_constant<int32_t, MyInt32Const> i32 =
40-
prog.set_spec_constant<MyInt32Const>(10);
39+
cl::sycl::ext::oneapi::experimental::spec_constant<int32_t, MyInt32Const>
40+
i32 = prog.set_spec_constant<MyInt32Const>(10);
4141

4242
prog.build_with_kernel_type<Kernel>();
4343

‎SYCL/AtomicRef/accessor.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
#include <numeric>
1111
#include <vector>
1212
using namespace sycl;
13-
using namespace sycl::ONEAPI;
13+
using namespace sycl::ext::oneapi;
1414

1515
// Equivalent to add_test from add.cpp
1616
// Uses atomic_accessor instead of atomic_ref

‎SYCL/AtomicRef/assignment.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ template <typename T> void assignment_test(queue q, size_t N) {
2121
assignment_buf.template get_access<access::mode::read_write>(cgh);
2222
cgh.parallel_for<assignment_kernel<T>>(range<1>(N), [=](item<1> it) {
2323
size_t gid = it.get_id(0);
24-
auto atm = atomic_ref<T, ONEAPI::memory_order::relaxed,
25-
ONEAPI::memory_scope::device,
24+
auto atm = atomic_ref<T, ext::oneapi::memory_order::relaxed,
25+
ext::oneapi::memory_scope::device,
2626
access::address_space::global_space>(st[0]);
2727
atm = T(gid);
2828
});

‎SYCL/Basic/enqueue_barrier.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
// UNSUPPORTED: cuda || windows
99

1010
#include <CL/sycl.hpp>
11-
#include <CL/sycl/INTEL/fpga_device_selector.hpp>
11+
#include <sycl/ext/intel/fpga_device_selector.hpp>
1212

1313
int main() {
1414
sycl::context Context;

‎SYCL/Basic/fpga_tests/buffer_location.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@ int main() {
88
sycl::buffer<int, 1> Buf{sycl::range{1}};
99

1010
Queue.submit([&](sycl::handler &CGH) {
11-
sycl::ONEAPI::accessor_property_list PL{sycl::INTEL::buffer_location<1>};
11+
sycl::ext::oneapi::accessor_property_list PL{
12+
sycl::ext::intel::buffer_location<1>};
1213
sycl::accessor Acc(Buf, CGH, sycl::write_only, PL);
1314
CGH.single_task<class Test>([=]() { Acc[0] = 42; });
1415
});

‎SYCL/Basic/fpga_tests/fpga_io_pipes.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@
88
//
99
//===----------------------------------------------------------------------===//
1010
#include <CL/sycl.hpp>
11-
#include <CL/sycl/INTEL/fpga_extensions.hpp>
1211
#include <fstream>
1312
#include <iostream>
13+
#include <sycl/ext/intel/fpga_extensions.hpp>
1414

1515
#include "io_pipe_def.h"
1616

@@ -113,11 +113,11 @@ int test_io_bl_pipe(cl::sycl::queue Queue) {
113113
}
114114

115115
int main() {
116-
cl::sycl::queue Queue{cl::sycl::INTEL::fpga_emulator_selector{}};
116+
cl::sycl::queue Queue{cl::sycl::ext::intel::fpga_emulator_selector{}};
117117

118118
if (!Queue.get_device()
119119
.get_info<cl::sycl::info::device::kernel_kernel_pipe_support>()) {
120-
std::cout << "SYCL_INTEL_data_flow_pipes not supported, skipping"
120+
std::cout << "SYCL_ext_intel_data_flow_pipes not supported, skipping"
121121
<< std::endl;
122122
return 0;
123123
}

‎SYCL/Basic/fpga_tests/fpga_lsu.cpp

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
//
99
//===----------------------------------------------------------------------===//
1010
#include <CL/sycl.hpp>
11-
#include <CL/sycl/INTEL/fpga_extensions.hpp>
11+
#include <sycl/ext/intel/fpga_extensions.hpp>
1212

1313
// TODO: run is disabled, since no support added in FPGA backend yet. Check
1414
// implementation correctness from CXX and SYCL languages perspective.
@@ -38,20 +38,20 @@ int test_lsu(cl::sycl::queue Queue) {
3838
auto input_ptr = input_accessor.get_pointer();
3939
auto output_ptr = output_accessor.get_pointer();
4040

41-
using PrefetchingLSU =
42-
cl::sycl::INTEL::lsu<cl::sycl::INTEL::prefetch<true>,
43-
cl::sycl::INTEL::statically_coalesce<false>>;
41+
using PrefetchingLSU = cl::sycl::ext::intel::lsu<
42+
cl::sycl::ext::intel::prefetch<true>,
43+
cl::sycl::ext::intel::statically_coalesce<false>>;
4444

45-
using BurstCoalescedLSU =
46-
cl::sycl::INTEL::lsu<cl::sycl::INTEL::burst_coalesce<true>,
47-
cl::sycl::INTEL::statically_coalesce<false>>;
45+
using BurstCoalescedLSU = cl::sycl::ext::intel::lsu<
46+
cl::sycl::ext::intel::burst_coalesce<true>,
47+
cl::sycl::ext::intel::statically_coalesce<false>>;
4848

49-
using CachingLSU =
50-
cl::sycl::INTEL::lsu<cl::sycl::INTEL::burst_coalesce<true>,
51-
cl::sycl::INTEL::cache<1024>,
52-
cl::sycl::INTEL::statically_coalesce<false>>;
49+
using CachingLSU = cl::sycl::ext::intel::lsu<
50+
cl::sycl::ext::intel::burst_coalesce<true>,
51+
cl::sycl::ext::intel::cache<1024>,
52+
cl::sycl::ext::intel::statically_coalesce<false>>;
5353

54-
using PipelinedLSU = cl::sycl::INTEL::lsu<>;
54+
using PipelinedLSU = cl::sycl::ext::intel::lsu<>;
5555

5656
int X = PrefetchingLSU::load(input_ptr); // int X = input_ptr[0]
5757
int Y = CachingLSU::load(input_ptr + 1); // int Y = input_ptr[1]
@@ -74,7 +74,7 @@ int test_lsu(cl::sycl::queue Queue) {
7474
}
7575

7676
int main() {
77-
cl::sycl::queue Queue{cl::sycl::INTEL::fpga_emulator_selector{}};
77+
cl::sycl::queue Queue{cl::sycl::ext::intel::fpga_emulator_selector{}};
7878

7979
return test_lsu(Queue);
8080
}

‎SYCL/Basic/fpga_tests/fpga_pipes.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,8 @@
1212
//
1313
//===----------------------------------------------------------------------===//
1414
#include <CL/sycl.hpp>
15-
#include <CL/sycl/INTEL/fpga_extensions.hpp>
1615
#include <iostream>
16+
#include <sycl/ext/intel/fpga_extensions.hpp>
1717

1818
// Size of an array passing through a pipe
1919
constexpr size_t N = 10;
@@ -31,7 +31,7 @@ template <int N> class templ_nb_pipe;
3131

3232
// For non-blocking multiple pipes
3333
template <int N>
34-
using PipeMulNb = cl::sycl::INTEL::pipe<class templ_nb_pipe<N>, int>;
34+
using PipeMulNb = cl::sycl::ext::intel::pipe<class templ_nb_pipe<N>, int>;
3535

3636
// For simple blocking pipes with explicit type
3737
class some_bl_pipe;
@@ -46,7 +46,7 @@ template <int N> class templ_bl_pipe;
4646

4747
// For blocking multiple pipes
4848
template <int N>
49-
using PipeMulBl = cl::sycl::INTEL::pipe<class templ_bl_pipe<N>, int>;
49+
using PipeMulBl = cl::sycl::ext::intel::pipe<class templ_bl_pipe<N>, int>;
5050

5151
// Kernel names
5252
template <int TestNumber, int KernelNumber = 0> class writer;
@@ -57,7 +57,7 @@ template <typename PipeName, int TestNumber>
5757
int test_simple_nb_pipe(cl::sycl::queue Queue) {
5858
int data[] = {0};
5959

60-
using Pipe = cl::sycl::INTEL::pipe<PipeName, int>;
60+
using Pipe = cl::sycl::ext::intel::pipe<PipeName, int>;
6161

6262
cl::sycl::buffer<int, 1> readBuf(data, 1);
6363
Queue.submit([&](cl::sycl::handler &cgh) {
@@ -146,7 +146,7 @@ template <int TestNumber> int test_multiple_nb_pipe(cl::sycl::queue Queue) {
146146
// Test for array passing through a non-blocking pipe
147147
template <int TestNumber> int test_array_th_nb_pipe(cl::sycl::queue Queue) {
148148
int data[N] = {0};
149-
using AnotherNbPipe = cl::sycl::INTEL::pipe<class another_nb_pipe, int>;
149+
using AnotherNbPipe = cl::sycl::ext::intel::pipe<class another_nb_pipe, int>;
150150

151151
Queue.submit([&](cl::sycl::handler &cgh) {
152152
cgh.single_task<class writer<TestNumber>>([=]() {
@@ -188,7 +188,7 @@ template <typename PipeName, int TestNumber>
188188
int test_simple_bl_pipe(cl::sycl::queue Queue) {
189189
int data[] = {0};
190190

191-
using Pipe = cl::sycl::INTEL::pipe<PipeName, int>;
191+
using Pipe = cl::sycl::ext::intel::pipe<PipeName, int>;
192192

193193
cl::sycl::buffer<int, 1> readBuf(data, 1);
194194
Queue.submit([&](cl::sycl::handler &cgh) {
@@ -256,7 +256,7 @@ template <int TestNumber> int test_multiple_bl_pipe(cl::sycl::queue Queue) {
256256
// Test for array passing through a blocking pipe
257257
template <int TestNumber> int test_array_th_bl_pipe(cl::sycl::queue Queue) {
258258
int data[N] = {0};
259-
using AnotherBlPipe = cl::sycl::INTEL::pipe<class another_bl_pipe, int>;
259+
using AnotherBlPipe = cl::sycl::ext::intel::pipe<class another_bl_pipe, int>;
260260

261261
Queue.submit([&](cl::sycl::handler &cgh) {
262262
cgh.single_task<class writer<TestNumber>>([=]() {
@@ -290,7 +290,7 @@ int main() {
290290

291291
if (!Queue.get_device()
292292
.get_info<cl::sycl::info::device::kernel_kernel_pipe_support>()) {
293-
std::cout << "SYCL_INTEL_data_flow_pipes not supported, skipping"
293+
std::cout << "SYCL_ext_intel_data_flow_pipes not supported, skipping"
294294
<< std::endl;
295295
return 0;
296296
}

‎SYCL/Basic/fpga_tests/global_fpga_device_selector.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,12 @@
44
// RUN: %ACC_RUN_PLACEHOLDER %t.out
55

66
#include <CL/sycl.hpp>
7-
#include <CL/sycl/INTEL/fpga_extensions.hpp>
7+
#include <sycl/ext/intel/fpga_extensions.hpp>
88

99
// Check that FPGA emulator device is found if we try to initialize inline
1010
// global variable using fpga_emulator_selector parameter.
1111

1212
inline cl::sycl::queue fpga_emu_queue_inlined{
13-
cl::sycl::INTEL::fpga_emulator_selector{}};
13+
cl::sycl::ext::intel::fpga_emulator_selector{}};
1414

1515
int main() { return 0; }

‎SYCL/Basic/fpga_tests/io_pipe_def.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
1-
#include <CL/sycl/INTEL/fpga_extensions.hpp>
1+
#include <sycl/ext/intel/fpga_extensions.hpp>
22

33
namespace intelfpga {
44
template <unsigned ID> struct ethernet_pipe_id {
55
static constexpr unsigned id = ID;
66
};
77

88
using ethernet_read_pipe =
9-
sycl::INTEL::kernel_readable_io_pipe<ethernet_pipe_id<0>, int, 0>;
9+
sycl::ext::intel::kernel_readable_io_pipe<ethernet_pipe_id<0>, int, 0>;
1010
using ethernet_write_pipe =
11-
sycl::INTEL::kernel_writeable_io_pipe<ethernet_pipe_id<1>, int, 0>;
11+
sycl::ext::intel::kernel_writeable_io_pipe<ethernet_pipe_id<1>, int, 0>;
1212
} // namespace intelfpga

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