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Create latency control E2E emulator tests
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// RUN: %clangxx -fsycl -fintelfpga %s -o %t.out
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// RUN: %ACC_RUN_PLACEHOLDER %t.out
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//==- fpga_latency_control_lsu.cpp - SYCL FPGA latency control on LSU test -==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include <CL/sycl.hpp>
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#include <sycl/ext/intel/fpga_extensions.hpp>
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using namespace sycl;
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using PrefetchingLSU = ext::intel::experimental::lsu<
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ext::intel::experimental::prefetch<true>,
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ext::intel::experimental::statically_coalesce<false>>;
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using BurstCoalescedLSU = ext::intel::experimental::lsu<
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ext::intel::experimental::burst_coalesce<true>,
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ext::intel::experimental::statically_coalesce<false>>;
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int test_latency_control(queue Queue) {
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std::vector<float> input_data = {1.23f};
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std::vector<float> output_data = {.0f};
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{
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buffer input_buffer(input_data);
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buffer output_buffer(output_data);
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Queue.submit([&](handler &cgh) {
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auto input_accessor = input_buffer.get_access<access::mode::read>(cgh);
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auto output_accessor = output_buffer.get_access<access::mode::write>(cgh);
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cgh.single_task<class kernel>([=] {
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auto in_ptr = input_accessor.get_pointer();
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auto out_ptr = output_accessor.get_pointer();
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float value = PrefetchingLSU::load<
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ext::intel::experimental::latency_anchor_id<0>>(in_ptr);
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BurstCoalescedLSU::store<ext::intel::experimental::latency_constraint<
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0, ext::intel::experimental::type::exact, 5>>(out_ptr, value);
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});
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});
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}
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if (output_data[0] != input_data[0]) {
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std::cout << "Unexpected read from output_data: " << output_data[0]
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<< ", v.s. expected " << input_data[0] << std::endl;
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return -1;
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}
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return 0;
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}
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int main() {
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queue Queue{ext::intel::fpga_emulator_selector{}};
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return test_latency_control(Queue);
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}
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// RUN: %clangxx -fsycl -fintelfpga %s -o %t.out
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// RUN: %ACC_RUN_PLACEHOLDER %t.out
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//== fpga_latency_control_pipe.cpp - SYCL FPGA latency control on pipe test ==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include <CL/sycl.hpp>
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#include <sycl/ext/intel/fpga_extensions.hpp>
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using namespace sycl;
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using Pipe1 = ext::intel::experimental::pipe<class PipeClass1, int, 8>;
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using Pipe2 = ext::intel::experimental::pipe<class PipeClass2, int, 8>;
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int test_latency_control(queue Queue) {
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std::vector<int> input_data = {1};
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std::vector<int> output_data = {0};
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{
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buffer input_buffer(input_data);
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buffer output_buffer(output_data);
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Queue.submit([&](handler &cgh) {
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auto input_accessor = input_buffer.get_access<access::mode::read>(cgh);
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auto output_accessor = output_buffer.get_access<access::mode::write>(cgh);
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cgh.single_task<class kernel>([=] {
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Pipe1::write(input_accessor[0]);
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int value =
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Pipe1::read<ext::intel::experimental::latency_anchor_id<0>>();
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Pipe2::write<ext::intel::experimental::latency_anchor_id<1>,
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ext::intel::experimental::latency_constraint<
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0, ext::intel::experimental::type::exact, 2>>(value);
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output_accessor[0] = Pipe2::read();
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});
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});
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}
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if (output_data[0] != input_data[0]) {
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std::cout << "Unexpected read from output_data: " << output_data[0]
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<< ", v.s. expected " << input_data[0] << std::endl;
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return -1;
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}
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return 0;
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}
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int main() {
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queue Queue{ext::intel::fpga_emulator_selector{}};
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return test_latency_control(Queue);
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}

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