diff --git a/SYCL/Basic/fpga_tests/fpga_latency_control_lsu.cpp b/SYCL/Basic/fpga_tests/fpga_latency_control_lsu.cpp
new file mode 100644
index 0000000000..03e4c92355
--- /dev/null
+++ b/SYCL/Basic/fpga_tests/fpga_latency_control_lsu.cpp
@@ -0,0 +1,63 @@
+// REQUIRES: aoc, accelerator
+// RUN: %clangxx -fsycl -fintelfpga %s -o %t.out
+// RUN: %ACC_RUN_PLACEHOLDER %t.out
+//==- fpga_latency_control_lsu.cpp - SYCL FPGA latency control on LSU test -==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+#include <CL/sycl.hpp>
+#include <sycl/ext/intel/fpga_extensions.hpp>
+
+using namespace sycl;
+
+using PrefetchingLSU = ext::intel::experimental::lsu<
+    ext::intel::experimental::prefetch<true>,
+    ext::intel::experimental::statically_coalesce<false>>;
+
+using BurstCoalescedLSU = ext::intel::experimental::lsu<
+    ext::intel::experimental::burst_coalesce<true>,
+    ext::intel::experimental::statically_coalesce<false>>;
+
+int test_latency_control(queue Queue) {
+  std::vector<float> input_data = {1.23f};
+  std::vector<float> output_data = {.0f};
+
+  {
+    buffer input_buffer(input_data);
+    buffer output_buffer(output_data);
+
+    Queue.submit([&](handler &cgh) {
+      auto input_accessor = input_buffer.get_access<access::mode::read>(cgh);
+
+      auto output_accessor = output_buffer.get_access<access::mode::write>(cgh);
+
+      cgh.single_task<class kernel>([=] {
+        auto in_ptr = input_accessor.get_pointer();
+        auto out_ptr = output_accessor.get_pointer();
+
+        float value = PrefetchingLSU::load<
+            ext::intel::experimental::latency_anchor_id<0>>(in_ptr);
+
+        BurstCoalescedLSU::store<ext::intel::experimental::latency_constraint<
+            0, ext::intel::experimental::type::exact, 5>>(out_ptr, value);
+      });
+    });
+  }
+
+  if (output_data[0] != input_data[0]) {
+    std::cout << "Unexpected read from output_data: " << output_data[0]
+              << ", v.s. expected " << input_data[0] << std::endl;
+
+    return -1;
+  }
+  return 0;
+}
+
+int main() {
+  queue Queue{ext::intel::fpga_emulator_selector{}};
+
+  return test_latency_control(Queue);
+}
diff --git a/SYCL/Basic/fpga_tests/fpga_latency_control_pipe.cpp b/SYCL/Basic/fpga_tests/fpga_latency_control_pipe.cpp
new file mode 100644
index 0000000000..c94d4f3c48
--- /dev/null
+++ b/SYCL/Basic/fpga_tests/fpga_latency_control_pipe.cpp
@@ -0,0 +1,60 @@
+// REQUIRES: aoc, accelerator
+// RUN: %clangxx -fsycl -fintelfpga %s -o %t.out
+// RUN: %ACC_RUN_PLACEHOLDER %t.out
+//== fpga_latency_control_pipe.cpp - SYCL FPGA latency control on pipe test ==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+#include <CL/sycl.hpp>
+#include <sycl/ext/intel/fpga_extensions.hpp>
+
+using namespace sycl;
+
+using Pipe1 = ext::intel::experimental::pipe<class PipeClass1, int, 8>;
+using Pipe2 = ext::intel::experimental::pipe<class PipeClass2, int, 8>;
+
+int test_latency_control(queue Queue) {
+  std::vector<int> input_data = {1};
+  std::vector<int> output_data = {0};
+
+  {
+    buffer input_buffer(input_data);
+    buffer output_buffer(output_data);
+
+    Queue.submit([&](handler &cgh) {
+      auto input_accessor = input_buffer.get_access<access::mode::read>(cgh);
+
+      auto output_accessor = output_buffer.get_access<access::mode::write>(cgh);
+
+      cgh.single_task<class kernel>([=] {
+        Pipe1::write(input_accessor[0]);
+
+        int value =
+            Pipe1::read<ext::intel::experimental::latency_anchor_id<0>>();
+
+        Pipe2::write<ext::intel::experimental::latency_anchor_id<1>,
+                     ext::intel::experimental::latency_constraint<
+                         0, ext::intel::experimental::type::exact, 2>>(value);
+
+        output_accessor[0] = Pipe2::read();
+      });
+    });
+  }
+
+  if (output_data[0] != input_data[0]) {
+    std::cout << "Unexpected read from output_data: " << output_data[0]
+              << ", v.s. expected " << input_data[0] << std::endl;
+
+    return -1;
+  }
+  return 0;
+}
+
+int main() {
+  queue Queue{ext::intel::fpga_emulator_selector{}};
+
+  return test_latency_control(Queue);
+}