From 440645cb3d27eabbb4788c77318dd913fc3935e3 Mon Sep 17 00:00:00 2001 From: Dmitry Sidorov Date: Fri, 8 May 2020 12:33:43 +0300 Subject: [PATCH 1/5] [SYCL] Deny support of SPV_INTEL_usm_storage_classes for all targets but FPGA Disable SPV_INTEL_usm_storage_classes by default since it adds new storage classes that represent global_device and global_host address spaces, which are not supported for all targets. With the extension disabled the storage classes will be lowered to CrossWorkgroup storage class that is mapped to just global address space. The extension is enabled only for FPGA with a flag 'enable-usm-address-spaces' passed to the driver. Signed-off-by: Dmitry Sidorov --- clang/include/clang/Driver/Options.td | 3 +++ clang/lib/Driver/ToolChains/Clang.cpp | 12 +++++++++++- clang/test/Driver/sycl-offload-intelfpga.cpp | 6 +++--- clang/test/Driver/sycl-offload.c | 4 +++- clang/test/Driver/sycl.c | 4 ++-- 5 files changed, 22 insertions(+), 7 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index b38a70a2640e9..c185e50d3b834 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -1822,6 +1822,9 @@ def fstrict_vtable_pointers: Flag<["-"], "fstrict-vtable-pointers">, def fstrict_overflow : Flag<["-"], "fstrict-overflow">, Group; def fintelfpga : Flag<["-"], "fintelfpga">, Group, Flags<[CC1Option, CoreOption]>, HelpText<"Perform ahead of time compilation for FPGA">; +def fenable_usm_address_spaces : Flag<["-"], "fenable-usm-address-spaces">, + Group, Flags<[CC1Option, CoreOption]>, + HelpText<"Add support for SPV_INTEL_usm_storage_classes feature">; def fsycl_device_only : Flag<["-"], "fsycl-device-only">, Flags<[CoreOption]>, HelpText<"Compile SYCL kernels for device">; def fsycl_targets_EQ : CommaJoined<["-"], "fsycl-targets=">, Flags<[DriverOption, CC1Option, CoreOption]>, diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 3a43682bd9ced..ff28d5e716d35 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -7642,7 +7642,17 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA, TranslatorArgs.push_back(Output.getFilename()); if (getToolChain().getTriple().isSYCLDeviceEnvironment()) { TranslatorArgs.push_back("-spirv-max-version=1.1"); - TranslatorArgs.push_back("-spirv-ext=+all"); + std::string ExtArg("-spirv-ext=+all"); + // Disable SPV_INTEL_usm_storage_classes by default since it adds new + // storage classes that represent global_device and global_host address + // spaces, which are not supported for all targets. With the extension + // disable the storage classes will be lowered to CrossWorkgroup storage + // class that is mapped to just global address space. + if (!(getToolChain().getTriple().getSubArch() == + llvm::Triple::SPIRSubArch_fpga && + TCArgs.hasArg(options::OPT_fenable_usm_address_spaces))) + ExtArg += ",-SPV_INTEL_usm_storage_classes"; + TranslatorArgs.push_back(TCArgs.MakeArgString(ExtArg)); } for (auto I : Inputs) { std::string Filename(I.getFilename()); diff --git a/clang/test/Driver/sycl-offload-intelfpga.cpp b/clang/test/Driver/sycl-offload-intelfpga.cpp index 2b1150f87b7de..de589affbc5e7 100644 --- a/clang/test/Driver/sycl-offload-intelfpga.cpp +++ b/clang/test/Driver/sycl-offload-intelfpga.cpp @@ -32,7 +32,7 @@ // CHK-FPGA-LINK-NOT: clang-offload-bundler{{.*}} // CHK-FPGA-LINK: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" // CHK-FPGA-LINK: sycl-post-link{{.*}} "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]" -// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT2]]" +// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]" // CHK-FPGA-EARLY: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl" // CHK-FPGA-IMAGE: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocx]]" "[[OUTPUT3]]" "-sycl" // CHK-FPGA-LINK: llvm-ar{{.*}} "cr" "libfoo.a" "[[INPUT]]" @@ -58,7 +58,7 @@ // CHK-FPGA-LINK-WIN-NOT: clang-offload-bundler{{.*}} // CHK-FPGA-LINK-WIN: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" // CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-ir-output-only" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]" -// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT2]]" +// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2]]" // CHK-FPGA-LINK-WIN: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl" // CHK-FPGA-LINK-WIN: lib.exe{{.*}} "[[INPUT]]" {{.*}} "-OUT:libfoo.lib" @@ -112,7 +112,7 @@ // CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=host-x86_64-unknown-linux-gnu,sycl-spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-outputs=[[FINALLINK2:.+\.o]],[[OUTPUT1:.+\.o]]" "-unbundle" // CHK-FPGA: llvm-no-spir-kernel{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT3:.+\.o]]" // CHK-FPGA: llvm-link{{.*}} "[[OUTPUT3]]" "-o" "[[OUTPUT4:.+\.bc]]" -// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT4]]" +// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT4]]" // CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT6:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga" "-kind=sycl" "[[OUTPUT5]]" // CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK3:.+\.o]]" "[[OUTPUT6]]" // CHK-FPGA: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" {{.*}} "-outputs=[[FINALLINK4:.+\.txt]]" "-unbundle" diff --git a/clang/test/Driver/sycl-offload.c b/clang/test/Driver/sycl-offload.c index 549aa1e739bcb..ea2eaef3d2132 100644 --- a/clang/test/Driver/sycl-offload.c +++ b/clang/test/Driver/sycl-offload.c @@ -649,7 +649,9 @@ // CHK-TOOLS-AOT: clang{{.*}} "-fsycl-is-device" {{.*}} "-o" "[[OUTPUT1:.+\.bc]]" // CHK-TOOLS-AOT: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2:.+\.bc]]" // CHK-TOOLS-AOT: sycl-post-link{{.*}} "-o" "[[OUTPUT2_1:.+\.bc]]" "[[OUTPUT2]]" -// CHK-TOOLS-AOT: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT2_1]]" +// CHK-TOOLS-CPU: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]" +// CHK-TOOLS-GEN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]" +// CHK-TOOLS-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]" // CHK-TOOLS-FPGA: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocx]]" "[[OUTPUT3]]" // CHK-TOOLS-GEN: ocloc{{.*}} "-output" "[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]" // CHK-TOOLS-CPU: opencl-aot{{.*}} "-o=[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]" diff --git a/clang/test/Driver/sycl.c b/clang/test/Driver/sycl.c index 733c32d7e1e82..7ba86293416e9 100644 --- a/clang/test/Driver/sycl.c +++ b/clang/test/Driver/sycl.c @@ -40,11 +40,11 @@ // DEFAULT: "-triple" "spir64-unknown-{{.*}}-sycldevice{{.*}}" "-fsycl-is-device"{{.*}} "-emit-llvm-bc" // DEFAULT: "-internal-isystem" "{{.*}}bin{{[/\\]+}}..{{[/\\]+}}include{{[/\\]+}}sycl" // DEFAULT: "-internal-isystem" "{{.*lib.*clang.*include}}" -// DEFAULT-NOT: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.1"{{.*}} "-spirv-ext=+all" +// DEFAULT-NOT: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.1"{{.*}} "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" // DEFAULT-NOT: "-std=c++11" // DEFAULT-NOT: "-std=c++14" // NO-BITCODE: "-triple" "spir64-unknown-{{.*}}-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc" -// NO-BITCODE: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.1"{{.*}} "-spirv-ext=+all" +// NO-BITCODE: "{{.*}}llvm-spirv"{{.*}} "-spirv-max-version=1.1"{{.*}} "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" // TARGET: "-triple" "spir64-unknown-linux-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc" // COMBINED: "-triple" "spir64-unknown-{{.*}}-sycldevice"{{.*}} "-fsycl-is-device"{{.*}} "-emit-llvm-bc" // TEXTUAL: "-triple" "spir64-unknown-{{.*}}-sycldevice{{.*}}" "-fsycl-is-device"{{.*}} "-emit-llvm" From dc84a4cee9e10cb1a3b318431a3894a6ddd475d9 Mon Sep 17 00:00:00 2001 From: Dmitry Sidorov Date: Thu, 25 Jun 2020 13:54:26 +0300 Subject: [PATCH 2/5] Apply clang-format Signed-off-by: Dmitry Sidorov --- clang/lib/Driver/ToolChains/Clang.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index ff28d5e716d35..9a12a320c1e76 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -7649,7 +7649,7 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA, // disable the storage classes will be lowered to CrossWorkgroup storage // class that is mapped to just global address space. if (!(getToolChain().getTriple().getSubArch() == - llvm::Triple::SPIRSubArch_fpga && + llvm::Triple::SPIRSubArch_fpga && TCArgs.hasArg(options::OPT_fenable_usm_address_spaces))) ExtArg += ",-SPV_INTEL_usm_storage_classes"; TranslatorArgs.push_back(TCArgs.MakeArgString(ExtArg)); From f354baa678e58431b7f4977487247caefe339ebf Mon Sep 17 00:00:00 2001 From: Dmitry Sidorov Date: Fri, 26 Jun 2020 18:50:52 +0300 Subject: [PATCH 3/5] Add positive test Signed-off-by: Dmitry Sidorov --- clang/include/clang/Driver/Options.td | 2 +- clang/lib/Driver/ToolChains/Clang.cpp | 2 +- clang/test/Driver/sycl-offload.c | 11 ++++++++--- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index c185e50d3b834..9d751bca29e68 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -1822,7 +1822,7 @@ def fstrict_vtable_pointers: Flag<["-"], "fstrict-vtable-pointers">, def fstrict_overflow : Flag<["-"], "fstrict-overflow">, Group; def fintelfpga : Flag<["-"], "fintelfpga">, Group, Flags<[CC1Option, CoreOption]>, HelpText<"Perform ahead of time compilation for FPGA">; -def fenable_usm_address_spaces : Flag<["-"], "fenable-usm-address-spaces">, +def fsycl_enable_usm_address_spaces : Flag<["-"], "fsycl-enable-usm-address-spaces">, Group, Flags<[CC1Option, CoreOption]>, HelpText<"Add support for SPV_INTEL_usm_storage_classes feature">; def fsycl_device_only : Flag<["-"], "fsycl-device-only">, Flags<[CoreOption]>, diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 9a12a320c1e76..30eea3dede1b9 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -7650,7 +7650,7 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA, // class that is mapped to just global address space. if (!(getToolChain().getTriple().getSubArch() == llvm::Triple::SPIRSubArch_fpga && - TCArgs.hasArg(options::OPT_fenable_usm_address_spaces))) + TCArgs.hasArg(options::OPT_fsycl_enable_usm_address_spaces))) ExtArg += ",-SPV_INTEL_usm_storage_classes"; TranslatorArgs.push_back(TCArgs.MakeArgString(ExtArg)); } diff --git a/clang/test/Driver/sycl-offload.c b/clang/test/Driver/sycl-offload.c index ea2eaef3d2132..0de866d943055 100644 --- a/clang/test/Driver/sycl-offload.c +++ b/clang/test/Driver/sycl-offload.c @@ -639,9 +639,13 @@ /// Ahead of Time compilation for fpga, gen, cpu - tool invocation // RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s -### 2>&1 \ -// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA +// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE // RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga %s -### 2>&1 \ -// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA +// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-DISABLE +// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -fsycl-enable-usm-address-spaces %s -### 2>&1 \ +// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE +// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -fsycl-enable-usm-address-spaces %s -### 2>&1 \ +// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE // RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s -### 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-GEN // RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s -### 2>&1 \ @@ -651,7 +655,8 @@ // CHK-TOOLS-AOT: sycl-post-link{{.*}} "-o" "[[OUTPUT2_1:.+\.bc]]" "[[OUTPUT2]]" // CHK-TOOLS-CPU: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]" // CHK-TOOLS-GEN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]" -// CHK-TOOLS-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]" +// CHK-TOOLS-FPGA-USM-DISABLE: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all,-SPV_INTEL_usm_storage_classes" "[[OUTPUT2_1]]" +// CHK-TOOLS-FPGA-USM-ENABLE: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.1" "-spirv-ext=+all" "[[OUTPUT2_1]]" // CHK-TOOLS-FPGA: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocx]]" "[[OUTPUT3]]" // CHK-TOOLS-GEN: ocloc{{.*}} "-output" "[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]" // CHK-TOOLS-CPU: opencl-aot{{.*}} "-o=[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]" From 60566ad4e9535b972354e8974972e5094652b373 Mon Sep 17 00:00:00 2001 From: Dmitry Sidorov Date: Fri, 26 Jun 2020 20:06:58 +0300 Subject: [PATCH 4/5] Apply suggestion Signed-off-by: Dmitry Sidorov --- clang/include/clang/Driver/Options.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 9d751bca29e68..02b64fb0e5cab 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -1824,7 +1824,7 @@ def fintelfpga : Flag<["-"], "fintelfpga">, Group, Flags<[CC1Option, CoreOption]>, HelpText<"Perform ahead of time compilation for FPGA">; def fsycl_enable_usm_address_spaces : Flag<["-"], "fsycl-enable-usm-address-spaces">, Group, Flags<[CC1Option, CoreOption]>, - HelpText<"Add support for SPV_INTEL_usm_storage_classes feature">; + HelpText<"Enable SPV_INTEL_usm_storage_classes extension">; def fsycl_device_only : Flag<["-"], "fsycl-device-only">, Flags<[CoreOption]>, HelpText<"Compile SYCL kernels for device">; def fsycl_targets_EQ : CommaJoined<["-"], "fsycl-targets=">, Flags<[DriverOption, CC1Option, CoreOption]>, From c8398dda27308941305a1a2872a054980dce7898 Mon Sep 17 00:00:00 2001 From: Dmitry Sidorov Date: Fri, 26 Jun 2020 20:51:12 +0300 Subject: [PATCH 5/5] Add extra test cases Signed-off-by: Dmitry Sidorov --- clang/test/Driver/sycl-offload.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/clang/test/Driver/sycl-offload.c b/clang/test/Driver/sycl-offload.c index 0de866d943055..c28a59e828ad4 100644 --- a/clang/test/Driver/sycl-offload.c +++ b/clang/test/Driver/sycl-offload.c @@ -646,6 +646,10 @@ // RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE // RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -fsycl-enable-usm-address-spaces %s -### 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-FPGA,CHK-TOOLS-FPGA-USM-ENABLE +// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice -fsycl-enable-usm-address-spaces %s -### 2>&1 \ +// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-GEN +// RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice -fsycl-enable-usm-address-spaces %s -### 2>&1 \ +// RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-CPU // RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s -### 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-TOOLS-AOT,CHK-TOOLS-GEN // RUN: %clang -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s -### 2>&1 \