diff --git a/libclc/generic/include/spirv/misc/shuffle.h b/libclc/generic/include/spirv/misc/shuffle.h deleted file mode 100644 index 177ae01d0027..000000000000 --- a/libclc/generic/include/spirv/misc/shuffle.h +++ /dev/null @@ -1,46 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define _SPIRV_SHUFFLE_DECL(TYPE, MASKTYPE, RETTYPE) \ - _CLC_OVERLOAD _CLC_DECL RETTYPE __spirv_ocl_shuffle(TYPE x, MASKTYPE mask); - -//Return type is same base type as the input type, with the same vector size as the mask. -//Elements in the mask must be the same size (number of bits) as the input value. -//E.g. char8 ret = __spirv_ocl_shuffle(char2 x, uchar8 mask); - -#define _SPIRV_VECTOR_SHUFFLE_MASKSIZE(INBASE, INTYPE, MASKTYPE) \ - _SPIRV_SHUFFLE_DECL(INTYPE, MASKTYPE##2, INBASE##2) \ - _SPIRV_SHUFFLE_DECL(INTYPE, MASKTYPE##4, INBASE##4) \ - _SPIRV_SHUFFLE_DECL(INTYPE, MASKTYPE##8, INBASE##8) \ - _SPIRV_SHUFFLE_DECL(INTYPE, MASKTYPE##16, INBASE##16) \ - -#define _SPIRV_VECTOR_SHUFFLE_INSIZE(TYPE, MASKTYPE) \ - _SPIRV_VECTOR_SHUFFLE_MASKSIZE(TYPE, TYPE##2, MASKTYPE) \ - _SPIRV_VECTOR_SHUFFLE_MASKSIZE(TYPE, TYPE##4, MASKTYPE) \ - _SPIRV_VECTOR_SHUFFLE_MASKSIZE(TYPE, TYPE##8, MASKTYPE) \ - _SPIRV_VECTOR_SHUFFLE_MASKSIZE(TYPE, TYPE##16, MASKTYPE) \ - -_SPIRV_VECTOR_SHUFFLE_INSIZE(char, uchar) -_SPIRV_VECTOR_SHUFFLE_INSIZE(short, ushort) -_SPIRV_VECTOR_SHUFFLE_INSIZE(int, uint) -_SPIRV_VECTOR_SHUFFLE_INSIZE(long, ulong) -_SPIRV_VECTOR_SHUFFLE_INSIZE(uchar, uchar) -_SPIRV_VECTOR_SHUFFLE_INSIZE(ushort, ushort) -_SPIRV_VECTOR_SHUFFLE_INSIZE(uint, uint) -_SPIRV_VECTOR_SHUFFLE_INSIZE(ulong, ulong) -_SPIRV_VECTOR_SHUFFLE_INSIZE(float, uint) -#ifdef cl_khr_fp64 -_SPIRV_VECTOR_SHUFFLE_INSIZE(double, ulong) -#endif -#ifdef cl_khr_fp16 -_SPIRV_VECTOR_SHUFFLE_INSIZE(half, ushort) -#endif - -#undef _SPIRV_SHUFFLE_DECL -#undef _SPIRV_VECTOR_SHUFFLE_MASKSIZE -#undef _SPIRV_VECTOR_SHUFFLE_INSIZE diff --git a/libclc/generic/include/spirv/misc/shuffle2.h b/libclc/generic/include/spirv/misc/shuffle2.h deleted file mode 100644 index 210d8f534372..000000000000 --- a/libclc/generic/include/spirv/misc/shuffle2.h +++ /dev/null @@ -1,46 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define _SPIRV_SHUFFLE2_DECL(TYPE, MASKTYPE, RETTYPE) \ - _CLC_OVERLOAD _CLC_DECL RETTYPE __spirv_ocl_shuffle2(TYPE x, TYPE y, MASKTYPE mask); - -//Return type is same base type as the input type, with the same vector size as the mask. -//Elements in the mask must be the same size (number of bits) as the input value. -//E.g. char8 ret = __spirv_ocl_shuffle2(char2 x, char2 y, uchar8 mask); - -#define _SPIRV_VECTOR_SHUFFLE2_MASKSIZE(INBASE, INTYPE, MASKTYPE) \ - _SPIRV_SHUFFLE2_DECL(INTYPE, MASKTYPE##2, INBASE##2) \ - _SPIRV_SHUFFLE2_DECL(INTYPE, MASKTYPE##4, INBASE##4) \ - _SPIRV_SHUFFLE2_DECL(INTYPE, MASKTYPE##8, INBASE##8) \ - _SPIRV_SHUFFLE2_DECL(INTYPE, MASKTYPE##16, INBASE##16) \ - -#define _SPIRV_VECTOR_SHUFFLE2_INSIZE(TYPE, MASKTYPE) \ - _SPIRV_VECTOR_SHUFFLE2_MASKSIZE(TYPE, TYPE##2, MASKTYPE) \ - _SPIRV_VECTOR_SHUFFLE2_MASKSIZE(TYPE, TYPE##4, MASKTYPE) \ - _SPIRV_VECTOR_SHUFFLE2_MASKSIZE(TYPE, TYPE##8, MASKTYPE) \ - _SPIRV_VECTOR_SHUFFLE2_MASKSIZE(TYPE, TYPE##16, MASKTYPE) \ - -_SPIRV_VECTOR_SHUFFLE2_INSIZE(char, uchar) -_SPIRV_VECTOR_SHUFFLE2_INSIZE(short, ushort) -_SPIRV_VECTOR_SHUFFLE2_INSIZE(int, uint) -_SPIRV_VECTOR_SHUFFLE2_INSIZE(long, ulong) -_SPIRV_VECTOR_SHUFFLE2_INSIZE(uchar, uchar) -_SPIRV_VECTOR_SHUFFLE2_INSIZE(ushort, ushort) -_SPIRV_VECTOR_SHUFFLE2_INSIZE(uint, uint) -_SPIRV_VECTOR_SHUFFLE2_INSIZE(ulong, ulong) -_SPIRV_VECTOR_SHUFFLE2_INSIZE(float, uint) -#ifdef cl_khr_fp64 -_SPIRV_VECTOR_SHUFFLE2_INSIZE(double, ulong) -#endif -#ifdef cl_khr_fp16 -_SPIRV_VECTOR_SHUFFLE2_INSIZE(half, ushort) -#endif - -#undef _SPIRV_SHUFFLE_DECL -#undef _SPIRV_VECTOR_SHUFFLE2_MASKSIZE -#undef _SPIRV_VECTOR_SHUFFLE2_INSIZE diff --git a/libclc/generic/include/spirv/spirv.h b/libclc/generic/include/spirv/spirv.h index 7083667856b9..7449d0340975 100644 --- a/libclc/generic/include/spirv/spirv.h +++ b/libclc/generic/include/spirv/spirv.h @@ -67,12 +67,6 @@ #include #include -/* cl_khr extension atomics are omitted from __spirv */ - -/* 6.12.12 Miscellaneous Vector Functions */ -#include -#include - /* 6.11.13 Image Read and Write Functions */ #include #include diff --git a/libclc/generic/include/spirv/spirv_builtins.h b/libclc/generic/include/spirv/spirv_builtins.h index e59c1850446d..adeb3a63460d 100644 --- a/libclc/generic/include/spirv/spirv_builtins.h +++ b/libclc/generic/include/spirv/spirv_builtins.h @@ -12426,6 +12426,43 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_Unordered(__clc_vec16_fp16_t, __clc_vec16_fp16_t); #endif +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_VectorTimesScalar(__clc_vec2_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_VectorTimesScalar(__clc_vec3_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_VectorTimesScalar(__clc_vec4_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_VectorTimesScalar(__clc_vec8_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_VectorTimesScalar(__clc_vec16_fp32_t, __clc_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_VectorTimesScalar(__clc_vec2_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_VectorTimesScalar(__clc_vec3_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_VectorTimesScalar(__clc_vec4_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_VectorTimesScalar(__clc_vec8_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_VectorTimesScalar(__clc_vec16_fp64_t, __clc_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_VectorTimesScalar(__clc_vec2_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_VectorTimesScalar(__clc_vec3_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_VectorTimesScalar(__clc_vec4_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_VectorTimesScalar(__clc_vec8_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_VectorTimesScalar(__clc_vec16_fp16_t, __clc_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_acos(__clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t @@ -17762,6 +17799,788 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_select( __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_uint16_t); #endif +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t + __spirv_ocl_shuffle(__clc_vec2_char_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t + __spirv_ocl_shuffle(__clc_vec4_char_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t + __spirv_ocl_shuffle(__clc_vec8_char_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t + __spirv_ocl_shuffle(__clc_vec16_char_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t + __spirv_ocl_shuffle(__clc_vec2_char_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t + __spirv_ocl_shuffle(__clc_vec4_char_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t + __spirv_ocl_shuffle(__clc_vec8_char_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t + __spirv_ocl_shuffle(__clc_vec16_char_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t + __spirv_ocl_shuffle(__clc_vec2_char_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t + __spirv_ocl_shuffle(__clc_vec4_char_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t + __spirv_ocl_shuffle(__clc_vec8_char_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t + __spirv_ocl_shuffle(__clc_vec16_char_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_shuffle(__clc_vec2_char_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_shuffle(__clc_vec4_char_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_shuffle(__clc_vec8_char_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_shuffle(__clc_vec16_char_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_ocl_shuffle(__clc_vec2_int8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_ocl_shuffle(__clc_vec4_int8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_ocl_shuffle(__clc_vec8_int8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_ocl_shuffle(__clc_vec16_int8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_ocl_shuffle(__clc_vec2_int8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_ocl_shuffle(__clc_vec4_int8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_ocl_shuffle(__clc_vec8_int8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_ocl_shuffle(__clc_vec16_int8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_ocl_shuffle(__clc_vec2_int8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_ocl_shuffle(__clc_vec4_int8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_ocl_shuffle(__clc_vec8_int8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_ocl_shuffle(__clc_vec16_int8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_shuffle(__clc_vec2_int8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_shuffle(__clc_vec4_int8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_shuffle(__clc_vec8_int8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_shuffle(__clc_vec16_int8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_shuffle(__clc_vec2_int16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_shuffle(__clc_vec4_int16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_shuffle(__clc_vec8_int16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_shuffle(__clc_vec16_int16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_shuffle(__clc_vec2_int16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_shuffle(__clc_vec4_int16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_shuffle(__clc_vec8_int16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_shuffle(__clc_vec16_int16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_shuffle(__clc_vec2_int16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_shuffle(__clc_vec4_int16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_shuffle(__clc_vec8_int16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_shuffle(__clc_vec16_int16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_shuffle(__clc_vec2_int16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_shuffle(__clc_vec4_int16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_shuffle(__clc_vec8_int16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_shuffle(__clc_vec16_int16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_shuffle(__clc_vec2_int32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_shuffle(__clc_vec4_int32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_shuffle(__clc_vec8_int32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_shuffle(__clc_vec16_int32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_shuffle(__clc_vec2_int32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_shuffle(__clc_vec4_int32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_shuffle(__clc_vec8_int32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_shuffle(__clc_vec16_int32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_shuffle(__clc_vec2_int32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_shuffle(__clc_vec4_int32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_shuffle(__clc_vec8_int32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_shuffle(__clc_vec16_int32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_shuffle(__clc_vec2_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_shuffle(__clc_vec4_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_shuffle(__clc_vec8_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_shuffle(__clc_vec16_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_shuffle(__clc_vec2_int64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_shuffle(__clc_vec4_int64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_shuffle(__clc_vec8_int64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_shuffle(__clc_vec16_int64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_shuffle(__clc_vec2_int64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_shuffle(__clc_vec4_int64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_shuffle(__clc_vec8_int64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_shuffle(__clc_vec16_int64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_shuffle(__clc_vec2_int64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_shuffle(__clc_vec4_int64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_shuffle(__clc_vec8_int64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_shuffle(__clc_vec16_int64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_shuffle(__clc_vec2_int64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_shuffle(__clc_vec4_int64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_shuffle(__clc_vec8_int64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_shuffle(__clc_vec16_int64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_shuffle(__clc_vec2_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_shuffle(__clc_vec4_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_shuffle(__clc_vec8_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_shuffle(__clc_vec16_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_shuffle(__clc_vec2_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_shuffle(__clc_vec4_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_shuffle(__clc_vec8_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_shuffle(__clc_vec16_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_shuffle(__clc_vec2_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_shuffle(__clc_vec4_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_shuffle(__clc_vec8_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_shuffle(__clc_vec16_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_shuffle(__clc_vec2_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_shuffle(__clc_vec4_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_shuffle(__clc_vec8_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_shuffle(__clc_vec16_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_shuffle(__clc_vec2_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_shuffle(__clc_vec4_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_shuffle(__clc_vec8_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_shuffle(__clc_vec16_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_shuffle(__clc_vec2_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_shuffle(__clc_vec4_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_shuffle(__clc_vec8_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_shuffle(__clc_vec16_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_shuffle(__clc_vec2_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_shuffle(__clc_vec4_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_shuffle(__clc_vec8_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_shuffle(__clc_vec16_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_shuffle(__clc_vec2_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_shuffle(__clc_vec4_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_shuffle(__clc_vec8_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_shuffle(__clc_vec16_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_shuffle(__clc_vec2_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_shuffle(__clc_vec4_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_shuffle(__clc_vec8_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_shuffle(__clc_vec16_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_shuffle(__clc_vec2_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_shuffle(__clc_vec4_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_shuffle(__clc_vec8_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_shuffle(__clc_vec16_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_shuffle(__clc_vec2_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_shuffle(__clc_vec4_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_shuffle(__clc_vec8_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_shuffle(__clc_vec16_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_shuffle(__clc_vec2_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_shuffle(__clc_vec4_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_shuffle(__clc_vec8_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_shuffle(__clc_vec16_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_shuffle(__clc_vec2_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_shuffle(__clc_vec4_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_shuffle(__clc_vec8_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_shuffle(__clc_vec16_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_shuffle(__clc_vec2_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_shuffle(__clc_vec4_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_shuffle(__clc_vec8_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_shuffle(__clc_vec16_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_shuffle(__clc_vec2_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_shuffle(__clc_vec4_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_shuffle(__clc_vec8_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_shuffle(__clc_vec16_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_shuffle(__clc_vec2_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_shuffle(__clc_vec4_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_shuffle(__clc_vec8_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_shuffle(__clc_vec16_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_shuffle(__clc_vec2_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_shuffle(__clc_vec4_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_shuffle(__clc_vec8_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_shuffle(__clc_vec16_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_shuffle(__clc_vec2_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_shuffle(__clc_vec4_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_shuffle(__clc_vec8_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_shuffle(__clc_vec16_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_shuffle(__clc_vec2_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_shuffle(__clc_vec4_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_shuffle(__clc_vec8_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_shuffle(__clc_vec16_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_shuffle(__clc_vec2_fp32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_shuffle(__clc_vec4_fp32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_shuffle(__clc_vec8_fp32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_shuffle(__clc_vec16_fp32_t, __clc_vec16_uint32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_shuffle(__clc_vec2_fp64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_shuffle(__clc_vec4_fp64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_shuffle(__clc_vec8_fp64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_shuffle(__clc_vec16_fp64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_shuffle(__clc_vec2_fp64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_shuffle(__clc_vec4_fp64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_shuffle(__clc_vec8_fp64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_shuffle(__clc_vec16_fp64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_shuffle(__clc_vec2_fp64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_shuffle(__clc_vec4_fp64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_shuffle(__clc_vec8_fp64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_shuffle(__clc_vec16_fp64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_shuffle(__clc_vec2_fp64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_shuffle(__clc_vec4_fp64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_shuffle(__clc_vec8_fp64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_shuffle(__clc_vec16_fp64_t, __clc_vec16_uint64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_shuffle(__clc_vec2_fp16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_shuffle(__clc_vec4_fp16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_shuffle(__clc_vec8_fp16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_shuffle(__clc_vec16_fp16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_shuffle(__clc_vec2_fp16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_shuffle(__clc_vec4_fp16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_shuffle(__clc_vec8_fp16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_shuffle(__clc_vec16_fp16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_shuffle(__clc_vec2_fp16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_shuffle(__clc_vec4_fp16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_shuffle(__clc_vec8_fp16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_shuffle(__clc_vec16_fp16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_shuffle(__clc_vec2_fp16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_shuffle(__clc_vec4_fp16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_shuffle(__clc_vec8_fp16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_shuffle(__clc_vec16_fp16_t, __clc_vec16_uint16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_shuffle2( + __clc_vec2_char_t, __clc_vec2_char_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_shuffle2( + __clc_vec4_char_t, __clc_vec4_char_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_shuffle2( + __clc_vec8_char_t, __clc_vec8_char_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_shuffle2( + __clc_vec16_char_t, __clc_vec16_char_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_shuffle2( + __clc_vec2_char_t, __clc_vec2_char_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_shuffle2( + __clc_vec4_char_t, __clc_vec4_char_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_shuffle2( + __clc_vec8_char_t, __clc_vec8_char_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_shuffle2( + __clc_vec16_char_t, __clc_vec16_char_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_shuffle2( + __clc_vec2_char_t, __clc_vec2_char_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_shuffle2( + __clc_vec4_char_t, __clc_vec4_char_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_shuffle2( + __clc_vec8_char_t, __clc_vec8_char_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_shuffle2( + __clc_vec16_char_t, __clc_vec16_char_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t __spirv_ocl_shuffle2( + __clc_vec2_char_t, __clc_vec2_char_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t __spirv_ocl_shuffle2( + __clc_vec4_char_t, __clc_vec4_char_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t __spirv_ocl_shuffle2( + __clc_vec8_char_t, __clc_vec8_char_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t __spirv_ocl_shuffle2( + __clc_vec16_char_t, __clc_vec16_char_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_shuffle2( + __clc_vec2_int8_t, __clc_vec2_int8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_shuffle2( + __clc_vec4_int8_t, __clc_vec4_int8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_shuffle2( + __clc_vec8_int8_t, __clc_vec8_int8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_shuffle2( + __clc_vec16_int8_t, __clc_vec16_int8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_shuffle2( + __clc_vec2_int8_t, __clc_vec2_int8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_shuffle2( + __clc_vec4_int8_t, __clc_vec4_int8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_shuffle2( + __clc_vec8_int8_t, __clc_vec8_int8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_shuffle2( + __clc_vec16_int8_t, __clc_vec16_int8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_shuffle2( + __clc_vec2_int8_t, __clc_vec2_int8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_shuffle2( + __clc_vec4_int8_t, __clc_vec4_int8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_shuffle2( + __clc_vec8_int8_t, __clc_vec8_int8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_shuffle2( + __clc_vec16_int8_t, __clc_vec16_int8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_ocl_shuffle2( + __clc_vec2_int8_t, __clc_vec2_int8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_ocl_shuffle2( + __clc_vec4_int8_t, __clc_vec4_int8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_ocl_shuffle2( + __clc_vec8_int8_t, __clc_vec8_int8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_ocl_shuffle2( + __clc_vec16_int8_t, __clc_vec16_int8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t __spirv_ocl_shuffle2( + __clc_vec2_int16_t, __clc_vec2_int16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t __spirv_ocl_shuffle2( + __clc_vec4_int16_t, __clc_vec4_int16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t __spirv_ocl_shuffle2( + __clc_vec8_int16_t, __clc_vec8_int16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t __spirv_ocl_shuffle2( + __clc_vec16_int16_t, __clc_vec16_int16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t __spirv_ocl_shuffle2( + __clc_vec2_int16_t, __clc_vec2_int16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t __spirv_ocl_shuffle2( + __clc_vec4_int16_t, __clc_vec4_int16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t __spirv_ocl_shuffle2( + __clc_vec8_int16_t, __clc_vec8_int16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t __spirv_ocl_shuffle2( + __clc_vec16_int16_t, __clc_vec16_int16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t __spirv_ocl_shuffle2( + __clc_vec2_int16_t, __clc_vec2_int16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t __spirv_ocl_shuffle2( + __clc_vec4_int16_t, __clc_vec4_int16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t __spirv_ocl_shuffle2( + __clc_vec8_int16_t, __clc_vec8_int16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t __spirv_ocl_shuffle2( + __clc_vec16_int16_t, __clc_vec16_int16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t __spirv_ocl_shuffle2( + __clc_vec2_int16_t, __clc_vec2_int16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t __spirv_ocl_shuffle2( + __clc_vec4_int16_t, __clc_vec4_int16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t __spirv_ocl_shuffle2( + __clc_vec8_int16_t, __clc_vec8_int16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t __spirv_ocl_shuffle2( + __clc_vec16_int16_t, __clc_vec16_int16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t __spirv_ocl_shuffle2( + __clc_vec2_int32_t, __clc_vec2_int32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t __spirv_ocl_shuffle2( + __clc_vec4_int32_t, __clc_vec4_int32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t __spirv_ocl_shuffle2( + __clc_vec8_int32_t, __clc_vec8_int32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t __spirv_ocl_shuffle2( + __clc_vec16_int32_t, __clc_vec16_int32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t __spirv_ocl_shuffle2( + __clc_vec2_int32_t, __clc_vec2_int32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t __spirv_ocl_shuffle2( + __clc_vec4_int32_t, __clc_vec4_int32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t __spirv_ocl_shuffle2( + __clc_vec8_int32_t, __clc_vec8_int32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t __spirv_ocl_shuffle2( + __clc_vec16_int32_t, __clc_vec16_int32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t __spirv_ocl_shuffle2( + __clc_vec2_int32_t, __clc_vec2_int32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t __spirv_ocl_shuffle2( + __clc_vec4_int32_t, __clc_vec4_int32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t __spirv_ocl_shuffle2( + __clc_vec8_int32_t, __clc_vec8_int32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t __spirv_ocl_shuffle2( + __clc_vec16_int32_t, __clc_vec16_int32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t __spirv_ocl_shuffle2( + __clc_vec2_int32_t, __clc_vec2_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t __spirv_ocl_shuffle2( + __clc_vec4_int32_t, __clc_vec4_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t __spirv_ocl_shuffle2( + __clc_vec8_int32_t, __clc_vec8_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t __spirv_ocl_shuffle2( + __clc_vec16_int32_t, __clc_vec16_int32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t __spirv_ocl_shuffle2( + __clc_vec2_int64_t, __clc_vec2_int64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t __spirv_ocl_shuffle2( + __clc_vec4_int64_t, __clc_vec4_int64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t __spirv_ocl_shuffle2( + __clc_vec8_int64_t, __clc_vec8_int64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t __spirv_ocl_shuffle2( + __clc_vec16_int64_t, __clc_vec16_int64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t __spirv_ocl_shuffle2( + __clc_vec2_int64_t, __clc_vec2_int64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t __spirv_ocl_shuffle2( + __clc_vec4_int64_t, __clc_vec4_int64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t __spirv_ocl_shuffle2( + __clc_vec8_int64_t, __clc_vec8_int64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t __spirv_ocl_shuffle2( + __clc_vec16_int64_t, __clc_vec16_int64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t __spirv_ocl_shuffle2( + __clc_vec2_int64_t, __clc_vec2_int64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t __spirv_ocl_shuffle2( + __clc_vec4_int64_t, __clc_vec4_int64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t __spirv_ocl_shuffle2( + __clc_vec8_int64_t, __clc_vec8_int64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t __spirv_ocl_shuffle2( + __clc_vec16_int64_t, __clc_vec16_int64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t __spirv_ocl_shuffle2( + __clc_vec2_int64_t, __clc_vec2_int64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t __spirv_ocl_shuffle2( + __clc_vec4_int64_t, __clc_vec4_int64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t __spirv_ocl_shuffle2( + __clc_vec8_int64_t, __clc_vec8_int64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t __spirv_ocl_shuffle2( + __clc_vec16_int64_t, __clc_vec16_int64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t __spirv_ocl_shuffle2( + __clc_vec2_uint8_t, __clc_vec2_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t __spirv_ocl_shuffle2( + __clc_vec4_uint8_t, __clc_vec4_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t __spirv_ocl_shuffle2( + __clc_vec8_uint8_t, __clc_vec8_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t __spirv_ocl_shuffle2( + __clc_vec16_uint8_t, __clc_vec16_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t __spirv_ocl_shuffle2( + __clc_vec2_uint8_t, __clc_vec2_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t __spirv_ocl_shuffle2( + __clc_vec4_uint8_t, __clc_vec4_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t __spirv_ocl_shuffle2( + __clc_vec8_uint8_t, __clc_vec8_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t __spirv_ocl_shuffle2( + __clc_vec16_uint8_t, __clc_vec16_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t __spirv_ocl_shuffle2( + __clc_vec2_uint8_t, __clc_vec2_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t __spirv_ocl_shuffle2( + __clc_vec4_uint8_t, __clc_vec4_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t __spirv_ocl_shuffle2( + __clc_vec8_uint8_t, __clc_vec8_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t __spirv_ocl_shuffle2( + __clc_vec16_uint8_t, __clc_vec16_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t __spirv_ocl_shuffle2( + __clc_vec2_uint8_t, __clc_vec2_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t __spirv_ocl_shuffle2( + __clc_vec4_uint8_t, __clc_vec4_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t __spirv_ocl_shuffle2( + __clc_vec8_uint8_t, __clc_vec8_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t __spirv_ocl_shuffle2( + __clc_vec16_uint8_t, __clc_vec16_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t __spirv_ocl_shuffle2( + __clc_vec2_uint16_t, __clc_vec2_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t __spirv_ocl_shuffle2( + __clc_vec4_uint16_t, __clc_vec4_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t __spirv_ocl_shuffle2( + __clc_vec8_uint16_t, __clc_vec8_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t __spirv_ocl_shuffle2( + __clc_vec16_uint16_t, __clc_vec16_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t __spirv_ocl_shuffle2( + __clc_vec2_uint16_t, __clc_vec2_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t __spirv_ocl_shuffle2( + __clc_vec4_uint16_t, __clc_vec4_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t __spirv_ocl_shuffle2( + __clc_vec8_uint16_t, __clc_vec8_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t __spirv_ocl_shuffle2( + __clc_vec16_uint16_t, __clc_vec16_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t __spirv_ocl_shuffle2( + __clc_vec2_uint16_t, __clc_vec2_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t __spirv_ocl_shuffle2( + __clc_vec4_uint16_t, __clc_vec4_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t __spirv_ocl_shuffle2( + __clc_vec8_uint16_t, __clc_vec8_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t __spirv_ocl_shuffle2( + __clc_vec16_uint16_t, __clc_vec16_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t __spirv_ocl_shuffle2( + __clc_vec2_uint16_t, __clc_vec2_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t __spirv_ocl_shuffle2( + __clc_vec4_uint16_t, __clc_vec4_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t __spirv_ocl_shuffle2( + __clc_vec8_uint16_t, __clc_vec8_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t __spirv_ocl_shuffle2( + __clc_vec16_uint16_t, __clc_vec16_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t __spirv_ocl_shuffle2( + __clc_vec2_uint32_t, __clc_vec2_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t __spirv_ocl_shuffle2( + __clc_vec4_uint32_t, __clc_vec4_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t __spirv_ocl_shuffle2( + __clc_vec8_uint32_t, __clc_vec8_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t __spirv_ocl_shuffle2( + __clc_vec16_uint32_t, __clc_vec16_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t __spirv_ocl_shuffle2( + __clc_vec2_uint32_t, __clc_vec2_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t __spirv_ocl_shuffle2( + __clc_vec4_uint32_t, __clc_vec4_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t __spirv_ocl_shuffle2( + __clc_vec8_uint32_t, __clc_vec8_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t __spirv_ocl_shuffle2( + __clc_vec16_uint32_t, __clc_vec16_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t __spirv_ocl_shuffle2( + __clc_vec2_uint32_t, __clc_vec2_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t __spirv_ocl_shuffle2( + __clc_vec4_uint32_t, __clc_vec4_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t __spirv_ocl_shuffle2( + __clc_vec8_uint32_t, __clc_vec8_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t __spirv_ocl_shuffle2( + __clc_vec16_uint32_t, __clc_vec16_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t __spirv_ocl_shuffle2( + __clc_vec2_uint32_t, __clc_vec2_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t __spirv_ocl_shuffle2( + __clc_vec4_uint32_t, __clc_vec4_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t __spirv_ocl_shuffle2( + __clc_vec8_uint32_t, __clc_vec8_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t __spirv_ocl_shuffle2( + __clc_vec16_uint32_t, __clc_vec16_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t __spirv_ocl_shuffle2( + __clc_vec2_uint64_t, __clc_vec2_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t __spirv_ocl_shuffle2( + __clc_vec4_uint64_t, __clc_vec4_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t __spirv_ocl_shuffle2( + __clc_vec8_uint64_t, __clc_vec8_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t __spirv_ocl_shuffle2( + __clc_vec16_uint64_t, __clc_vec16_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t __spirv_ocl_shuffle2( + __clc_vec2_uint64_t, __clc_vec2_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t __spirv_ocl_shuffle2( + __clc_vec4_uint64_t, __clc_vec4_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t __spirv_ocl_shuffle2( + __clc_vec8_uint64_t, __clc_vec8_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t __spirv_ocl_shuffle2( + __clc_vec16_uint64_t, __clc_vec16_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t __spirv_ocl_shuffle2( + __clc_vec2_uint64_t, __clc_vec2_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t __spirv_ocl_shuffle2( + __clc_vec4_uint64_t, __clc_vec4_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t __spirv_ocl_shuffle2( + __clc_vec8_uint64_t, __clc_vec8_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t __spirv_ocl_shuffle2( + __clc_vec16_uint64_t, __clc_vec16_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_shuffle2( + __clc_vec2_uint64_t, __clc_vec2_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_shuffle2( + __clc_vec4_uint64_t, __clc_vec4_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_shuffle2( + __clc_vec8_uint64_t, __clc_vec8_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_shuffle2( + __clc_vec16_uint64_t, __clc_vec16_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_shuffle2( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_shuffle2( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_shuffle2( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_shuffle2( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_shuffle2( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_shuffle2( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_shuffle2( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_shuffle2( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_shuffle2( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_shuffle2( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_shuffle2( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_shuffle2( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_shuffle2( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_shuffle2( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_shuffle2( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_shuffle2( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_uint32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_shuffle2( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_shuffle2( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_shuffle2( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_shuffle2( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_shuffle2( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_shuffle2( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_shuffle2( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_shuffle2( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_shuffle2( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_shuffle2( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_shuffle2( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_shuffle2( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_shuffle2( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_shuffle2( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_shuffle2( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_shuffle2( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_uint64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_shuffle2( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_shuffle2( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_shuffle2( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_shuffle2( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_shuffle2( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_shuffle2( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_shuffle2( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_shuffle2( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_shuffle2( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_shuffle2( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_shuffle2( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_shuffle2( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_shuffle2( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_shuffle2( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_shuffle2( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_shuffle2( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_uint16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_sign(__clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t diff --git a/libclc/generic/libspirv/SOURCES b/libclc/generic/libspirv/SOURCES index f52fadf1a43e..ef42990a3cdd 100644 --- a/libclc/generic/libspirv/SOURCES +++ b/libclc/generic/libspirv/SOURCES @@ -182,6 +182,8 @@ math/tanh.cl math/tanpi.cl math/tgamma.cl math/trunc.cl +misc/shuffle.cl +misc/shuffle2.cl relational/all.cl relational/any.cl relational/bitselect.cl diff --git a/libclc/generic/libspirv/misc/shuffle.cl b/libclc/generic/libspirv/misc/shuffle.cl new file mode 100644 index 000000000000..bdb413e1ae77 --- /dev/null +++ b/libclc/generic/libspirv/misc/shuffle.cl @@ -0,0 +1,174 @@ +//===----------------- generic/lib/misc/shuffle.cl ------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define _CLC_ELEMENT_CASES2(VAR) \ + case 0: \ + return VAR.s0; \ + case 1: \ + return VAR.s1; + +#define _CLC_ELEMENT_CASES4(VAR) \ + _CLC_ELEMENT_CASES2(VAR) \ + case 2: \ + return VAR.s2; \ + case 3: \ + return VAR.s3; + +#define _CLC_ELEMENT_CASES8(VAR) \ + _CLC_ELEMENT_CASES4(VAR) \ + case 4: \ + return VAR.s4; \ + case 5: \ + return VAR.s5; \ + case 6: \ + return VAR.s6; \ + case 7: \ + return VAR.s7; + +#define _CLC_ELEMENT_CASES16(VAR) \ + _CLC_ELEMENT_CASES8(VAR) \ + case 8: \ + return VAR.s8; \ + case 9: \ + return VAR.s9; \ + case 10: \ + return VAR.sA; \ + case 11: \ + return VAR.sB; \ + case 12: \ + return VAR.sC; \ + case 13: \ + return VAR.sD; \ + case 14: \ + return VAR.sE; \ + case 15: \ + return VAR.sF; + +#define _CLC_GET_ELEMENT_DEFINE(ARGTYPE, ARGSIZE, IDXTYPE) \ + inline ARGTYPE __clc_get_el_##ARGTYPE##ARGSIZE##_##IDXTYPE( \ + ARGTYPE##ARGSIZE x, IDXTYPE idx) { \ + switch (idx) { _CLC_ELEMENT_CASES##ARGSIZE(x) default : return 0; } \ + } + +#define _CLC_SHUFFLE_SET_ONE_ELEMENT(ARGTYPE, ARGSIZE, INDEX, MASKTYPE) \ + ret_val.s##INDEX = \ + __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s##INDEX); + +#define _CLC_SHUFFLE_SET_2_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + ret_val.s0 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s0); \ + ret_val.s1 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s1); + +#define _CLC_SHUFFLE_SET_4_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_SET_2_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + ret_val.s2 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s2); \ + ret_val.s3 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s3); + +#define _CLC_SHUFFLE_SET_8_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_SET_4_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + ret_val.s4 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s4); \ + ret_val.s5 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s5); \ + ret_val.s6 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s6); \ + ret_val.s7 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s7); + +#define _CLC_SHUFFLE_SET_16_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_SET_8_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + ret_val.s8 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s8); \ + ret_val.s9 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.s9); \ + ret_val.sA = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.sA); \ + ret_val.sB = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.sB); \ + ret_val.sC = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.sC); \ + ret_val.sD = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.sD); \ + ret_val.sE = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.sE); \ + ret_val.sF = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, mask.sF); + +#define _CLC_SHUFFLE_DEFINE2(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_DEF _CLC_OVERLOAD ARGTYPE##2 __spirv_ocl_shuffle(ARGTYPE##ARGSIZE x, \ + MASKTYPE##2 mask) { \ + ARGTYPE##2 ret_val; \ + mask &= (MASKTYPE##2)(ARGSIZE - 1); \ + _CLC_SHUFFLE_SET_2_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + return ret_val; \ + } + +#define _CLC_SHUFFLE_DEFINE4(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_DEF _CLC_OVERLOAD ARGTYPE##4 __spirv_ocl_shuffle(ARGTYPE##ARGSIZE x, \ + MASKTYPE##4 mask) { \ + ARGTYPE##4 ret_val; \ + mask &= (MASKTYPE##4)(ARGSIZE - 1); \ + _CLC_SHUFFLE_SET_4_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + return ret_val; \ + } + +#define _CLC_SHUFFLE_DEFINE8(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_DEF _CLC_OVERLOAD ARGTYPE##8 __spirv_ocl_shuffle(ARGTYPE##ARGSIZE x, \ + MASKTYPE##8 mask) { \ + ARGTYPE##8 ret_val; \ + mask &= (MASKTYPE##8)(ARGSIZE - 1); \ + _CLC_SHUFFLE_SET_8_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + return ret_val; \ + } + +#define _CLC_SHUFFLE_DEFINE16(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_DEF _CLC_OVERLOAD ARGTYPE##16 __spirv_ocl_shuffle(ARGTYPE##ARGSIZE x, \ + MASKTYPE##16 mask) { \ + ARGTYPE##16 ret_val; \ + mask &= (MASKTYPE##16)(ARGSIZE - 1); \ + _CLC_SHUFFLE_SET_16_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + return ret_val; \ + } + +#define _CLC_VECTOR_SHUFFLE_MASKSIZE(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_GET_ELEMENT_DEFINE(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_DEFINE2(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_DEFINE4(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_DEFINE8(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_DEFINE16(INTYPE, ARGSIZE, MASKTYPE) + +#define _CLC_VECTOR_SHUFFLE_INSIZE(TYPE, MASKTYPE) \ + _CLC_VECTOR_SHUFFLE_MASKSIZE(TYPE, 2, MASKTYPE) \ + _CLC_VECTOR_SHUFFLE_MASKSIZE(TYPE, 4, MASKTYPE) \ + _CLC_VECTOR_SHUFFLE_MASKSIZE(TYPE, 8, MASKTYPE) \ + _CLC_VECTOR_SHUFFLE_MASKSIZE(TYPE, 16, MASKTYPE) + +_CLC_VECTOR_SHUFFLE_INSIZE(char, uchar) +_CLC_VECTOR_SHUFFLE_INSIZE(schar, uchar) +_CLC_VECTOR_SHUFFLE_INSIZE(short, ushort) +_CLC_VECTOR_SHUFFLE_INSIZE(int, uint) +_CLC_VECTOR_SHUFFLE_INSIZE(long, ulong) +_CLC_VECTOR_SHUFFLE_INSIZE(uchar, uchar) +_CLC_VECTOR_SHUFFLE_INSIZE(ushort, ushort) +_CLC_VECTOR_SHUFFLE_INSIZE(uint, uint) +_CLC_VECTOR_SHUFFLE_INSIZE(ulong, ulong) +_CLC_VECTOR_SHUFFLE_INSIZE(float, uint) +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable +_CLC_VECTOR_SHUFFLE_INSIZE(double, ulong) +#endif +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +_CLC_VECTOR_SHUFFLE_INSIZE(half, ushort) +#endif + +#undef _CLC_ELEMENT_CASES2 +#undef _CLC_ELEMENT_CASES4 +#undef _CLC_ELEMENT_CASES8 +#undef _CLC_ELEMENT_CASES16 +#undef _CLC_GET_ELEMENT_DEFINE +#undef _CLC_SHUFFLE_SET_ONE_ELEMENT +#undef _CLC_SHUFFLE_SET_2_ELEMENTS +#undef _CLC_SHUFFLE_SET_4_ELEMENTS +#undef _CLC_SHUFFLE_SET_8_ELEMENTS +#undef _CLC_SHUFFLE_SET_16_ELEMENTS +#undef _CLC_SHUFFLE_DEFINE2 +#undef _CLC_SHUFFLE_DEFINE4 +#undef _CLC_SHUFFLE_DEFINE8 +#undef _CLC_SHUFFLE_DEFINE16 +#undef _CLC_VECTOR_SHUFFLE_MASKSIZE +#undef _CLC_VECTOR_SHUFFLE_INSIZE diff --git a/libclc/generic/libspirv/misc/shuffle2.cl b/libclc/generic/libspirv/misc/shuffle2.cl new file mode 100644 index 000000000000..5a3737361234 --- /dev/null +++ b/libclc/generic/libspirv/misc/shuffle2.cl @@ -0,0 +1,175 @@ +//===---------- generic/lib/misc/shuffle2.cl ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define _CLC_ELEMENT_CASES2(VAR) \ + case 0: \ + return VAR.s0; \ + case 1: \ + return VAR.s1; + +#define _CLC_ELEMENT_CASES4(VAR) \ + _CLC_ELEMENT_CASES2(VAR) \ + case 2: \ + return VAR.s2; \ + case 3: \ + return VAR.s3; + +#define _CLC_ELEMENT_CASES8(VAR) \ + _CLC_ELEMENT_CASES4(VAR) \ + case 4: \ + return VAR.s4; \ + case 5: \ + return VAR.s5; \ + case 6: \ + return VAR.s6; \ + case 7: \ + return VAR.s7; + +#define _CLC_ELEMENT_CASES16(VAR) \ + _CLC_ELEMENT_CASES8(VAR) \ + case 8: \ + return VAR.s8; \ + case 9: \ + return VAR.s9; \ + case 10: \ + return VAR.sA; \ + case 11: \ + return VAR.sB; \ + case 12: \ + return VAR.sC; \ + case 13: \ + return VAR.sD; \ + case 14: \ + return VAR.sE; \ + case 15: \ + return VAR.sF; + +#define _CLC_GET_ELEMENT_DEFINE(ARGTYPE, ARGSIZE, IDXTYPE) \ + __attribute__((always_inline)) \ + ARGTYPE __clc_get_el_##ARGTYPE##ARGSIZE##_##IDXTYPE( \ + ARGTYPE##ARGSIZE x, ARGTYPE##ARGSIZE y, IDXTYPE idx) { \ + if (idx < ARGSIZE) \ + switch (idx) { _CLC_ELEMENT_CASES##ARGSIZE(x) default : return 0; } \ + else \ + switch (idx - ARGSIZE) { \ + _CLC_ELEMENT_CASES##ARGSIZE(y) default : return 0; \ + } \ + } + +#define _CLC_SHUFFLE_SET_2_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + ret_val.s0 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s0); \ + ret_val.s1 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s1); + +#define _CLC_SHUFFLE_SET_4_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_SET_2_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + ret_val.s2 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s2); \ + ret_val.s3 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s3); + +#define _CLC_SHUFFLE_SET_8_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_SET_4_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + ret_val.s4 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s4); \ + ret_val.s5 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s5); \ + ret_val.s6 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s6); \ + ret_val.s7 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s7); + +#define _CLC_SHUFFLE_SET_16_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_SET_8_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + ret_val.s8 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s8); \ + ret_val.s9 = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.s9); \ + ret_val.sA = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.sA); \ + ret_val.sB = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.sB); \ + ret_val.sC = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.sC); \ + ret_val.sD = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.sD); \ + ret_val.sE = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.sE); \ + ret_val.sF = __clc_get_el_##ARGTYPE##ARGSIZE##_##MASKTYPE(x, y, mask.sF); + +#define _CLC_SHUFFLE_DEFINE2(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_DEF _CLC_OVERLOAD ARGTYPE##2 __spirv_ocl_shuffle2( \ + ARGTYPE##ARGSIZE x, ARGTYPE##ARGSIZE y, MASKTYPE##2 mask) { \ + ARGTYPE##2 ret_val; \ + mask &= (MASKTYPE##2)(ARGSIZE * 2 - 1); \ + _CLC_SHUFFLE_SET_2_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + return ret_val; \ + } + +#define _CLC_SHUFFLE_DEFINE4(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_DEF _CLC_OVERLOAD ARGTYPE##4 __spirv_ocl_shuffle2( \ + ARGTYPE##ARGSIZE x, ARGTYPE##ARGSIZE y, MASKTYPE##4 mask) { \ + ARGTYPE##4 ret_val; \ + mask &= (MASKTYPE##4)(ARGSIZE * 2 - 1); \ + _CLC_SHUFFLE_SET_4_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + return ret_val; \ + } + +#define _CLC_SHUFFLE_DEFINE8(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_DEF _CLC_OVERLOAD ARGTYPE##8 __spirv_ocl_shuffle2( \ + ARGTYPE##ARGSIZE x, ARGTYPE##ARGSIZE y, MASKTYPE##8 mask) { \ + ARGTYPE##8 ret_val; \ + mask &= (MASKTYPE##8)(ARGSIZE * 2 - 1); \ + _CLC_SHUFFLE_SET_8_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + return ret_val; \ + } + +#define _CLC_SHUFFLE_DEFINE16(ARGTYPE, ARGSIZE, MASKTYPE) \ + _CLC_DEF _CLC_OVERLOAD ARGTYPE##16 __spirv_ocl_shuffle2( \ + ARGTYPE##ARGSIZE x, ARGTYPE##ARGSIZE y, MASKTYPE##16 mask) { \ + ARGTYPE##16 ret_val; \ + mask &= (MASKTYPE##16)(ARGSIZE * 2 - 1); \ + _CLC_SHUFFLE_SET_16_ELEMENTS(ARGTYPE, ARGSIZE, MASKTYPE) \ + return ret_val; \ + } + +#define _CLC_VECTOR_SHUFFLE_MASKSIZE(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_GET_ELEMENT_DEFINE(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_DEFINE2(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_DEFINE4(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_DEFINE8(INTYPE, ARGSIZE, MASKTYPE) \ + _CLC_SHUFFLE_DEFINE16(INTYPE, ARGSIZE, MASKTYPE) + +#define _CLC_VECTOR_SHUFFLE_INSIZE(TYPE, MASKTYPE) \ + _CLC_VECTOR_SHUFFLE_MASKSIZE(TYPE, 2, MASKTYPE) \ + _CLC_VECTOR_SHUFFLE_MASKSIZE(TYPE, 4, MASKTYPE) \ + _CLC_VECTOR_SHUFFLE_MASKSIZE(TYPE, 8, MASKTYPE) \ + _CLC_VECTOR_SHUFFLE_MASKSIZE(TYPE, 16, MASKTYPE) + +_CLC_VECTOR_SHUFFLE_INSIZE(char, uchar) +_CLC_VECTOR_SHUFFLE_INSIZE(schar, uchar) +_CLC_VECTOR_SHUFFLE_INSIZE(short, ushort) +_CLC_VECTOR_SHUFFLE_INSIZE(int, uint) +_CLC_VECTOR_SHUFFLE_INSIZE(long, ulong) +_CLC_VECTOR_SHUFFLE_INSIZE(uchar, uchar) +_CLC_VECTOR_SHUFFLE_INSIZE(ushort, ushort) +_CLC_VECTOR_SHUFFLE_INSIZE(uint, uint) +_CLC_VECTOR_SHUFFLE_INSIZE(ulong, ulong) +_CLC_VECTOR_SHUFFLE_INSIZE(float, uint) +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable +_CLC_VECTOR_SHUFFLE_INSIZE(double, ulong) +#endif +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +_CLC_VECTOR_SHUFFLE_INSIZE(half, ushort) +#endif + +#undef _CLC_ELEMENT_CASES2 +#undef _CLC_ELEMENT_CASES4 +#undef _CLC_ELEMENT_CASES8 +#undef _CLC_ELEMENT_CASES16 +#undef _CLC_GET_ELEMENT_DEFINE +#undef _CLC_SHUFFLE_SET_2_ELEMENTS +#undef _CLC_SHUFFLE_SET_4_ELEMENTS +#undef _CLC_SHUFFLE_SET_8_ELEMENTS +#undef _CLC_SHUFFLE_SET_16_ELEMENTS +#undef _CLC_SHUFFLE_DEFINE2 +#undef _CLC_SHUFFLE_DEFINE4 +#undef _CLC_SHUFFLE_DEFINE8 +#undef _CLC_SHUFFLE_DEFINE16 +#undef _CLC_VECTOR_SHUFFLE_MASKSIZE +#undef _CLC_VECTOR_SHUFFLE_INSIZE diff --git a/libclc/test/binding/core/ConvertFToS_Rchar.cl b/libclc/test/binding/core/ConvertFToS_Rchar.cl new file mode 100644 index 000000000000..a8504a38311d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16.cl b/libclc/test/binding/core/ConvertFToS_Rchar16.cl new file mode 100644 index 000000000000..a3916808a1c0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar16_rte.cl new file mode 100644 index 000000000000..7b34b33d383f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar16_rtn.cl new file mode 100644 index 000000000000..c06d86597eb8 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar16_rtp.cl new file mode 100644 index 000000000000..0ccda99757f2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar16_rtz.cl new file mode 100644 index 000000000000..1d125a828d41 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16_sat.cl b/libclc/test/binding/core/ConvertFToS_Rchar16_sat.cl new file mode 100644 index 000000000000..e3ae73a28bb6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rte.cl new file mode 100644 index 000000000000..680851151d2b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rtn.cl new file mode 100644 index 000000000000..791a2281de6b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rtp.cl new file mode 100644 index 000000000000..be2012862b39 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rtz.cl new file mode 100644 index 000000000000..19303db1b535 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar16_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ConvertFToS_Rchar16_sat_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar16_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2.cl b/libclc/test/binding/core/ConvertFToS_Rchar2.cl new file mode 100644 index 000000000000..813746a35074 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar2_rte.cl new file mode 100644 index 000000000000..1975ebbf176e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar2_rtn.cl new file mode 100644 index 000000000000..aa88e1d7023a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar2_rtp.cl new file mode 100644 index 000000000000..a13a3419c6fc --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar2_rtz.cl new file mode 100644 index 000000000000..603b0045cb38 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2_sat.cl b/libclc/test/binding/core/ConvertFToS_Rchar2_sat.cl new file mode 100644 index 000000000000..4e72c6cdd406 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rte.cl new file mode 100644 index 000000000000..086328906c96 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rtn.cl new file mode 100644 index 000000000000..517ac4aefb02 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rtp.cl new file mode 100644 index 000000000000..f14b3ded3802 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rtz.cl new file mode 100644 index 000000000000..56de76ae18a9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar2_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ConvertFToS_Rchar2_sat_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar2_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3.cl b/libclc/test/binding/core/ConvertFToS_Rchar3.cl new file mode 100644 index 000000000000..bdedf9d47a8a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar3_rte.cl new file mode 100644 index 000000000000..14a4da1dd3c9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar3_rtn.cl new file mode 100644 index 000000000000..658981d4e7c5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar3_rtp.cl new file mode 100644 index 000000000000..b765241f93b9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar3_rtz.cl new file mode 100644 index 000000000000..0549c2419e06 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3_sat.cl b/libclc/test/binding/core/ConvertFToS_Rchar3_sat.cl new file mode 100644 index 000000000000..66a2185ab7ef --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rte.cl new file mode 100644 index 000000000000..53b012169fc1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rtn.cl new file mode 100644 index 000000000000..d984a5890256 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rtp.cl new file mode 100644 index 000000000000..b65c5f3f3b98 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rtz.cl new file mode 100644 index 000000000000..f1a744e0c3c9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar3_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ConvertFToS_Rchar3_sat_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar3_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4.cl b/libclc/test/binding/core/ConvertFToS_Rchar4.cl new file mode 100644 index 000000000000..e81c6c8405c3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar4_rte.cl new file mode 100644 index 000000000000..04d257e22553 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar4_rtn.cl new file mode 100644 index 000000000000..0aeb24361129 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar4_rtp.cl new file mode 100644 index 000000000000..a1546cd8dbf0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar4_rtz.cl new file mode 100644 index 000000000000..1c30f05b3202 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4_sat.cl b/libclc/test/binding/core/ConvertFToS_Rchar4_sat.cl new file mode 100644 index 000000000000..a0717e415a8d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rte.cl new file mode 100644 index 000000000000..b4ede1d334fa --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rtn.cl new file mode 100644 index 000000000000..9c2ad440fb1f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rtp.cl new file mode 100644 index 000000000000..904326bc87c2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rtz.cl new file mode 100644 index 000000000000..d45c4ab31e92 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar4_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ConvertFToS_Rchar4_sat_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar4_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8.cl b/libclc/test/binding/core/ConvertFToS_Rchar8.cl new file mode 100644 index 000000000000..3a505a6246d5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar8_rte.cl new file mode 100644 index 000000000000..9baf37197b61 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar8_rtn.cl new file mode 100644 index 000000000000..8eb960126d22 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar8_rtp.cl new file mode 100644 index 000000000000..54fd14782c33 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar8_rtz.cl new file mode 100644 index 000000000000..ece782cc86a8 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8_sat.cl b/libclc/test/binding/core/ConvertFToS_Rchar8_sat.cl new file mode 100644 index 000000000000..6d36f518ede4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rte.cl new file mode 100644 index 000000000000..8bdf33eefa6c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rtn.cl new file mode 100644 index 000000000000..62f541c35561 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rtp.cl new file mode 100644 index 000000000000..5567d3803c82 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rtz.cl new file mode 100644 index 000000000000..4ab2e651d376 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar8_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ConvertFToS_Rchar8_sat_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar8_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar_rte.cl new file mode 100644 index 000000000000..03a6a50607ee --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar_rtn.cl new file mode 100644 index 000000000000..351ab6de06f8 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar_rtp.cl new file mode 100644 index 000000000000..e74dce2d4876 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar_rtz.cl new file mode 100644 index 000000000000..0927fcd76cbb --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar_sat.cl b/libclc/test/binding/core/ConvertFToS_Rchar_sat.cl new file mode 100644 index 000000000000..c28618a7cc99 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rchar_sat_rte.cl new file mode 100644 index 000000000000..691765dd6345 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rchar_sat_rtn.cl new file mode 100644 index 000000000000..ad54a042e320 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rchar_sat_rtp.cl new file mode 100644 index 000000000000..a14444b26ce7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rchar_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rchar_sat_rtz.cl new file mode 100644 index 000000000000..a351aa34e5cd --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rchar_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int8_t +test___spirv_ConvertFToS_Rchar_sat_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rchar_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint.cl b/libclc/test/binding/core/ConvertFToS_Rint.cl new file mode 100644 index 000000000000..ad45947ad5be --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16.cl b/libclc/test/binding/core/ConvertFToS_Rint16.cl new file mode 100644 index 000000000000..00576f82d663 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint16_rte.cl new file mode 100644 index 000000000000..cd857b20dc4c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint16_rtn.cl new file mode 100644 index 000000000000..3ff5c7a92729 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint16_rtp.cl new file mode 100644 index 000000000000..5a79ac1c2f2f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint16_rtz.cl new file mode 100644 index 000000000000..bd94e57f9435 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16_sat.cl b/libclc/test/binding/core/ConvertFToS_Rint16_sat.cl new file mode 100644 index 000000000000..6e9cfdbcd590 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint16_sat_rte.cl new file mode 100644 index 000000000000..f8bb3e8f05df --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint16_sat_rtn.cl new file mode 100644 index 000000000000..6e400096a73c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint16_sat_rtp.cl new file mode 100644 index 000000000000..726f095ccfc9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint16_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint16_sat_rtz.cl new file mode 100644 index 000000000000..e756cdffa962 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint16_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ConvertFToS_Rint16_sat_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rint16_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2.cl b/libclc/test/binding/core/ConvertFToS_Rint2.cl new file mode 100644 index 000000000000..0c4bd90a7f97 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint2_rte.cl new file mode 100644 index 000000000000..dcb6491537c3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint2_rtn.cl new file mode 100644 index 000000000000..7a81174909ee --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint2_rtp.cl new file mode 100644 index 000000000000..9e149bba5a01 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint2_rtz.cl new file mode 100644 index 000000000000..a8620176b72d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2_sat.cl b/libclc/test/binding/core/ConvertFToS_Rint2_sat.cl new file mode 100644 index 000000000000..dea4fd73d968 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint2_sat_rte.cl new file mode 100644 index 000000000000..7bd25c134db3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint2_sat_rtn.cl new file mode 100644 index 000000000000..f29605d89bd9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint2_sat_rtp.cl new file mode 100644 index 000000000000..8b079477b818 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint2_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint2_sat_rtz.cl new file mode 100644 index 000000000000..afe34597c990 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint2_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ConvertFToS_Rint2_sat_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rint2_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3.cl b/libclc/test/binding/core/ConvertFToS_Rint3.cl new file mode 100644 index 000000000000..19098b0eb349 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint3_rte.cl new file mode 100644 index 000000000000..363b69883d9e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint3_rtn.cl new file mode 100644 index 000000000000..46c195d71925 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint3_rtp.cl new file mode 100644 index 000000000000..25613e0239d5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint3_rtz.cl new file mode 100644 index 000000000000..585b34167498 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3_sat.cl b/libclc/test/binding/core/ConvertFToS_Rint3_sat.cl new file mode 100644 index 000000000000..98f22110922b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint3_sat_rte.cl new file mode 100644 index 000000000000..396ca313cc58 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint3_sat_rtn.cl new file mode 100644 index 000000000000..0a0cbf211420 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint3_sat_rtp.cl new file mode 100644 index 000000000000..72c31cbc5b70 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint3_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint3_sat_rtz.cl new file mode 100644 index 000000000000..f19b97ca938a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint3_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ConvertFToS_Rint3_sat_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rint3_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4.cl b/libclc/test/binding/core/ConvertFToS_Rint4.cl new file mode 100644 index 000000000000..64dc6bdbc44d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint4_rte.cl new file mode 100644 index 000000000000..b0f743dd4fe3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint4_rtn.cl new file mode 100644 index 000000000000..dd6acef1e2ea --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint4_rtp.cl new file mode 100644 index 000000000000..ec8aff78a33c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint4_rtz.cl new file mode 100644 index 000000000000..c09c2409909f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4_sat.cl b/libclc/test/binding/core/ConvertFToS_Rint4_sat.cl new file mode 100644 index 000000000000..b0805910f01f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint4_sat_rte.cl new file mode 100644 index 000000000000..5e129102f829 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint4_sat_rtn.cl new file mode 100644 index 000000000000..8b96a70954a7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint4_sat_rtp.cl new file mode 100644 index 000000000000..48ce3839dd53 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint4_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint4_sat_rtz.cl new file mode 100644 index 000000000000..6948d1641722 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint4_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ConvertFToS_Rint4_sat_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rint4_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8.cl b/libclc/test/binding/core/ConvertFToS_Rint8.cl new file mode 100644 index 000000000000..52c9f6cd7561 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint8_rte.cl new file mode 100644 index 000000000000..a21c260172f4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint8_rtn.cl new file mode 100644 index 000000000000..50fef599a9c5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint8_rtp.cl new file mode 100644 index 000000000000..59dd87ca1fd6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint8_rtz.cl new file mode 100644 index 000000000000..972a61547a08 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8_sat.cl b/libclc/test/binding/core/ConvertFToS_Rint8_sat.cl new file mode 100644 index 000000000000..47e1062ed4f3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint8_sat_rte.cl new file mode 100644 index 000000000000..68e0010b494f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint8_sat_rtn.cl new file mode 100644 index 000000000000..c6a715d84aac --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint8_sat_rtp.cl new file mode 100644 index 000000000000..e03ebc90c376 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint8_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint8_sat_rtz.cl new file mode 100644 index 000000000000..31e937adee4d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint8_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ConvertFToS_Rint8_sat_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rint8_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint_rte.cl new file mode 100644 index 000000000000..ecfcc5c19586 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint_rtn.cl new file mode 100644 index 000000000000..344aa33dddd2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint_rtp.cl new file mode 100644 index 000000000000..5bfde1dc428c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint_rtz.cl new file mode 100644 index 000000000000..8e6b836a3bf4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint_sat.cl b/libclc/test/binding/core/ConvertFToS_Rint_sat.cl new file mode 100644 index 000000000000..a5f2cf25bcb5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rint_sat_rte.cl new file mode 100644 index 000000000000..396ff7a025d9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rint_sat_rtn.cl new file mode 100644 index 000000000000..00419802e514 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rint_sat_rtp.cl new file mode 100644 index 000000000000..f53cd5b59435 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rint_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rint_sat_rtz.cl new file mode 100644 index 000000000000..3fab14025bbe --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rint_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ConvertFToS_Rint_sat_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rint_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong.cl b/libclc/test/binding/core/ConvertFToS_Rlong.cl new file mode 100644 index 000000000000..e9ab0123c7b0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16.cl b/libclc/test/binding/core/ConvertFToS_Rlong16.cl new file mode 100644 index 000000000000..ce3516620b5b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong16_rte.cl new file mode 100644 index 000000000000..6af705c6593d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong16_rtn.cl new file mode 100644 index 000000000000..b10182175d24 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong16_rtp.cl new file mode 100644 index 000000000000..a7c902334e89 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong16_rtz.cl new file mode 100644 index 000000000000..6db23d31e4ee --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16_sat.cl b/libclc/test/binding/core/ConvertFToS_Rlong16_sat.cl new file mode 100644 index 000000000000..9e87ae193390 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rte.cl new file mode 100644 index 000000000000..7d344c4ae3ab --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rtn.cl new file mode 100644 index 000000000000..395ee9f5ee34 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rtp.cl new file mode 100644 index 000000000000..25cb18a60f98 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rtz.cl new file mode 100644 index 000000000000..5dec8b7c8fcb --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong16_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ConvertFToS_Rlong16_sat_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong16_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2.cl b/libclc/test/binding/core/ConvertFToS_Rlong2.cl new file mode 100644 index 000000000000..ea3b717faa6e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong2_rte.cl new file mode 100644 index 000000000000..c1e3a142e7d4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong2_rtn.cl new file mode 100644 index 000000000000..4f65d54fe53e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong2_rtp.cl new file mode 100644 index 000000000000..d0d0b807b405 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong2_rtz.cl new file mode 100644 index 000000000000..12d70a576da3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2_sat.cl b/libclc/test/binding/core/ConvertFToS_Rlong2_sat.cl new file mode 100644 index 000000000000..6b22c4a94849 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rte.cl new file mode 100644 index 000000000000..8f1dac2d5594 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rtn.cl new file mode 100644 index 000000000000..7136e080b9e4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rtp.cl new file mode 100644 index 000000000000..ba2d65eef821 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rtz.cl new file mode 100644 index 000000000000..f38e761d2528 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong2_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ConvertFToS_Rlong2_sat_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong2_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3.cl b/libclc/test/binding/core/ConvertFToS_Rlong3.cl new file mode 100644 index 000000000000..8c4b63c1bb23 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong3_rte.cl new file mode 100644 index 000000000000..3d3a1560299e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong3_rtn.cl new file mode 100644 index 000000000000..0e3bc36486c6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong3_rtp.cl new file mode 100644 index 000000000000..7985be4e1cc2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong3_rtz.cl new file mode 100644 index 000000000000..64ccda85ac12 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3_sat.cl b/libclc/test/binding/core/ConvertFToS_Rlong3_sat.cl new file mode 100644 index 000000000000..ee3803821439 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rte.cl new file mode 100644 index 000000000000..fde17c3354f0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rtn.cl new file mode 100644 index 000000000000..b8ef32bcd505 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rtp.cl new file mode 100644 index 000000000000..2f3cf4f5a881 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rtz.cl new file mode 100644 index 000000000000..d67899ac0f2f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong3_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ConvertFToS_Rlong3_sat_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong3_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4.cl b/libclc/test/binding/core/ConvertFToS_Rlong4.cl new file mode 100644 index 000000000000..d321cc224759 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong4_rte.cl new file mode 100644 index 000000000000..035836923746 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong4_rtn.cl new file mode 100644 index 000000000000..70ea5f4e2567 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong4_rtp.cl new file mode 100644 index 000000000000..8087f633f826 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong4_rtz.cl new file mode 100644 index 000000000000..0252dc349d7d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4_sat.cl b/libclc/test/binding/core/ConvertFToS_Rlong4_sat.cl new file mode 100644 index 000000000000..ae27642077c6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rte.cl new file mode 100644 index 000000000000..1c474ba4217f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rtn.cl new file mode 100644 index 000000000000..e643847b9241 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rtp.cl new file mode 100644 index 000000000000..fd5aca78cdc7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rtz.cl new file mode 100644 index 000000000000..82eab958c34b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong4_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ConvertFToS_Rlong4_sat_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong4_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8.cl b/libclc/test/binding/core/ConvertFToS_Rlong8.cl new file mode 100644 index 000000000000..a3888ddbc8d6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong8_rte.cl new file mode 100644 index 000000000000..989eebe5a66c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong8_rtn.cl new file mode 100644 index 000000000000..3feee6e31b98 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong8_rtp.cl new file mode 100644 index 000000000000..096b333bc322 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong8_rtz.cl new file mode 100644 index 000000000000..c157e3ae0f9f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8_sat.cl b/libclc/test/binding/core/ConvertFToS_Rlong8_sat.cl new file mode 100644 index 000000000000..11a055d5199b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rte.cl new file mode 100644 index 000000000000..13b784bf8474 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rtn.cl new file mode 100644 index 000000000000..2d8cea50a1a3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rtp.cl new file mode 100644 index 000000000000..f8dd773a5cbb --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rtz.cl new file mode 100644 index 000000000000..783eacb81122 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong8_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ConvertFToS_Rlong8_sat_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong8_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong_rte.cl new file mode 100644 index 000000000000..47e15f9cc361 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong_rtn.cl new file mode 100644 index 000000000000..5462396dc19a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong_rtp.cl new file mode 100644 index 000000000000..44c19ce1e253 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong_rtz.cl new file mode 100644 index 000000000000..dd85b03a4229 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong_sat.cl b/libclc/test/binding/core/ConvertFToS_Rlong_sat.cl new file mode 100644 index 000000000000..d57152e48788 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rlong_sat_rte.cl new file mode 100644 index 000000000000..60515058c48d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rlong_sat_rtn.cl new file mode 100644 index 000000000000..efead0ee04fd --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rlong_sat_rtp.cl new file mode 100644 index 000000000000..0ceff56f9318 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rlong_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rlong_sat_rtz.cl new file mode 100644 index 000000000000..be772954827f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rlong_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int64_t +test___spirv_ConvertFToS_Rlong_sat_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rlong_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort.cl b/libclc/test/binding/core/ConvertFToS_Rshort.cl new file mode 100644 index 000000000000..f13123da351f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16.cl b/libclc/test/binding/core/ConvertFToS_Rshort16.cl new file mode 100644 index 000000000000..4d4a8c08eee3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort16_rte.cl new file mode 100644 index 000000000000..20b00d94fcd8 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort16_rtn.cl new file mode 100644 index 000000000000..e9e10d7e30a3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort16_rtp.cl new file mode 100644 index 000000000000..094a6febbbfb --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort16_rtz.cl new file mode 100644 index 000000000000..3b7b17309a50 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16_sat.cl b/libclc/test/binding/core/ConvertFToS_Rshort16_sat.cl new file mode 100644 index 000000000000..469a63c7f0d4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rte.cl new file mode 100644 index 000000000000..5ce177ce5e47 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rtn.cl new file mode 100644 index 000000000000..e25f66e85cad --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rtp.cl new file mode 100644 index 000000000000..de84706776bc --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rtz.cl new file mode 100644 index 000000000000..18d39576b71c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort16_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ConvertFToS_Rshort16_sat_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort16_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2.cl b/libclc/test/binding/core/ConvertFToS_Rshort2.cl new file mode 100644 index 000000000000..c37aecd9c5e1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort2_rte.cl new file mode 100644 index 000000000000..09c0cfafa6ab --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort2_rtn.cl new file mode 100644 index 000000000000..d07cbe49f1a2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort2_rtp.cl new file mode 100644 index 000000000000..810f37974ccd --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort2_rtz.cl new file mode 100644 index 000000000000..d83a24df9388 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2_sat.cl b/libclc/test/binding/core/ConvertFToS_Rshort2_sat.cl new file mode 100644 index 000000000000..f46be0dccd91 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rte.cl new file mode 100644 index 000000000000..6b730a740221 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rtn.cl new file mode 100644 index 000000000000..4658860da4da --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rtp.cl new file mode 100644 index 000000000000..30c332da1070 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rtz.cl new file mode 100644 index 000000000000..9b72cc162a39 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort2_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ConvertFToS_Rshort2_sat_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort2_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3.cl b/libclc/test/binding/core/ConvertFToS_Rshort3.cl new file mode 100644 index 000000000000..3e62b800053b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort3_rte.cl new file mode 100644 index 000000000000..cc511fd94fd1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort3_rtn.cl new file mode 100644 index 000000000000..410f8e46a940 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort3_rtp.cl new file mode 100644 index 000000000000..78844bf05b8e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort3_rtz.cl new file mode 100644 index 000000000000..87826e87b7f7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3_sat.cl b/libclc/test/binding/core/ConvertFToS_Rshort3_sat.cl new file mode 100644 index 000000000000..aa539d0011da --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rte.cl new file mode 100644 index 000000000000..1da9c8cf4e65 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rtn.cl new file mode 100644 index 000000000000..97a850af3bef --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rtp.cl new file mode 100644 index 000000000000..572587124829 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rtz.cl new file mode 100644 index 000000000000..b22fe53ff97e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort3_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ConvertFToS_Rshort3_sat_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort3_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4.cl b/libclc/test/binding/core/ConvertFToS_Rshort4.cl new file mode 100644 index 000000000000..3b62ad2f74f4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort4_rte.cl new file mode 100644 index 000000000000..80616733c708 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort4_rtn.cl new file mode 100644 index 000000000000..ee51ff71d4f7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort4_rtp.cl new file mode 100644 index 000000000000..320bf804e220 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort4_rtz.cl new file mode 100644 index 000000000000..aac5151164a4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4_sat.cl b/libclc/test/binding/core/ConvertFToS_Rshort4_sat.cl new file mode 100644 index 000000000000..5e89b39c0c68 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rte.cl new file mode 100644 index 000000000000..79e327574dc6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rtn.cl new file mode 100644 index 000000000000..eab509693516 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rtp.cl new file mode 100644 index 000000000000..eac3b6fa0fa6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rtz.cl new file mode 100644 index 000000000000..e2224589fea7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort4_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ConvertFToS_Rshort4_sat_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort4_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8.cl b/libclc/test/binding/core/ConvertFToS_Rshort8.cl new file mode 100644 index 000000000000..78f9d19d5ed3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort8_rte.cl new file mode 100644 index 000000000000..bf968c8761c1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort8_rtn.cl new file mode 100644 index 000000000000..d00c0785421d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort8_rtp.cl new file mode 100644 index 000000000000..4e02c8ba04a9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort8_rtz.cl new file mode 100644 index 000000000000..78c705334689 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8_sat.cl b/libclc/test/binding/core/ConvertFToS_Rshort8_sat.cl new file mode 100644 index 000000000000..7566621494d8 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rte.cl new file mode 100644 index 000000000000..731b783b2c25 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rtn.cl new file mode 100644 index 000000000000..17c0ac2e7e1e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rtp.cl new file mode 100644 index 000000000000..09f78d321fa1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rtz.cl new file mode 100644 index 000000000000..504c3f53bba7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort8_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ConvertFToS_Rshort8_sat_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort8_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort_rte.cl new file mode 100644 index 000000000000..644e6173014d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort_rtn.cl new file mode 100644 index 000000000000..a4799ad5fd8a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort_rtp.cl new file mode 100644 index 000000000000..2917417d5731 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort_rtz.cl new file mode 100644 index 000000000000..9eda97bb18ba --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort_sat.cl b/libclc/test/binding/core/ConvertFToS_Rshort_sat.cl new file mode 100644 index 000000000000..824431f75c9b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort_sat_rte.cl b/libclc/test/binding/core/ConvertFToS_Rshort_sat_rte.cl new file mode 100644 index 000000000000..eecb9ed379d4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort_sat_rtn.cl b/libclc/test/binding/core/ConvertFToS_Rshort_sat_rtn.cl new file mode 100644 index 000000000000..40bd2634b6e4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort_sat_rtp.cl b/libclc/test/binding/core/ConvertFToS_Rshort_sat_rtp.cl new file mode 100644 index 000000000000..1ca7fb6b5fdd --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToS_Rshort_sat_rtz.cl b/libclc/test/binding/core/ConvertFToS_Rshort_sat_rtz.cl new file mode 100644 index 000000000000..70ecbc3dcc35 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToS_Rshort_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int16_t +test___spirv_ConvertFToS_Rshort_sat_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToS_Rshort_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar.cl b/libclc/test/binding/core/ConvertFToU_Ruchar.cl new file mode 100644 index 000000000000..3b27e3acb364 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16.cl new file mode 100644 index 000000000000..a2493d910765 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16_rte.cl new file mode 100644 index 000000000000..e809adeba733 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16_rtn.cl new file mode 100644 index 000000000000..8176198a7193 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16_rtp.cl new file mode 100644 index 000000000000..26c3313ac316 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16_rtz.cl new file mode 100644 index 000000000000..c82ba5cbec4d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat.cl new file mode 100644 index 000000000000..df4a8729486b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rte.cl new file mode 100644 index 000000000000..402b31818451 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rtn.cl new file mode 100644 index 000000000000..ec78d80ce844 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rtp.cl new file mode 100644 index 000000000000..eb15932bf07d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rtz.cl new file mode 100644 index 000000000000..c2e1d8d85a4f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar16_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ConvertFToU_Ruchar16_sat_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar16_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2.cl new file mode 100644 index 000000000000..3a1a579e75ec --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2_rte.cl new file mode 100644 index 000000000000..ddbb9388c694 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2_rtn.cl new file mode 100644 index 000000000000..6582819676d0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2_rtp.cl new file mode 100644 index 000000000000..7707c4a4b4b0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2_rtz.cl new file mode 100644 index 000000000000..cabba0dab63d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat.cl new file mode 100644 index 000000000000..49366a5d28cf --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rte.cl new file mode 100644 index 000000000000..d2df14aa71fd --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rtn.cl new file mode 100644 index 000000000000..81ca95b42946 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rtp.cl new file mode 100644 index 000000000000..c093547c159e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rtz.cl new file mode 100644 index 000000000000..4ed41fd3a8a8 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar2_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ConvertFToU_Ruchar2_sat_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar2_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3.cl new file mode 100644 index 000000000000..9acb931e6fd1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3_rte.cl new file mode 100644 index 000000000000..f27f1ff545d5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3_rtn.cl new file mode 100644 index 000000000000..62050d2a714d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3_rtp.cl new file mode 100644 index 000000000000..0ee1286987a5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3_rtz.cl new file mode 100644 index 000000000000..23f94e1cb977 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat.cl new file mode 100644 index 000000000000..2a43be5983e1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rte.cl new file mode 100644 index 000000000000..d6a2923f84d0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rtn.cl new file mode 100644 index 000000000000..5cab526e586c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rtp.cl new file mode 100644 index 000000000000..4945abec2358 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rtz.cl new file mode 100644 index 000000000000..f888d135a934 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar3_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ConvertFToU_Ruchar3_sat_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar3_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4.cl new file mode 100644 index 000000000000..6aa61e0a1994 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4_rte.cl new file mode 100644 index 000000000000..0df52fcf6339 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4_rtn.cl new file mode 100644 index 000000000000..010559cab0a1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4_rtp.cl new file mode 100644 index 000000000000..a6f0ba7a6ae1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4_rtz.cl new file mode 100644 index 000000000000..f57677e76c05 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat.cl new file mode 100644 index 000000000000..54bdc7bb83ed --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rte.cl new file mode 100644 index 000000000000..9e712111ae5e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rtn.cl new file mode 100644 index 000000000000..75bf942107ee --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rtp.cl new file mode 100644 index 000000000000..cf12ca1069f8 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rtz.cl new file mode 100644 index 000000000000..c7ebe66ad572 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar4_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ConvertFToU_Ruchar4_sat_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar4_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8.cl new file mode 100644 index 000000000000..c8c3da45ab9d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8_rte.cl new file mode 100644 index 000000000000..7114c31d7d7e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8_rtn.cl new file mode 100644 index 000000000000..afa1b61e1e41 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8_rtp.cl new file mode 100644 index 000000000000..346a714f396d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8_rtz.cl new file mode 100644 index 000000000000..dfd411bf136d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat.cl new file mode 100644 index 000000000000..b25d15e66a19 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rte.cl new file mode 100644 index 000000000000..546c454931cd --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rtn.cl new file mode 100644 index 000000000000..7a00b84c5b8a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rtp.cl new file mode 100644 index 000000000000..b94e2e5b56dd --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rtz.cl new file mode 100644 index 000000000000..d2e53605781f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar8_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ConvertFToU_Ruchar8_sat_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar8_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar_rte.cl new file mode 100644 index 000000000000..1312e79be2e6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar_rtn.cl new file mode 100644 index 000000000000..e1f63c0befb6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar_rtp.cl new file mode 100644 index 000000000000..1ee83b470609 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar_rtz.cl new file mode 100644 index 000000000000..b71071af9fc2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruchar_sat.cl new file mode 100644 index 000000000000..1ae65a1b706e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rte.cl new file mode 100644 index 000000000000..4a07372a032e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rtn.cl new file mode 100644 index 000000000000..84bfe4f91b0e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rtp.cl new file mode 100644 index 000000000000..06cf7acf568d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rtz.cl new file mode 100644 index 000000000000..89d274d10e98 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruchar_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ConvertFToU_Ruchar_sat_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruchar_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint.cl b/libclc/test/binding/core/ConvertFToU_Ruint.cl new file mode 100644 index 000000000000..d9676ab8d291 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16.cl b/libclc/test/binding/core/ConvertFToU_Ruint16.cl new file mode 100644 index 000000000000..ca6db1d52edc --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint16_rte.cl new file mode 100644 index 000000000000..728d42a3e3bf --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint16_rtn.cl new file mode 100644 index 000000000000..35d793d1d4de --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint16_rtp.cl new file mode 100644 index 000000000000..1b6a7691fcfa --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint16_rtz.cl new file mode 100644 index 000000000000..a2fe2dba5453 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruint16_sat.cl new file mode 100644 index 000000000000..774e49d5e57c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rte.cl new file mode 100644 index 000000000000..7f2f9c4be87b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rtn.cl new file mode 100644 index 000000000000..a6d2f42e7b8e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rtp.cl new file mode 100644 index 000000000000..e3f20fcecae9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rtz.cl new file mode 100644 index 000000000000..ae93d82bbe92 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint16_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ConvertFToU_Ruint16_sat_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint16_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2.cl b/libclc/test/binding/core/ConvertFToU_Ruint2.cl new file mode 100644 index 000000000000..b218002177b6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint2_rte.cl new file mode 100644 index 000000000000..527ed091d80d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint2_rtn.cl new file mode 100644 index 000000000000..b91d24ac105f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint2_rtp.cl new file mode 100644 index 000000000000..858b61a636c4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint2_rtz.cl new file mode 100644 index 000000000000..8ae3fa983d2f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruint2_sat.cl new file mode 100644 index 000000000000..6a41898cb394 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rte.cl new file mode 100644 index 000000000000..576438ca1266 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rtn.cl new file mode 100644 index 000000000000..6eb84801d2dd --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rtp.cl new file mode 100644 index 000000000000..619e7a5b7e50 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rtz.cl new file mode 100644 index 000000000000..8b5f5410f37f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint2_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ConvertFToU_Ruint2_sat_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint2_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3.cl b/libclc/test/binding/core/ConvertFToU_Ruint3.cl new file mode 100644 index 000000000000..4e0d802c6a0e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint3_rte.cl new file mode 100644 index 000000000000..ba7b190e2c42 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint3_rtn.cl new file mode 100644 index 000000000000..da3d855cdaea --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint3_rtp.cl new file mode 100644 index 000000000000..ffc3d1792051 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint3_rtz.cl new file mode 100644 index 000000000000..8c0bd1a56a32 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruint3_sat.cl new file mode 100644 index 000000000000..bdc2da0cf570 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rte.cl new file mode 100644 index 000000000000..ef7cac121907 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rtn.cl new file mode 100644 index 000000000000..9667436b692e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rtp.cl new file mode 100644 index 000000000000..d2f9f623bcb5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rtz.cl new file mode 100644 index 000000000000..6fdd5123893d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint3_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ConvertFToU_Ruint3_sat_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint3_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4.cl b/libclc/test/binding/core/ConvertFToU_Ruint4.cl new file mode 100644 index 000000000000..203dc53bf8a9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint4_rte.cl new file mode 100644 index 000000000000..b8432c3f71d6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint4_rtn.cl new file mode 100644 index 000000000000..3505e2e75370 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint4_rtp.cl new file mode 100644 index 000000000000..5ee6960b1851 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint4_rtz.cl new file mode 100644 index 000000000000..b124eb0b3c9f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruint4_sat.cl new file mode 100644 index 000000000000..5171a0f5421f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rte.cl new file mode 100644 index 000000000000..6a5dfe1cab14 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rtn.cl new file mode 100644 index 000000000000..68d04499ef3a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rtp.cl new file mode 100644 index 000000000000..c6b8a448fb95 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rtz.cl new file mode 100644 index 000000000000..5269be3f37c3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint4_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ConvertFToU_Ruint4_sat_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint4_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8.cl b/libclc/test/binding/core/ConvertFToU_Ruint8.cl new file mode 100644 index 000000000000..a2bf64a879da --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint8_rte.cl new file mode 100644 index 000000000000..c0078292f5bc --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint8_rtn.cl new file mode 100644 index 000000000000..97cdc2c75275 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint8_rtp.cl new file mode 100644 index 000000000000..c2f51facff41 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint8_rtz.cl new file mode 100644 index 000000000000..afe1d715da44 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruint8_sat.cl new file mode 100644 index 000000000000..36d7492004cb --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rte.cl new file mode 100644 index 000000000000..b2b26737daf0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rtn.cl new file mode 100644 index 000000000000..35532003b5c2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rtp.cl new file mode 100644 index 000000000000..e6062af25ce7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rtz.cl new file mode 100644 index 000000000000..b28002f9a7c0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint8_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ConvertFToU_Ruint8_sat_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint8_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint_rte.cl new file mode 100644 index 000000000000..ff96b60877ab --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint_rtn.cl new file mode 100644 index 000000000000..3e4df70c3775 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint_rtp.cl new file mode 100644 index 000000000000..26924f62a433 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint_rtz.cl new file mode 100644 index 000000000000..620003694846 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint_sat.cl b/libclc/test/binding/core/ConvertFToU_Ruint_sat.cl new file mode 100644 index 000000000000..95b0dbdae40b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Ruint_sat_rte.cl new file mode 100644 index 000000000000..afef42e0bbc3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Ruint_sat_rtn.cl new file mode 100644 index 000000000000..2a3c8da8204a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Ruint_sat_rtp.cl new file mode 100644 index 000000000000..9eba08f982e0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Ruint_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Ruint_sat_rtz.cl new file mode 100644 index 000000000000..6727d7e0d733 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Ruint_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ConvertFToU_Ruint_sat_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Ruint_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong.cl b/libclc/test/binding/core/ConvertFToU_Rulong.cl new file mode 100644 index 000000000000..1c5d23a6a675 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16.cl b/libclc/test/binding/core/ConvertFToU_Rulong16.cl new file mode 100644 index 000000000000..2dad217a169c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong16_rte.cl new file mode 100644 index 000000000000..c9d4cba28564 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong16_rtn.cl new file mode 100644 index 000000000000..d607e11f8df1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong16_rtp.cl new file mode 100644 index 000000000000..1fd13577159e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong16_rtz.cl new file mode 100644 index 000000000000..6dac8d1639c1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16_sat.cl b/libclc/test/binding/core/ConvertFToU_Rulong16_sat.cl new file mode 100644 index 000000000000..3418aba7ba8b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rte.cl new file mode 100644 index 000000000000..ac67ca24b269 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rtn.cl new file mode 100644 index 000000000000..d7d9efc14f28 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rtp.cl new file mode 100644 index 000000000000..0f6b4ef8f0d2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rtz.cl new file mode 100644 index 000000000000..7750bc1df82b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong16_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ConvertFToU_Rulong16_sat_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong16_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2.cl b/libclc/test/binding/core/ConvertFToU_Rulong2.cl new file mode 100644 index 000000000000..f205361ca5e1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong2_rte.cl new file mode 100644 index 000000000000..8099da37a0e1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong2_rtn.cl new file mode 100644 index 000000000000..5b8be0b4fc68 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong2_rtp.cl new file mode 100644 index 000000000000..373904380d42 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong2_rtz.cl new file mode 100644 index 000000000000..b817bec14164 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2_sat.cl b/libclc/test/binding/core/ConvertFToU_Rulong2_sat.cl new file mode 100644 index 000000000000..3724e462b73f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rte.cl new file mode 100644 index 000000000000..fb64a48b6f1e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rtn.cl new file mode 100644 index 000000000000..4989599d8228 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rtp.cl new file mode 100644 index 000000000000..a748f84e6ab6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rtz.cl new file mode 100644 index 000000000000..94c284aa4ab9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong2_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ConvertFToU_Rulong2_sat_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong2_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3.cl b/libclc/test/binding/core/ConvertFToU_Rulong3.cl new file mode 100644 index 000000000000..ce37396d305f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong3_rte.cl new file mode 100644 index 000000000000..77bf421ff7a2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong3_rtn.cl new file mode 100644 index 000000000000..1906be2ccefb --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong3_rtp.cl new file mode 100644 index 000000000000..5fbdad4f09c3 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong3_rtz.cl new file mode 100644 index 000000000000..d318f63ef9be --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3_sat.cl b/libclc/test/binding/core/ConvertFToU_Rulong3_sat.cl new file mode 100644 index 000000000000..b3abff0155ec --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rte.cl new file mode 100644 index 000000000000..294b4c01d88f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rtn.cl new file mode 100644 index 000000000000..dcb85a70ff12 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rtp.cl new file mode 100644 index 000000000000..5bf53b10fa0a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rtz.cl new file mode 100644 index 000000000000..5213b97cede7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong3_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ConvertFToU_Rulong3_sat_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong3_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4.cl b/libclc/test/binding/core/ConvertFToU_Rulong4.cl new file mode 100644 index 000000000000..1557fc18a25d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong4_rte.cl new file mode 100644 index 000000000000..c4819227308b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong4_rtn.cl new file mode 100644 index 000000000000..c495da1caf37 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong4_rtp.cl new file mode 100644 index 000000000000..1d55968434ce --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong4_rtz.cl new file mode 100644 index 000000000000..54889f294e3a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4_sat.cl b/libclc/test/binding/core/ConvertFToU_Rulong4_sat.cl new file mode 100644 index 000000000000..4203b429fe39 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rte.cl new file mode 100644 index 000000000000..28ef6c8ee640 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rtn.cl new file mode 100644 index 000000000000..9d20ca964eee --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rtp.cl new file mode 100644 index 000000000000..909421e62162 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rtz.cl new file mode 100644 index 000000000000..dc646b51ebef --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong4_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ConvertFToU_Rulong4_sat_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong4_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8.cl b/libclc/test/binding/core/ConvertFToU_Rulong8.cl new file mode 100644 index 000000000000..5f2540349614 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong8_rte.cl new file mode 100644 index 000000000000..330f97860399 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong8_rtn.cl new file mode 100644 index 000000000000..b873d6469c0e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong8_rtp.cl new file mode 100644 index 000000000000..fa2da0e3e6ba --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong8_rtz.cl new file mode 100644 index 000000000000..a3568aaf249f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8_sat.cl b/libclc/test/binding/core/ConvertFToU_Rulong8_sat.cl new file mode 100644 index 000000000000..ebfaa529f8e7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rte.cl new file mode 100644 index 000000000000..27ac7654e37a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rtn.cl new file mode 100644 index 000000000000..23aac418601c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rtp.cl new file mode 100644 index 000000000000..27c4e08e94de --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rtz.cl new file mode 100644 index 000000000000..edab691939b9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong8_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ConvertFToU_Rulong8_sat_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong8_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong_rte.cl new file mode 100644 index 000000000000..e1f755b1ef83 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong_rtn.cl new file mode 100644 index 000000000000..6ad1f6a29d2d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong_rtp.cl new file mode 100644 index 000000000000..5031b44da2e9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong_rtz.cl new file mode 100644 index 000000000000..22e45076345d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong_sat.cl b/libclc/test/binding/core/ConvertFToU_Rulong_sat.cl new file mode 100644 index 000000000000..3d928c3ccc41 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rulong_sat_rte.cl new file mode 100644 index 000000000000..2fcc6720172c --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rulong_sat_rtn.cl new file mode 100644 index 000000000000..90e728fa02c5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rulong_sat_rtp.cl new file mode 100644 index 000000000000..869ffb80bde4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rulong_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rulong_sat_rtz.cl new file mode 100644 index 000000000000..3e6d99937326 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rulong_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ConvertFToU_Rulong_sat_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rulong_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort.cl b/libclc/test/binding/core/ConvertFToU_Rushort.cl new file mode 100644 index 000000000000..5cd12e1f55a9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16.cl b/libclc/test/binding/core/ConvertFToU_Rushort16.cl new file mode 100644 index 000000000000..597aa2a802df --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort16_rte.cl new file mode 100644 index 000000000000..d70647106c3b --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort16_rtn.cl new file mode 100644 index 000000000000..993e0a47d427 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort16_rtp.cl new file mode 100644 index 000000000000..9b8a91a090aa --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort16_rtz.cl new file mode 100644 index 000000000000..12c7d88741d4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16_sat.cl b/libclc/test/binding/core/ConvertFToU_Rushort16_sat.cl new file mode 100644 index 000000000000..c05de7082035 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rte.cl new file mode 100644 index 000000000000..b9dd7c39776a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rte(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rte(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rte(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rtn.cl new file mode 100644 index 000000000000..24ecd75246f4 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rtp.cl new file mode 100644 index 000000000000..3fa371c0d3ff --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rtz.cl new file mode 100644 index 000000000000..08c6f9a774a7 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort16_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ConvertFToU_Rushort16_sat_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort16_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2.cl b/libclc/test/binding/core/ConvertFToU_Rushort2.cl new file mode 100644 index 000000000000..e4f78ef5755a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort2_rte.cl new file mode 100644 index 000000000000..bd9ee8821f1e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort2_rtn.cl new file mode 100644 index 000000000000..4f62ed62c20e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort2_rtp.cl new file mode 100644 index 000000000000..256d41737183 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort2_rtz.cl new file mode 100644 index 000000000000..696d4d2d7707 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2_sat.cl b/libclc/test/binding/core/ConvertFToU_Rushort2_sat.cl new file mode 100644 index 000000000000..5c108240be21 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rte.cl new file mode 100644 index 000000000000..c05e747775bc --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rte(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rte(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rte(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rtn.cl new file mode 100644 index 000000000000..3e92e66e007f --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rtp.cl new file mode 100644 index 000000000000..f234b05afb34 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rtz.cl new file mode 100644 index 000000000000..7cc364902296 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort2_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ConvertFToU_Rushort2_sat_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort2_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3.cl b/libclc/test/binding/core/ConvertFToU_Rushort3.cl new file mode 100644 index 000000000000..6fd11caac454 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort3_rte.cl new file mode 100644 index 000000000000..da5912737035 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort3_rtn.cl new file mode 100644 index 000000000000..4aea9685e3f5 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort3_rtp.cl new file mode 100644 index 000000000000..b7de0683f9ea --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort3_rtz.cl new file mode 100644 index 000000000000..1b2c545c7999 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3_sat.cl b/libclc/test/binding/core/ConvertFToU_Rushort3_sat.cl new file mode 100644 index 000000000000..bbe5a5e21c54 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rte.cl new file mode 100644 index 000000000000..6cf4ee4a4538 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rte(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rte(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rte(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rtn.cl new file mode 100644 index 000000000000..552321ba9b00 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rtp.cl new file mode 100644 index 000000000000..bdc02cb02174 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rtz.cl new file mode 100644 index 000000000000..aab4edfe4379 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort3_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ConvertFToU_Rushort3_sat_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort3_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4.cl b/libclc/test/binding/core/ConvertFToU_Rushort4.cl new file mode 100644 index 000000000000..38c71cf01529 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort4_rte.cl new file mode 100644 index 000000000000..e56f2b976580 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort4_rtn.cl new file mode 100644 index 000000000000..7e9a69e976dd --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort4_rtp.cl new file mode 100644 index 000000000000..37d2adf0e95a --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort4_rtz.cl new file mode 100644 index 000000000000..7c74329059f6 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4_sat.cl b/libclc/test/binding/core/ConvertFToU_Rushort4_sat.cl new file mode 100644 index 000000000000..aa17e8d53d57 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rte.cl new file mode 100644 index 000000000000..19d882d73414 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rte(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rte(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rte(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rtn.cl new file mode 100644 index 000000000000..c3a7316768ea --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rtp.cl new file mode 100644 index 000000000000..b2db4f3cb062 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rtz.cl new file mode 100644 index 000000000000..fcd9d89fab5e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort4_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ConvertFToU_Rushort4_sat_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort4_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8.cl b/libclc/test/binding/core/ConvertFToU_Rushort8.cl new file mode 100644 index 000000000000..5c3b6a0a8a64 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort8_rte.cl new file mode 100644 index 000000000000..b4ed7c959aec --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort8_rtn.cl new file mode 100644 index 000000000000..60e6a37f1dc2 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort8_rtp.cl new file mode 100644 index 000000000000..05b1b7b2f1a1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort8_rtz.cl new file mode 100644 index 000000000000..3ae127ff68e0 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8_sat.cl b/libclc/test/binding/core/ConvertFToU_Rushort8_sat.cl new file mode 100644 index 000000000000..a17aa4d7af6d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rte.cl new file mode 100644 index 000000000000..2de7d0e59610 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rte(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rte(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rte(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rtn.cl new file mode 100644 index 000000000000..885a6906655d --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rtp.cl new file mode 100644 index 000000000000..e2d039d1b8fe --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rtz.cl new file mode 100644 index 000000000000..3801992534ae --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort8_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ConvertFToU_Rushort8_sat_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort8_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort_rte.cl new file mode 100644 index 000000000000..b2dfb545aacb --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort_rtn.cl new file mode 100644 index 000000000000..3f3dded63066 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort_rtp.cl new file mode 100644 index 000000000000..ec8e7f85d02e --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort_rtz.cl new file mode 100644 index 000000000000..10112371fbda --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort_sat.cl b/libclc/test/binding/core/ConvertFToU_Rushort_sat.cl new file mode 100644 index 000000000000..1a3dab97a4c9 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort_sat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort_sat(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort_sat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort_sat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort_sat_rte.cl b/libclc/test/binding/core/ConvertFToU_Rushort_sat_rte.cl new file mode 100644 index 000000000000..1b9c5967ced1 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort_sat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rte(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rte(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rte(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rte(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort_sat_rtn.cl b/libclc/test/binding/core/ConvertFToU_Rushort_sat_rtn.cl new file mode 100644 index 000000000000..9da732a5c1ce --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort_sat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rtn(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rtn(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rtn(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rtn(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort_sat_rtp.cl b/libclc/test/binding/core/ConvertFToU_Rushort_sat_rtp.cl new file mode 100644 index 000000000000..d6fb3f77b8dc --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort_sat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rtp(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rtp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rtp(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rtp(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertFToU_Rushort_sat_rtz.cl b/libclc/test/binding/core/ConvertFToU_Rushort_sat_rtz.cl new file mode 100644 index 000000000000..13253fe45f26 --- /dev/null +++ b/libclc/test/binding/core/ConvertFToU_Rushort_sat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rtz(__clc_fp32_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rtz(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rtz(__clc_fp64_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ConvertFToU_Rushort_sat_rtz(__clc_fp16_t args_0) { + return __spirv_ConvertFToU_Rushort_sat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble.cl b/libclc/test/binding/core/ConvertSToF_Rdouble.cl new file mode 100644 index 000000000000..2b12fde37ad0 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble16.cl b/libclc/test/binding/core/ConvertSToF_Rdouble16.cl new file mode 100644 index 000000000000..8f2f8815b9d6 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble16.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble16(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble16(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble16(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble16_rte.cl b/libclc/test/binding/core/ConvertSToF_Rdouble16_rte.cl new file mode 100644 index 000000000000..333cbefc9a92 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble16_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rte(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rte(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rte(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rte(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble16_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rdouble16_rtn.cl new file mode 100644 index 000000000000..fb4e4230efb0 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble16_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtn(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtn(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtn(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtn(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble16_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rdouble16_rtp.cl new file mode 100644 index 000000000000..79f70e94151a --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble16_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtp(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtp(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtp(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtp(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble16_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rdouble16_rtz.cl new file mode 100644 index 000000000000..f6da250fee17 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble16_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtz(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtz(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtz(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertSToF_Rdouble16_rtz(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble2.cl b/libclc/test/binding/core/ConvertSToF_Rdouble2.cl new file mode 100644 index 000000000000..3128aef73156 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble2.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble2_rte.cl b/libclc/test/binding/core/ConvertSToF_Rdouble2_rte.cl new file mode 100644 index 000000000000..c135bf85ae64 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble2_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rte(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rte(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rte(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rte(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble2_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rdouble2_rtn.cl new file mode 100644 index 000000000000..1315850f5185 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble2_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtn(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtn(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtn(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtn(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble2_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rdouble2_rtp.cl new file mode 100644 index 000000000000..81fa4115aac5 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble2_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtp(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtp(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtp(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtp(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble2_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rdouble2_rtz.cl new file mode 100644 index 000000000000..adf844de9af6 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble2_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtz(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtz(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtz(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertSToF_Rdouble2_rtz(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble3.cl b/libclc/test/binding/core/ConvertSToF_Rdouble3.cl new file mode 100644 index 000000000000..672a5797eef2 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble3.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble3(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble3(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble3(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble3_rte.cl b/libclc/test/binding/core/ConvertSToF_Rdouble3_rte.cl new file mode 100644 index 000000000000..a964fac5b389 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble3_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rte(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rte(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rte(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rte(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble3_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rdouble3_rtn.cl new file mode 100644 index 000000000000..22b35bfaa4bf --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble3_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtn(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtn(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtn(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtn(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble3_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rdouble3_rtp.cl new file mode 100644 index 000000000000..52b078e8dcc5 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble3_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtp(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtp(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtp(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtp(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble3_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rdouble3_rtz.cl new file mode 100644 index 000000000000..c174ec95d762 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble3_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtz(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtz(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtz(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertSToF_Rdouble3_rtz(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble4.cl b/libclc/test/binding/core/ConvertSToF_Rdouble4.cl new file mode 100644 index 000000000000..0df9dbabadce --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble4.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble4(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble4(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble4(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble4_rte.cl b/libclc/test/binding/core/ConvertSToF_Rdouble4_rte.cl new file mode 100644 index 000000000000..285262bf3b24 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble4_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rte(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rte(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rte(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rte(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble4_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rdouble4_rtn.cl new file mode 100644 index 000000000000..75fae76430bf --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble4_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtn(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtn(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtn(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtn(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble4_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rdouble4_rtp.cl new file mode 100644 index 000000000000..d2693a793b75 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble4_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtp(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtp(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtp(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtp(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble4_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rdouble4_rtz.cl new file mode 100644 index 000000000000..e674b53797da --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble4_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtz(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtz(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtz(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertSToF_Rdouble4_rtz(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble8.cl b/libclc/test/binding/core/ConvertSToF_Rdouble8.cl new file mode 100644 index 000000000000..7c1ec383f5f3 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble8.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble8(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble8(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble8(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble8_rte.cl b/libclc/test/binding/core/ConvertSToF_Rdouble8_rte.cl new file mode 100644 index 000000000000..e533897aceac --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble8_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rte(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rte(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rte(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rte(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble8_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rdouble8_rtn.cl new file mode 100644 index 000000000000..f0fb193ba680 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble8_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtn(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtn(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtn(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtn(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble8_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rdouble8_rtp.cl new file mode 100644 index 000000000000..ae30bf9839c6 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble8_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtp(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtp(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtp(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtp(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble8_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rdouble8_rtz.cl new file mode 100644 index 000000000000..edc2209312fd --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble8_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtz(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtz(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtz(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertSToF_Rdouble8_rtz(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble_rte.cl b/libclc/test/binding/core/ConvertSToF_Rdouble_rte.cl new file mode 100644 index 000000000000..b5b1d7575835 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rte(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rte(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rte(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rte(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rdouble_rtn.cl new file mode 100644 index 000000000000..793d1f7655e1 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtn(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtn(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtn(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtn(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rdouble_rtp.cl new file mode 100644 index 000000000000..906e343d43eb --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtp(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtp(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtp(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtp(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rdouble_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rdouble_rtz.cl new file mode 100644 index 000000000000..f69878124646 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rdouble_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtz(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtz(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtz(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertSToF_Rdouble_rtz(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rdouble_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat.cl b/libclc/test/binding/core/ConvertSToF_Rfloat.cl new file mode 100644 index 000000000000..f3684f02ab88 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat16.cl b/libclc/test/binding/core/ConvertSToF_Rfloat16.cl new file mode 100644 index 000000000000..47f301b4bf04 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat16(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat16_rte.cl b/libclc/test/binding/core/ConvertSToF_Rfloat16_rte.cl new file mode 100644 index 000000000000..d03f05e3b752 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rte(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rte(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rte(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rte(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat16_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rfloat16_rtn.cl new file mode 100644 index 000000000000..a596561a823b --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtn(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtn(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtn(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtn(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat16_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rfloat16_rtp.cl new file mode 100644 index 000000000000..2324bde60c46 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtp(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtp(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtp(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtp(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat16_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rfloat16_rtz.cl new file mode 100644 index 000000000000..95e4f0a5b993 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtz(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtz(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtz(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertSToF_Rfloat16_rtz(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat16_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat2.cl b/libclc/test/binding/core/ConvertSToF_Rfloat2.cl new file mode 100644 index 000000000000..de6a0c2d6808 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat2(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat2_rte.cl b/libclc/test/binding/core/ConvertSToF_Rfloat2_rte.cl new file mode 100644 index 000000000000..a80b054483b4 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rte(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rte(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rte(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rte(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat2_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rfloat2_rtn.cl new file mode 100644 index 000000000000..115fd63c00cc --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtn(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtn(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtn(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtn(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat2_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rfloat2_rtp.cl new file mode 100644 index 000000000000..51e4f48c1fcf --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtp(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtp(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtp(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtp(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat2_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rfloat2_rtz.cl new file mode 100644 index 000000000000..9c902297e8d4 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtz(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtz(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtz(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertSToF_Rfloat2_rtz(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat2_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat3.cl b/libclc/test/binding/core/ConvertSToF_Rfloat3.cl new file mode 100644 index 000000000000..65dc39e20aa8 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat3(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat3_rte.cl b/libclc/test/binding/core/ConvertSToF_Rfloat3_rte.cl new file mode 100644 index 000000000000..8f8c9dbe1e87 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rte(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rte(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rte(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rte(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat3_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rfloat3_rtn.cl new file mode 100644 index 000000000000..391adf8fc15c --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtn(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtn(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtn(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtn(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat3_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rfloat3_rtp.cl new file mode 100644 index 000000000000..200433965403 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtp(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtp(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtp(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtp(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat3_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rfloat3_rtz.cl new file mode 100644 index 000000000000..7f809faab1a8 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtz(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtz(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtz(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertSToF_Rfloat3_rtz(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat3_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat4.cl b/libclc/test/binding/core/ConvertSToF_Rfloat4.cl new file mode 100644 index 000000000000..ce707d1a0bf8 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat4(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat4_rte.cl b/libclc/test/binding/core/ConvertSToF_Rfloat4_rte.cl new file mode 100644 index 000000000000..cb467c04735d --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rte(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rte(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rte(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rte(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat4_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rfloat4_rtn.cl new file mode 100644 index 000000000000..afd47d7ea04c --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtn(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtn(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtn(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtn(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat4_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rfloat4_rtp.cl new file mode 100644 index 000000000000..2f40215e48fb --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtp(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtp(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtp(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtp(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat4_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rfloat4_rtz.cl new file mode 100644 index 000000000000..66caba6f6f88 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtz(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtz(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtz(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertSToF_Rfloat4_rtz(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat4_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat8.cl b/libclc/test/binding/core/ConvertSToF_Rfloat8.cl new file mode 100644 index 000000000000..c2a47fe7fed2 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat8(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat8_rte.cl b/libclc/test/binding/core/ConvertSToF_Rfloat8_rte.cl new file mode 100644 index 000000000000..90b913cf5eb8 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rte(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rte(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rte(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rte(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat8_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rfloat8_rtn.cl new file mode 100644 index 000000000000..183247456cfb --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtn(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtn(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtn(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtn(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat8_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rfloat8_rtp.cl new file mode 100644 index 000000000000..eacc5b83a938 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtp(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtp(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtp(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtp(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat8_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rfloat8_rtz.cl new file mode 100644 index 000000000000..02efcdad27bb --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtz(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtz(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtz(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertSToF_Rfloat8_rtz(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat8_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat_rte.cl b/libclc/test/binding/core/ConvertSToF_Rfloat_rte.cl new file mode 100644 index 000000000000..29278e16c157 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rte(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat_rte(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rte(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat_rte(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rte(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat_rte(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rte(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rfloat_rtn.cl new file mode 100644 index 000000000000..37f443fd8719 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtn(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtn(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtn(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtn(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtn(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtn(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtn(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rfloat_rtp.cl new file mode 100644 index 000000000000..7bc541cc1694 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtp(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtp(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtp(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtp(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtp(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtp(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtp(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rfloat_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rfloat_rtz.cl new file mode 100644 index 000000000000..0ea812e7bdbd --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rfloat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtz(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtz(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtz(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtz(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtz(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtz(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertSToF_Rfloat_rtz(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rfloat_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf.cl b/libclc/test/binding/core/ConvertSToF_Rhalf.cl new file mode 100644 index 000000000000..236b677492ad --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf16.cl b/libclc/test/binding/core/ConvertSToF_Rhalf16.cl new file mode 100644 index 000000000000..ecf4afbe174d --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf16.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf16_rte.cl b/libclc/test/binding/core/ConvertSToF_Rhalf16_rte.cl new file mode 100644 index 000000000000..192ae9b8d3ec --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf16_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rte(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rte(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rte(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rte(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf16_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rhalf16_rtn.cl new file mode 100644 index 000000000000..099658f43b25 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf16_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtn(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtn(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtn(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtn(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf16_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rhalf16_rtp.cl new file mode 100644 index 000000000000..e23f43c8cf76 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf16_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtp(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtp(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtp(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtp(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf16_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rhalf16_rtz.cl new file mode 100644 index 000000000000..82ea6583b5c8 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf16_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtz(__clc_vec16_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtz(__clc_vec16_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtz(__clc_vec16_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertSToF_Rhalf16_rtz(__clc_vec16_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf2.cl b/libclc/test/binding/core/ConvertSToF_Rhalf2.cl new file mode 100644 index 000000000000..93de14525c7a --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf2.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf2_rte.cl b/libclc/test/binding/core/ConvertSToF_Rhalf2_rte.cl new file mode 100644 index 000000000000..21715626ddcc --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf2_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rte(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rte(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rte(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rte(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf2_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rhalf2_rtn.cl new file mode 100644 index 000000000000..b42544ec38eb --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf2_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtn(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtn(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtn(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtn(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf2_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rhalf2_rtp.cl new file mode 100644 index 000000000000..1896c23d42de --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf2_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtp(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtp(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtp(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtp(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf2_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rhalf2_rtz.cl new file mode 100644 index 000000000000..0f9f4d64d817 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf2_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtz(__clc_vec2_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtz(__clc_vec2_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtz(__clc_vec2_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertSToF_Rhalf2_rtz(__clc_vec2_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf3.cl b/libclc/test/binding/core/ConvertSToF_Rhalf3.cl new file mode 100644 index 000000000000..046bfbd9ab63 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf3.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf3_rte.cl b/libclc/test/binding/core/ConvertSToF_Rhalf3_rte.cl new file mode 100644 index 000000000000..76bf2e9e3d08 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf3_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rte(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rte(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rte(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rte(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf3_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rhalf3_rtn.cl new file mode 100644 index 000000000000..f15b15502c8b --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf3_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtn(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtn(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtn(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtn(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf3_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rhalf3_rtp.cl new file mode 100644 index 000000000000..9af81df96d5a --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf3_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtp(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtp(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtp(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtp(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf3_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rhalf3_rtz.cl new file mode 100644 index 000000000000..17d855c84d1e --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf3_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtz(__clc_vec3_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtz(__clc_vec3_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtz(__clc_vec3_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertSToF_Rhalf3_rtz(__clc_vec3_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf4.cl b/libclc/test/binding/core/ConvertSToF_Rhalf4.cl new file mode 100644 index 000000000000..3ad0c861c8a3 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf4.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf4_rte.cl b/libclc/test/binding/core/ConvertSToF_Rhalf4_rte.cl new file mode 100644 index 000000000000..b9a87982e388 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf4_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rte(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rte(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rte(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rte(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf4_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rhalf4_rtn.cl new file mode 100644 index 000000000000..65a8c41ecfa9 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf4_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtn(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtn(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtn(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtn(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf4_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rhalf4_rtp.cl new file mode 100644 index 000000000000..b67ca8d73d5b --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf4_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtp(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtp(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtp(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtp(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf4_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rhalf4_rtz.cl new file mode 100644 index 000000000000..e32ff3f5e3e9 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf4_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtz(__clc_vec4_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtz(__clc_vec4_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtz(__clc_vec4_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertSToF_Rhalf4_rtz(__clc_vec4_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf8.cl b/libclc/test/binding/core/ConvertSToF_Rhalf8.cl new file mode 100644 index 000000000000..41481126ecdc --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf8.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf8_rte.cl b/libclc/test/binding/core/ConvertSToF_Rhalf8_rte.cl new file mode 100644 index 000000000000..e9f105fb17fd --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf8_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rte(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rte(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rte(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rte(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf8_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rhalf8_rtn.cl new file mode 100644 index 000000000000..640674f0dd67 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf8_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtn(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtn(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtn(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtn(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf8_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rhalf8_rtp.cl new file mode 100644 index 000000000000..cff633462e43 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf8_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtp(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtp(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtp(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtp(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf8_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rhalf8_rtz.cl new file mode 100644 index 000000000000..a5d4e02ce0a2 --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf8_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtz(__clc_vec8_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtz(__clc_vec8_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtz(__clc_vec8_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertSToF_Rhalf8_rtz(__clc_vec8_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf_rte.cl b/libclc/test/binding/core/ConvertSToF_Rhalf_rte.cl new file mode 100644 index 000000000000..08bbad2b9faf --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rte(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rte(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rte(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rte(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf_rtn.cl b/libclc/test/binding/core/ConvertSToF_Rhalf_rtn.cl new file mode 100644 index 000000000000..95938c03b14f --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtn(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtn(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtn(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtn(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf_rtp.cl b/libclc/test/binding/core/ConvertSToF_Rhalf_rtp.cl new file mode 100644 index 000000000000..0d35bfd2bd1c --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtp(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtp(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtp(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtp(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertSToF_Rhalf_rtz.cl b/libclc/test/binding/core/ConvertSToF_Rhalf_rtz.cl new file mode 100644 index 000000000000..2fefb9d4f96e --- /dev/null +++ b/libclc/test/binding/core/ConvertSToF_Rhalf_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtz(__clc_int8_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtz(__clc_int16_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtz(__clc_int32_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertSToF_Rhalf_rtz(__clc_int64_t args_0) { + return __spirv_ConvertSToF_Rhalf_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble.cl b/libclc/test/binding/core/ConvertUToF_Rdouble.cl new file mode 100644 index 000000000000..711996aef27a --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble16.cl b/libclc/test/binding/core/ConvertUToF_Rdouble16.cl new file mode 100644 index 000000000000..49d7c0199364 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble16.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble16(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble16(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble16(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble16_rte.cl b/libclc/test/binding/core/ConvertUToF_Rdouble16_rte.cl new file mode 100644 index 000000000000..a7e91e3c6bfb --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble16_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rte(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rte(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rte(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rte(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble16_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rdouble16_rtn.cl new file mode 100644 index 000000000000..1a7edb39b4b0 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble16_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtn(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtn(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtn(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtn(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble16_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rdouble16_rtp.cl new file mode 100644 index 000000000000..059850ca6cc1 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble16_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtp(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtp(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtp(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtp(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble16_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rdouble16_rtz.cl new file mode 100644 index 000000000000..880314f5a0ff --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble16_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtz(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtz(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtz(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ConvertUToF_Rdouble16_rtz(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble2.cl b/libclc/test/binding/core/ConvertUToF_Rdouble2.cl new file mode 100644 index 000000000000..0ce30344edde --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble2.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble2_rte.cl b/libclc/test/binding/core/ConvertUToF_Rdouble2_rte.cl new file mode 100644 index 000000000000..843451dc83d1 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble2_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rte(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rte(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rte(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rte(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble2_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rdouble2_rtn.cl new file mode 100644 index 000000000000..e3e29e9892d2 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble2_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtn(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtn(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtn(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtn(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble2_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rdouble2_rtp.cl new file mode 100644 index 000000000000..b9a196cf7ca7 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble2_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtp(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtp(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtp(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtp(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble2_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rdouble2_rtz.cl new file mode 100644 index 000000000000..51e7b7f5855b --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble2_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtz(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtz(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtz(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ConvertUToF_Rdouble2_rtz(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble3.cl b/libclc/test/binding/core/ConvertUToF_Rdouble3.cl new file mode 100644 index 000000000000..06e546d7298d --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble3.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble3(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble3(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble3(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble3_rte.cl b/libclc/test/binding/core/ConvertUToF_Rdouble3_rte.cl new file mode 100644 index 000000000000..374a5109bb57 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble3_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rte(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rte(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rte(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rte(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble3_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rdouble3_rtn.cl new file mode 100644 index 000000000000..0446792ecdfa --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble3_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtn(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtn(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtn(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtn(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble3_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rdouble3_rtp.cl new file mode 100644 index 000000000000..fb9054a642b9 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble3_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtp(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtp(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtp(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtp(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble3_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rdouble3_rtz.cl new file mode 100644 index 000000000000..640c5194f1d6 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble3_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtz(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtz(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtz(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ConvertUToF_Rdouble3_rtz(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble4.cl b/libclc/test/binding/core/ConvertUToF_Rdouble4.cl new file mode 100644 index 000000000000..6ca80f03d227 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble4.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble4(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble4(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble4(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble4_rte.cl b/libclc/test/binding/core/ConvertUToF_Rdouble4_rte.cl new file mode 100644 index 000000000000..6f3942f2737e --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble4_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rte(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rte(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rte(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rte(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble4_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rdouble4_rtn.cl new file mode 100644 index 000000000000..f04ca25a9159 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble4_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtn(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtn(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtn(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtn(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble4_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rdouble4_rtp.cl new file mode 100644 index 000000000000..a2e56357b373 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble4_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtp(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtp(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtp(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtp(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble4_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rdouble4_rtz.cl new file mode 100644 index 000000000000..bcb3637f3266 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble4_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtz(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtz(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtz(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ConvertUToF_Rdouble4_rtz(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble8.cl b/libclc/test/binding/core/ConvertUToF_Rdouble8.cl new file mode 100644 index 000000000000..46358fb4cecb --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble8.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble8(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble8(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble8(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble8_rte.cl b/libclc/test/binding/core/ConvertUToF_Rdouble8_rte.cl new file mode 100644 index 000000000000..9e4104e27960 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble8_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rte(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rte(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rte(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rte(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble8_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rdouble8_rtn.cl new file mode 100644 index 000000000000..53feff9770c5 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble8_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtn(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtn(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtn(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtn(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble8_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rdouble8_rtp.cl new file mode 100644 index 000000000000..20838b1d2afb --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble8_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtp(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtp(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtp(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtp(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble8_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rdouble8_rtz.cl new file mode 100644 index 000000000000..cfe0ce9ea226 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble8_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtz(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtz(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtz(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ConvertUToF_Rdouble8_rtz(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble_rte.cl b/libclc/test/binding/core/ConvertUToF_Rdouble_rte.cl new file mode 100644 index 000000000000..e6b81bd20817 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rte(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rte(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rte(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble_rte(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rte(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rdouble_rtn.cl new file mode 100644 index 000000000000..fd69abcfeece --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtn(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtn(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtn(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtn(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rdouble_rtp.cl new file mode 100644 index 000000000000..18815efb3826 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtp(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtp(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtp(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtp(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rdouble_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rdouble_rtz.cl new file mode 100644 index 000000000000..678615fdeccd --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rdouble_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtz(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtz(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtz(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ConvertUToF_Rdouble_rtz(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rdouble_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat.cl b/libclc/test/binding/core/ConvertUToF_Rfloat.cl new file mode 100644 index 000000000000..6e3238b7ac07 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat16.cl b/libclc/test/binding/core/ConvertUToF_Rfloat16.cl new file mode 100644 index 000000000000..e0109c980527 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat16(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat16_rte.cl b/libclc/test/binding/core/ConvertUToF_Rfloat16_rte.cl new file mode 100644 index 000000000000..f12e35344998 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat16_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rte(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rte(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rte(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rte(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat16_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rfloat16_rtn.cl new file mode 100644 index 000000000000..c7e75d14d983 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat16_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtn(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtn(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtn(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtn(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat16_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rfloat16_rtp.cl new file mode 100644 index 000000000000..47c219a9709a --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat16_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtp(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtp(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtp(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtp(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat16_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rfloat16_rtz.cl new file mode 100644 index 000000000000..631f66763535 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat16_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtz(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtz(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtz(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ConvertUToF_Rfloat16_rtz(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat16_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat2.cl b/libclc/test/binding/core/ConvertUToF_Rfloat2.cl new file mode 100644 index 000000000000..835451694751 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat2(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat2_rte.cl b/libclc/test/binding/core/ConvertUToF_Rfloat2_rte.cl new file mode 100644 index 000000000000..a3e8ce605480 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat2_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rte(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rte(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rte(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rte(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat2_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rfloat2_rtn.cl new file mode 100644 index 000000000000..9514f275e0e9 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat2_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtn(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtn(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtn(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtn(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat2_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rfloat2_rtp.cl new file mode 100644 index 000000000000..87cac51d90cf --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat2_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtp(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtp(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtp(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtp(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat2_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rfloat2_rtz.cl new file mode 100644 index 000000000000..a7b1d50eb341 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat2_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtz(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtz(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtz(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ConvertUToF_Rfloat2_rtz(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat2_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat3.cl b/libclc/test/binding/core/ConvertUToF_Rfloat3.cl new file mode 100644 index 000000000000..17923bef561a --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat3(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat3_rte.cl b/libclc/test/binding/core/ConvertUToF_Rfloat3_rte.cl new file mode 100644 index 000000000000..e6469296e677 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat3_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rte(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rte(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rte(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rte(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat3_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rfloat3_rtn.cl new file mode 100644 index 000000000000..ddf8cdb03c3a --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat3_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtn(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtn(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtn(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtn(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat3_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rfloat3_rtp.cl new file mode 100644 index 000000000000..b53837c75045 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat3_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtp(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtp(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtp(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtp(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat3_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rfloat3_rtz.cl new file mode 100644 index 000000000000..0ae9e1d5a2c1 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat3_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtz(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtz(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtz(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ConvertUToF_Rfloat3_rtz(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat3_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat4.cl b/libclc/test/binding/core/ConvertUToF_Rfloat4.cl new file mode 100644 index 000000000000..208959ea7d7f --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat4(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat4_rte.cl b/libclc/test/binding/core/ConvertUToF_Rfloat4_rte.cl new file mode 100644 index 000000000000..9e89564f30d0 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat4_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rte(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rte(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rte(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rte(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat4_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rfloat4_rtn.cl new file mode 100644 index 000000000000..dc4edd1a3f41 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat4_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtn(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtn(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtn(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtn(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat4_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rfloat4_rtp.cl new file mode 100644 index 000000000000..9fff5cf92b06 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat4_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtp(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtp(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtp(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtp(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat4_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rfloat4_rtz.cl new file mode 100644 index 000000000000..15f659c223db --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat4_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtz(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtz(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtz(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ConvertUToF_Rfloat4_rtz(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat4_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat8.cl b/libclc/test/binding/core/ConvertUToF_Rfloat8.cl new file mode 100644 index 000000000000..3cce7b72b8b0 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat8(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat8_rte.cl b/libclc/test/binding/core/ConvertUToF_Rfloat8_rte.cl new file mode 100644 index 000000000000..bcb9edbc174c --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat8_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rte(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rte(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rte(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rte(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rte(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat8_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rfloat8_rtn.cl new file mode 100644 index 000000000000..e31745329dbb --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat8_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtn(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtn(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtn(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtn(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtn(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat8_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rfloat8_rtp.cl new file mode 100644 index 000000000000..3908974f8d5b --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat8_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtp(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtp(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtp(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtp(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtp(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat8_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rfloat8_rtz.cl new file mode 100644 index 000000000000..bed3bc02a77d --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat8_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtz(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtz(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtz(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ConvertUToF_Rfloat8_rtz(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat8_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat_rte.cl b/libclc/test/binding/core/ConvertUToF_Rfloat_rte.cl new file mode 100644 index 000000000000..852a0c2c5d6a --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat_rte.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rte(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat_rte(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rte(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat_rte(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rte(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat_rte(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rte(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat_rte(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rfloat_rtn.cl new file mode 100644 index 000000000000..9a99244e4b05 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat_rtn.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtn(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtn(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtn(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtn(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtn(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtn(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtn(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtn(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rfloat_rtp.cl new file mode 100644 index 000000000000..1dc3b6a36e37 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat_rtp.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtp(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtp(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtp(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtp(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtp(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtp(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtp(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtp(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rfloat_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rfloat_rtz.cl new file mode 100644 index 000000000000..e12c7aa847c8 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rfloat_rtz.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtz(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtz(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtz(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtz(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtz(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtz(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ConvertUToF_Rfloat_rtz(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rfloat_rtz(args_0); +} diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf.cl b/libclc/test/binding/core/ConvertUToF_Rhalf.cl new file mode 100644 index 000000000000..5d3a03b3a30a --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf16.cl b/libclc/test/binding/core/ConvertUToF_Rhalf16.cl new file mode 100644 index 000000000000..58527b8a8213 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf16.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf16_rte.cl b/libclc/test/binding/core/ConvertUToF_Rhalf16_rte.cl new file mode 100644 index 000000000000..76231d507015 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf16_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rte(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rte(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rte(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rte(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf16_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rhalf16_rtn.cl new file mode 100644 index 000000000000..745873d38e8d --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf16_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtn(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtn(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtn(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtn(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf16_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rhalf16_rtp.cl new file mode 100644 index 000000000000..ef660f8a454c --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf16_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtp(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtp(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtp(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtp(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf16_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rhalf16_rtz.cl new file mode 100644 index 000000000000..fbba79830e8b --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf16_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtz(__clc_vec16_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtz(__clc_vec16_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtz(__clc_vec16_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ConvertUToF_Rhalf16_rtz(__clc_vec16_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf2.cl b/libclc/test/binding/core/ConvertUToF_Rhalf2.cl new file mode 100644 index 000000000000..462da9bde51f --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf2.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf2_rte.cl b/libclc/test/binding/core/ConvertUToF_Rhalf2_rte.cl new file mode 100644 index 000000000000..7e62fc19711b --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf2_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rte(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rte(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rte(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rte(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf2_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rhalf2_rtn.cl new file mode 100644 index 000000000000..89532c02fb93 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf2_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtn(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtn(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtn(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtn(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf2_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rhalf2_rtp.cl new file mode 100644 index 000000000000..267e81ef8b8a --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf2_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtp(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtp(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtp(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtp(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf2_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rhalf2_rtz.cl new file mode 100644 index 000000000000..d64838fe8404 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf2_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtz(__clc_vec2_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtz(__clc_vec2_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtz(__clc_vec2_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ConvertUToF_Rhalf2_rtz(__clc_vec2_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf3.cl b/libclc/test/binding/core/ConvertUToF_Rhalf3.cl new file mode 100644 index 000000000000..721fd36bdcd9 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf3.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf3_rte.cl b/libclc/test/binding/core/ConvertUToF_Rhalf3_rte.cl new file mode 100644 index 000000000000..177bd59fe79b --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf3_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rte(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rte(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rte(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rte(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf3_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rhalf3_rtn.cl new file mode 100644 index 000000000000..c8cfddf9e3ce --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf3_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtn(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtn(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtn(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtn(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf3_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rhalf3_rtp.cl new file mode 100644 index 000000000000..d963e0780cc7 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf3_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtp(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtp(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtp(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtp(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf3_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rhalf3_rtz.cl new file mode 100644 index 000000000000..8ee93817765d --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf3_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtz(__clc_vec3_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtz(__clc_vec3_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtz(__clc_vec3_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ConvertUToF_Rhalf3_rtz(__clc_vec3_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf4.cl b/libclc/test/binding/core/ConvertUToF_Rhalf4.cl new file mode 100644 index 000000000000..4feaecc2a63e --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf4.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf4_rte.cl b/libclc/test/binding/core/ConvertUToF_Rhalf4_rte.cl new file mode 100644 index 000000000000..a225a3022be3 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf4_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rte(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rte(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rte(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rte(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf4_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rhalf4_rtn.cl new file mode 100644 index 000000000000..4b577b7531f8 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf4_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtn(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtn(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtn(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtn(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf4_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rhalf4_rtp.cl new file mode 100644 index 000000000000..bbe1b2989048 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf4_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtp(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtp(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtp(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtp(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf4_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rhalf4_rtz.cl new file mode 100644 index 000000000000..1ac75d25aad8 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf4_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtz(__clc_vec4_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtz(__clc_vec4_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtz(__clc_vec4_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ConvertUToF_Rhalf4_rtz(__clc_vec4_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf8.cl b/libclc/test/binding/core/ConvertUToF_Rhalf8.cl new file mode 100644 index 000000000000..ddaf6f7245da --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf8.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf8_rte.cl b/libclc/test/binding/core/ConvertUToF_Rhalf8_rte.cl new file mode 100644 index 000000000000..97ef753d3009 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf8_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rte(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rte(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rte(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rte(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf8_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rhalf8_rtn.cl new file mode 100644 index 000000000000..6488c82f2bce --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf8_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtn(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtn(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtn(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtn(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf8_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rhalf8_rtp.cl new file mode 100644 index 000000000000..705c30312d7d --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf8_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtp(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtp(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtp(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtp(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf8_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rhalf8_rtz.cl new file mode 100644 index 000000000000..565f090230f4 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf8_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtz(__clc_vec8_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtz(__clc_vec8_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtz(__clc_vec8_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ConvertUToF_Rhalf8_rtz(__clc_vec8_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf_rte.cl b/libclc/test/binding/core/ConvertUToF_Rhalf_rte.cl new file mode 100644 index 000000000000..b0b1eba48a32 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf_rte.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rte(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rte(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rte(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rte(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf_rtn.cl b/libclc/test/binding/core/ConvertUToF_Rhalf_rtn.cl new file mode 100644 index 000000000000..75ac77a8ce04 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf_rtn.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtn(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtn(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtn(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtn(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf_rtp.cl b/libclc/test/binding/core/ConvertUToF_Rhalf_rtp.cl new file mode 100644 index 000000000000..8b5432f7dc05 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf_rtp.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtp(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtp(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtp(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtp(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/ConvertUToF_Rhalf_rtz.cl b/libclc/test/binding/core/ConvertUToF_Rhalf_rtz.cl new file mode 100644 index 000000000000..f2d9c86f00b1 --- /dev/null +++ b/libclc/test/binding/core/ConvertUToF_Rhalf_rtz.cl @@ -0,0 +1,45 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtz(__clc_uint8_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtz(__clc_uint16_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtz(__clc_uint32_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ConvertUToF_Rhalf_rtz(__clc_uint64_t args_0) { + return __spirv_ConvertUToF_Rhalf_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble.cl b/libclc/test/binding/core/FConvert_Rdouble.cl new file mode 100644 index 000000000000..4b1b0d0a3951 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble(__clc_fp32_t args_0) { + return __spirv_FConvert_Rdouble(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble(__clc_fp16_t args_0) { + return __spirv_FConvert_Rdouble(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble16.cl b/libclc/test/binding/core/FConvert_Rdouble16.cl new file mode 100644 index 000000000000..55776b9940a6 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble16.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rdouble16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rdouble16(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble16_rte.cl b/libclc/test/binding/core/FConvert_Rdouble16_rte.cl new file mode 100644 index 000000000000..935399ec155b --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble16_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rdouble16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rdouble16_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble16_rtn.cl b/libclc/test/binding/core/FConvert_Rdouble16_rtn.cl new file mode 100644 index 000000000000..c7c6cba5e7e2 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble16_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rdouble16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rdouble16_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble16_rtp.cl b/libclc/test/binding/core/FConvert_Rdouble16_rtp.cl new file mode 100644 index 000000000000..4ef6ec7ad66e --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble16_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rdouble16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rdouble16_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble16_rtz.cl b/libclc/test/binding/core/FConvert_Rdouble16_rtz.cl new file mode 100644 index 000000000000..c17379753a2a --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble16_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rdouble16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_FConvert_Rdouble16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rdouble16_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble2.cl b/libclc/test/binding/core/FConvert_Rdouble2.cl new file mode 100644 index 000000000000..54a5560e0044 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble2.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rdouble2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rdouble2(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble2_rte.cl b/libclc/test/binding/core/FConvert_Rdouble2_rte.cl new file mode 100644 index 000000000000..1ad777e235a1 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble2_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rdouble2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rdouble2_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble2_rtn.cl b/libclc/test/binding/core/FConvert_Rdouble2_rtn.cl new file mode 100644 index 000000000000..c09f22726575 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble2_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rdouble2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rdouble2_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble2_rtp.cl b/libclc/test/binding/core/FConvert_Rdouble2_rtp.cl new file mode 100644 index 000000000000..621ff7498b2e --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble2_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rdouble2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rdouble2_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble2_rtz.cl b/libclc/test/binding/core/FConvert_Rdouble2_rtz.cl new file mode 100644 index 000000000000..db807cfcfa7c --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble2_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rdouble2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_FConvert_Rdouble2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rdouble2_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble3.cl b/libclc/test/binding/core/FConvert_Rdouble3.cl new file mode 100644 index 000000000000..b6d6854b9616 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble3.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rdouble3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rdouble3(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble3_rte.cl b/libclc/test/binding/core/FConvert_Rdouble3_rte.cl new file mode 100644 index 000000000000..af59922a762f --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble3_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rdouble3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rdouble3_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble3_rtn.cl b/libclc/test/binding/core/FConvert_Rdouble3_rtn.cl new file mode 100644 index 000000000000..0cbfd6aa7465 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble3_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rdouble3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rdouble3_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble3_rtp.cl b/libclc/test/binding/core/FConvert_Rdouble3_rtp.cl new file mode 100644 index 000000000000..899db46e98e6 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble3_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rdouble3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rdouble3_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble3_rtz.cl b/libclc/test/binding/core/FConvert_Rdouble3_rtz.cl new file mode 100644 index 000000000000..be4e65a05402 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble3_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rdouble3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_FConvert_Rdouble3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rdouble3_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble4.cl b/libclc/test/binding/core/FConvert_Rdouble4.cl new file mode 100644 index 000000000000..4b872503c266 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble4.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rdouble4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rdouble4(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble4_rte.cl b/libclc/test/binding/core/FConvert_Rdouble4_rte.cl new file mode 100644 index 000000000000..1f8610b3df6b --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble4_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rdouble4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rdouble4_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble4_rtn.cl b/libclc/test/binding/core/FConvert_Rdouble4_rtn.cl new file mode 100644 index 000000000000..61f8b2688c72 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble4_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rdouble4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rdouble4_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble4_rtp.cl b/libclc/test/binding/core/FConvert_Rdouble4_rtp.cl new file mode 100644 index 000000000000..dc6c20d8d524 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble4_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rdouble4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rdouble4_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble4_rtz.cl b/libclc/test/binding/core/FConvert_Rdouble4_rtz.cl new file mode 100644 index 000000000000..96a4d98478d9 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble4_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rdouble4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_FConvert_Rdouble4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rdouble4_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble8.cl b/libclc/test/binding/core/FConvert_Rdouble8.cl new file mode 100644 index 000000000000..afce9ceac02f --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble8.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rdouble8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rdouble8(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble8_rte.cl b/libclc/test/binding/core/FConvert_Rdouble8_rte.cl new file mode 100644 index 000000000000..0aa406706ad5 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble8_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rdouble8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rdouble8_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble8_rtn.cl b/libclc/test/binding/core/FConvert_Rdouble8_rtn.cl new file mode 100644 index 000000000000..8733e0c76fc8 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble8_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rdouble8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rdouble8_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble8_rtp.cl b/libclc/test/binding/core/FConvert_Rdouble8_rtp.cl new file mode 100644 index 000000000000..416812fc7a76 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble8_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rdouble8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rdouble8_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble8_rtz.cl b/libclc/test/binding/core/FConvert_Rdouble8_rtz.cl new file mode 100644 index 000000000000..fbcb8abdb6c2 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble8_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rdouble8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_FConvert_Rdouble8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rdouble8_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble_rte.cl b/libclc/test/binding/core/FConvert_Rdouble_rte.cl new file mode 100644 index 000000000000..d85f51ef2d22 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble_rte(__clc_fp32_t args_0) { + return __spirv_FConvert_Rdouble_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble_rte(__clc_fp16_t args_0) { + return __spirv_FConvert_Rdouble_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble_rtn.cl b/libclc/test/binding/core/FConvert_Rdouble_rtn.cl new file mode 100644 index 000000000000..731254748387 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble_rtn(__clc_fp32_t args_0) { + return __spirv_FConvert_Rdouble_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble_rtn(__clc_fp16_t args_0) { + return __spirv_FConvert_Rdouble_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble_rtp.cl b/libclc/test/binding/core/FConvert_Rdouble_rtp.cl new file mode 100644 index 000000000000..a33b0ab94e86 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble_rtp(__clc_fp32_t args_0) { + return __spirv_FConvert_Rdouble_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble_rtp(__clc_fp16_t args_0) { + return __spirv_FConvert_Rdouble_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rdouble_rtz.cl b/libclc/test/binding/core/FConvert_Rdouble_rtz.cl new file mode 100644 index 000000000000..dc40a097276e --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rdouble_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble_rtz(__clc_fp32_t args_0) { + return __spirv_FConvert_Rdouble_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_FConvert_Rdouble_rtz(__clc_fp16_t args_0) { + return __spirv_FConvert_Rdouble_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat.cl b/libclc/test/binding/core/FConvert_Rfloat.cl new file mode 100644 index 000000000000..c08c1ad77b5c --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat(__clc_fp64_t args_0) { + return __spirv_FConvert_Rfloat(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat(__clc_fp16_t args_0) { + return __spirv_FConvert_Rfloat(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat16.cl b/libclc/test/binding/core/FConvert_Rfloat16.cl new file mode 100644 index 000000000000..59b5831e52c6 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat16.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rfloat16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rfloat16(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat16_rte.cl b/libclc/test/binding/core/FConvert_Rfloat16_rte.cl new file mode 100644 index 000000000000..e5faec983505 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat16_rte.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rfloat16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16_rte(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rfloat16_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat16_rtn.cl b/libclc/test/binding/core/FConvert_Rfloat16_rtn.cl new file mode 100644 index 000000000000..d857983fa5de --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat16_rtn.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rfloat16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16_rtn(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rfloat16_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat16_rtp.cl b/libclc/test/binding/core/FConvert_Rfloat16_rtp.cl new file mode 100644 index 000000000000..d9cc3bee9fdc --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat16_rtp.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rfloat16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16_rtp(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rfloat16_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat16_rtz.cl b/libclc/test/binding/core/FConvert_Rfloat16_rtz.cl new file mode 100644 index 000000000000..bde3ff43113e --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat16_rtz.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rfloat16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_FConvert_Rfloat16_rtz(__clc_vec16_fp16_t args_0) { + return __spirv_FConvert_Rfloat16_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat2.cl b/libclc/test/binding/core/FConvert_Rfloat2.cl new file mode 100644 index 000000000000..f010a2e9cea3 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat2.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rfloat2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rfloat2(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat2_rte.cl b/libclc/test/binding/core/FConvert_Rfloat2_rte.cl new file mode 100644 index 000000000000..2a9046976fa1 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat2_rte.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rfloat2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2_rte(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rfloat2_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat2_rtn.cl b/libclc/test/binding/core/FConvert_Rfloat2_rtn.cl new file mode 100644 index 000000000000..6a1217e7a8f9 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat2_rtn.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rfloat2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2_rtn(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rfloat2_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat2_rtp.cl b/libclc/test/binding/core/FConvert_Rfloat2_rtp.cl new file mode 100644 index 000000000000..5218d4074225 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat2_rtp.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rfloat2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2_rtp(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rfloat2_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat2_rtz.cl b/libclc/test/binding/core/FConvert_Rfloat2_rtz.cl new file mode 100644 index 000000000000..6550956d6d10 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat2_rtz.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rfloat2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_FConvert_Rfloat2_rtz(__clc_vec2_fp16_t args_0) { + return __spirv_FConvert_Rfloat2_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat3.cl b/libclc/test/binding/core/FConvert_Rfloat3.cl new file mode 100644 index 000000000000..957dbe929ac8 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat3.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rfloat3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rfloat3(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat3_rte.cl b/libclc/test/binding/core/FConvert_Rfloat3_rte.cl new file mode 100644 index 000000000000..e238ee37ae8b --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat3_rte.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rfloat3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3_rte(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rfloat3_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat3_rtn.cl b/libclc/test/binding/core/FConvert_Rfloat3_rtn.cl new file mode 100644 index 000000000000..e0e6cd8fdbc9 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat3_rtn.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rfloat3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3_rtn(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rfloat3_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat3_rtp.cl b/libclc/test/binding/core/FConvert_Rfloat3_rtp.cl new file mode 100644 index 000000000000..668fe83ed8df --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat3_rtp.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rfloat3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3_rtp(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rfloat3_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat3_rtz.cl b/libclc/test/binding/core/FConvert_Rfloat3_rtz.cl new file mode 100644 index 000000000000..de657516c3ca --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat3_rtz.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rfloat3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_FConvert_Rfloat3_rtz(__clc_vec3_fp16_t args_0) { + return __spirv_FConvert_Rfloat3_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat4.cl b/libclc/test/binding/core/FConvert_Rfloat4.cl new file mode 100644 index 000000000000..12d484fe9c1e --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat4.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rfloat4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rfloat4(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat4_rte.cl b/libclc/test/binding/core/FConvert_Rfloat4_rte.cl new file mode 100644 index 000000000000..088400a1856b --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat4_rte.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rfloat4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4_rte(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rfloat4_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat4_rtn.cl b/libclc/test/binding/core/FConvert_Rfloat4_rtn.cl new file mode 100644 index 000000000000..a7752ae7c08d --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat4_rtn.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rfloat4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4_rtn(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rfloat4_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat4_rtp.cl b/libclc/test/binding/core/FConvert_Rfloat4_rtp.cl new file mode 100644 index 000000000000..e093abe533e1 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat4_rtp.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rfloat4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4_rtp(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rfloat4_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat4_rtz.cl b/libclc/test/binding/core/FConvert_Rfloat4_rtz.cl new file mode 100644 index 000000000000..1d36ef0c35e1 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat4_rtz.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rfloat4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_FConvert_Rfloat4_rtz(__clc_vec4_fp16_t args_0) { + return __spirv_FConvert_Rfloat4_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat8.cl b/libclc/test/binding/core/FConvert_Rfloat8.cl new file mode 100644 index 000000000000..4b569ca09d8b --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat8.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rfloat8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rfloat8(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat8_rte.cl b/libclc/test/binding/core/FConvert_Rfloat8_rte.cl new file mode 100644 index 000000000000..972b4a620c7c --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat8_rte.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rfloat8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8_rte(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rfloat8_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat8_rtn.cl b/libclc/test/binding/core/FConvert_Rfloat8_rtn.cl new file mode 100644 index 000000000000..6f522c7fa585 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat8_rtn.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rfloat8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8_rtn(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rfloat8_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat8_rtp.cl b/libclc/test/binding/core/FConvert_Rfloat8_rtp.cl new file mode 100644 index 000000000000..0a3bd8769acc --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat8_rtp.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rfloat8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8_rtp(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rfloat8_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat8_rtz.cl b/libclc/test/binding/core/FConvert_Rfloat8_rtz.cl new file mode 100644 index 000000000000..54662cc8f1ba --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat8_rtz.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rfloat8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_FConvert_Rfloat8_rtz(__clc_vec8_fp16_t args_0) { + return __spirv_FConvert_Rfloat8_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat_rte.cl b/libclc/test/binding/core/FConvert_Rfloat_rte.cl new file mode 100644 index 000000000000..6712c64910ff --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat_rte.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat_rte(__clc_fp64_t args_0) { + return __spirv_FConvert_Rfloat_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat_rte(__clc_fp16_t args_0) { + return __spirv_FConvert_Rfloat_rte(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat_rtn.cl b/libclc/test/binding/core/FConvert_Rfloat_rtn.cl new file mode 100644 index 000000000000..4025306f2deb --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat_rtn.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat_rtn(__clc_fp64_t args_0) { + return __spirv_FConvert_Rfloat_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat_rtn(__clc_fp16_t args_0) { + return __spirv_FConvert_Rfloat_rtn(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat_rtp.cl b/libclc/test/binding/core/FConvert_Rfloat_rtp.cl new file mode 100644 index 000000000000..90887196809e --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat_rtp.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat_rtp(__clc_fp64_t args_0) { + return __spirv_FConvert_Rfloat_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat_rtp(__clc_fp16_t args_0) { + return __spirv_FConvert_Rfloat_rtp(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rfloat_rtz.cl b/libclc/test/binding/core/FConvert_Rfloat_rtz.cl new file mode 100644 index 000000000000..bbbad15baf81 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rfloat_rtz.cl @@ -0,0 +1,31 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat_rtz(__clc_fp64_t args_0) { + return __spirv_FConvert_Rfloat_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_FConvert_Rfloat_rtz(__clc_fp16_t args_0) { + return __spirv_FConvert_Rfloat_rtz(args_0); +} + +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf.cl b/libclc/test/binding/core/FConvert_Rhalf.cl new file mode 100644 index 000000000000..6822a0de461b --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf(__clc_fp32_t args_0) { + return __spirv_FConvert_Rhalf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf(__clc_fp64_t args_0) { + return __spirv_FConvert_Rhalf(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf16.cl b/libclc/test/binding/core/FConvert_Rhalf16.cl new file mode 100644 index 000000000000..643d751cd66c --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf16.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rhalf16(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rhalf16(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf16_rte.cl b/libclc/test/binding/core/FConvert_Rhalf16_rte.cl new file mode 100644 index 000000000000..66d155d65b37 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf16_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16_rte(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rhalf16_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16_rte(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rhalf16_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf16_rtn.cl b/libclc/test/binding/core/FConvert_Rhalf16_rtn.cl new file mode 100644 index 000000000000..7a51629d9f11 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf16_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16_rtn(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rhalf16_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16_rtn(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rhalf16_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf16_rtp.cl b/libclc/test/binding/core/FConvert_Rhalf16_rtp.cl new file mode 100644 index 000000000000..66c85cd0d90b --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf16_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16_rtp(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rhalf16_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16_rtp(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rhalf16_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf16_rtz.cl b/libclc/test/binding/core/FConvert_Rhalf16_rtz.cl new file mode 100644 index 000000000000..79afb5a388e1 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf16_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16_rtz(__clc_vec16_fp32_t args_0) { + return __spirv_FConvert_Rhalf16_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_FConvert_Rhalf16_rtz(__clc_vec16_fp64_t args_0) { + return __spirv_FConvert_Rhalf16_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf2.cl b/libclc/test/binding/core/FConvert_Rhalf2.cl new file mode 100644 index 000000000000..c9c8f91ee438 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf2.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rhalf2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rhalf2(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf2_rte.cl b/libclc/test/binding/core/FConvert_Rhalf2_rte.cl new file mode 100644 index 000000000000..b28d385bf89a --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf2_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2_rte(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rhalf2_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2_rte(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rhalf2_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf2_rtn.cl b/libclc/test/binding/core/FConvert_Rhalf2_rtn.cl new file mode 100644 index 000000000000..7c6d7aa722ae --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf2_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2_rtn(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rhalf2_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2_rtn(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rhalf2_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf2_rtp.cl b/libclc/test/binding/core/FConvert_Rhalf2_rtp.cl new file mode 100644 index 000000000000..f7603776d8b2 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf2_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2_rtp(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rhalf2_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2_rtp(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rhalf2_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf2_rtz.cl b/libclc/test/binding/core/FConvert_Rhalf2_rtz.cl new file mode 100644 index 000000000000..62fbeb448d52 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf2_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2_rtz(__clc_vec2_fp32_t args_0) { + return __spirv_FConvert_Rhalf2_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_FConvert_Rhalf2_rtz(__clc_vec2_fp64_t args_0) { + return __spirv_FConvert_Rhalf2_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf3.cl b/libclc/test/binding/core/FConvert_Rhalf3.cl new file mode 100644 index 000000000000..cb4b573e8c61 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf3.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rhalf3(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rhalf3(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf3_rte.cl b/libclc/test/binding/core/FConvert_Rhalf3_rte.cl new file mode 100644 index 000000000000..9209b7d0adb8 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf3_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3_rte(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rhalf3_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3_rte(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rhalf3_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf3_rtn.cl b/libclc/test/binding/core/FConvert_Rhalf3_rtn.cl new file mode 100644 index 000000000000..ef70aaa67122 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf3_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3_rtn(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rhalf3_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3_rtn(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rhalf3_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf3_rtp.cl b/libclc/test/binding/core/FConvert_Rhalf3_rtp.cl new file mode 100644 index 000000000000..a8a5e880ce93 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf3_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3_rtp(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rhalf3_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3_rtp(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rhalf3_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf3_rtz.cl b/libclc/test/binding/core/FConvert_Rhalf3_rtz.cl new file mode 100644 index 000000000000..2c8b861686fb --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf3_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3_rtz(__clc_vec3_fp32_t args_0) { + return __spirv_FConvert_Rhalf3_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_FConvert_Rhalf3_rtz(__clc_vec3_fp64_t args_0) { + return __spirv_FConvert_Rhalf3_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf4.cl b/libclc/test/binding/core/FConvert_Rhalf4.cl new file mode 100644 index 000000000000..3b66d54cf547 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf4.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rhalf4(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rhalf4(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf4_rte.cl b/libclc/test/binding/core/FConvert_Rhalf4_rte.cl new file mode 100644 index 000000000000..725836ff5e8a --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf4_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4_rte(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rhalf4_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4_rte(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rhalf4_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf4_rtn.cl b/libclc/test/binding/core/FConvert_Rhalf4_rtn.cl new file mode 100644 index 000000000000..9b185bf2260c --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf4_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4_rtn(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rhalf4_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4_rtn(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rhalf4_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf4_rtp.cl b/libclc/test/binding/core/FConvert_Rhalf4_rtp.cl new file mode 100644 index 000000000000..a5bca48bd1b0 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf4_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4_rtp(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rhalf4_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4_rtp(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rhalf4_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf4_rtz.cl b/libclc/test/binding/core/FConvert_Rhalf4_rtz.cl new file mode 100644 index 000000000000..97dcc5ef37b7 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf4_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4_rtz(__clc_vec4_fp32_t args_0) { + return __spirv_FConvert_Rhalf4_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_FConvert_Rhalf4_rtz(__clc_vec4_fp64_t args_0) { + return __spirv_FConvert_Rhalf4_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf8.cl b/libclc/test/binding/core/FConvert_Rhalf8.cl new file mode 100644 index 000000000000..09d7bcdfca68 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf8.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rhalf8(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rhalf8(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf8_rte.cl b/libclc/test/binding/core/FConvert_Rhalf8_rte.cl new file mode 100644 index 000000000000..fde0d004bb5d --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf8_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8_rte(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rhalf8_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8_rte(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rhalf8_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf8_rtn.cl b/libclc/test/binding/core/FConvert_Rhalf8_rtn.cl new file mode 100644 index 000000000000..ee9dd7b1ba9c --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf8_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8_rtn(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rhalf8_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8_rtn(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rhalf8_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf8_rtp.cl b/libclc/test/binding/core/FConvert_Rhalf8_rtp.cl new file mode 100644 index 000000000000..e5e1ce57bb96 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf8_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8_rtp(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rhalf8_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8_rtp(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rhalf8_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf8_rtz.cl b/libclc/test/binding/core/FConvert_Rhalf8_rtz.cl new file mode 100644 index 000000000000..9e02f57095f5 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf8_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8_rtz(__clc_vec8_fp32_t args_0) { + return __spirv_FConvert_Rhalf8_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_FConvert_Rhalf8_rtz(__clc_vec8_fp64_t args_0) { + return __spirv_FConvert_Rhalf8_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf_rte.cl b/libclc/test/binding/core/FConvert_Rhalf_rte.cl new file mode 100644 index 000000000000..adfaecd89a3b --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf_rte.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf_rte(__clc_fp32_t args_0) { + return __spirv_FConvert_Rhalf_rte(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf_rte(__clc_fp64_t args_0) { + return __spirv_FConvert_Rhalf_rte(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf_rtn.cl b/libclc/test/binding/core/FConvert_Rhalf_rtn.cl new file mode 100644 index 000000000000..ce30a3058916 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf_rtn.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf_rtn(__clc_fp32_t args_0) { + return __spirv_FConvert_Rhalf_rtn(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf_rtn(__clc_fp64_t args_0) { + return __spirv_FConvert_Rhalf_rtn(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf_rtp.cl b/libclc/test/binding/core/FConvert_Rhalf_rtp.cl new file mode 100644 index 000000000000..8d72c7558eb1 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf_rtp.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf_rtp(__clc_fp32_t args_0) { + return __spirv_FConvert_Rhalf_rtp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf_rtp(__clc_fp64_t args_0) { + return __spirv_FConvert_Rhalf_rtp(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/FConvert_Rhalf_rtz.cl b/libclc/test/binding/core/FConvert_Rhalf_rtz.cl new file mode 100644 index 000000000000..b0c938694096 --- /dev/null +++ b/libclc/test/binding/core/FConvert_Rhalf_rtz.cl @@ -0,0 +1,33 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf_rtz(__clc_fp32_t args_0) { + return __spirv_FConvert_Rhalf_rtz(args_0); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_FConvert_Rhalf_rtz(__clc_fp64_t args_0) { + return __spirv_FConvert_Rhalf_rtz(args_0); +} + +#endif +#endif diff --git a/libclc/test/binding/core/SConvert_Rchar.cl b/libclc/test/binding/core/SConvert_Rchar.cl new file mode 100644 index 000000000000..3be4929dabe9 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar(__clc_int16_t args_0) { + return __spirv_SConvert_Rchar(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar(__clc_uint16_t args_0) { + return __spirv_SConvert_Rchar(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar(__clc_int32_t args_0) { + return __spirv_SConvert_Rchar(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar(__clc_uint32_t args_0) { + return __spirv_SConvert_Rchar(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar(__clc_int64_t args_0) { + return __spirv_SConvert_Rchar(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar(__clc_uint64_t args_0) { + return __spirv_SConvert_Rchar(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar16.cl b/libclc/test/binding/core/SConvert_Rchar16.cl new file mode 100644 index 000000000000..7b2c8986b5d0 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar16.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16(__clc_vec16_int16_t args_0) { + return __spirv_SConvert_Rchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16(__clc_vec16_uint16_t args_0) { + return __spirv_SConvert_Rchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16(__clc_vec16_int32_t args_0) { + return __spirv_SConvert_Rchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16(__clc_vec16_uint32_t args_0) { + return __spirv_SConvert_Rchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16(__clc_vec16_int64_t args_0) { + return __spirv_SConvert_Rchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16(__clc_vec16_uint64_t args_0) { + return __spirv_SConvert_Rchar16(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar16_sat.cl b/libclc/test/binding/core/SConvert_Rchar16_sat.cl new file mode 100644 index 000000000000..6b6b73944013 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar16_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16_sat(__clc_vec16_int16_t args_0) { + return __spirv_SConvert_Rchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16_sat(__clc_vec16_uint16_t args_0) { + return __spirv_SConvert_Rchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16_sat(__clc_vec16_int32_t args_0) { + return __spirv_SConvert_Rchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16_sat(__clc_vec16_uint32_t args_0) { + return __spirv_SConvert_Rchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16_sat(__clc_vec16_int64_t args_0) { + return __spirv_SConvert_Rchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SConvert_Rchar16_sat(__clc_vec16_uint64_t args_0) { + return __spirv_SConvert_Rchar16_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar2.cl b/libclc/test/binding/core/SConvert_Rchar2.cl new file mode 100644 index 000000000000..05f14817aab6 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2(__clc_vec2_int16_t args_0) { + return __spirv_SConvert_Rchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2(__clc_vec2_uint16_t args_0) { + return __spirv_SConvert_Rchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2(__clc_vec2_int32_t args_0) { + return __spirv_SConvert_Rchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2(__clc_vec2_uint32_t args_0) { + return __spirv_SConvert_Rchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2(__clc_vec2_int64_t args_0) { + return __spirv_SConvert_Rchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2(__clc_vec2_uint64_t args_0) { + return __spirv_SConvert_Rchar2(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar2_sat.cl b/libclc/test/binding/core/SConvert_Rchar2_sat.cl new file mode 100644 index 000000000000..b8f1910870cc --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar2_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2_sat(__clc_vec2_int16_t args_0) { + return __spirv_SConvert_Rchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2_sat(__clc_vec2_uint16_t args_0) { + return __spirv_SConvert_Rchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2_sat(__clc_vec2_int32_t args_0) { + return __spirv_SConvert_Rchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2_sat(__clc_vec2_uint32_t args_0) { + return __spirv_SConvert_Rchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2_sat(__clc_vec2_int64_t args_0) { + return __spirv_SConvert_Rchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SConvert_Rchar2_sat(__clc_vec2_uint64_t args_0) { + return __spirv_SConvert_Rchar2_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar3.cl b/libclc/test/binding/core/SConvert_Rchar3.cl new file mode 100644 index 000000000000..1f2af90f9e71 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar3.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3(__clc_vec3_int16_t args_0) { + return __spirv_SConvert_Rchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3(__clc_vec3_uint16_t args_0) { + return __spirv_SConvert_Rchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3(__clc_vec3_int32_t args_0) { + return __spirv_SConvert_Rchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3(__clc_vec3_uint32_t args_0) { + return __spirv_SConvert_Rchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3(__clc_vec3_int64_t args_0) { + return __spirv_SConvert_Rchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3(__clc_vec3_uint64_t args_0) { + return __spirv_SConvert_Rchar3(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar3_sat.cl b/libclc/test/binding/core/SConvert_Rchar3_sat.cl new file mode 100644 index 000000000000..78d73f570a85 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar3_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3_sat(__clc_vec3_int16_t args_0) { + return __spirv_SConvert_Rchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3_sat(__clc_vec3_uint16_t args_0) { + return __spirv_SConvert_Rchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3_sat(__clc_vec3_int32_t args_0) { + return __spirv_SConvert_Rchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3_sat(__clc_vec3_uint32_t args_0) { + return __spirv_SConvert_Rchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3_sat(__clc_vec3_int64_t args_0) { + return __spirv_SConvert_Rchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SConvert_Rchar3_sat(__clc_vec3_uint64_t args_0) { + return __spirv_SConvert_Rchar3_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar4.cl b/libclc/test/binding/core/SConvert_Rchar4.cl new file mode 100644 index 000000000000..94b379000835 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar4.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4(__clc_vec4_int16_t args_0) { + return __spirv_SConvert_Rchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4(__clc_vec4_uint16_t args_0) { + return __spirv_SConvert_Rchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4(__clc_vec4_int32_t args_0) { + return __spirv_SConvert_Rchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4(__clc_vec4_uint32_t args_0) { + return __spirv_SConvert_Rchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4(__clc_vec4_int64_t args_0) { + return __spirv_SConvert_Rchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4(__clc_vec4_uint64_t args_0) { + return __spirv_SConvert_Rchar4(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar4_sat.cl b/libclc/test/binding/core/SConvert_Rchar4_sat.cl new file mode 100644 index 000000000000..237c1428f9fe --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar4_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4_sat(__clc_vec4_int16_t args_0) { + return __spirv_SConvert_Rchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4_sat(__clc_vec4_uint16_t args_0) { + return __spirv_SConvert_Rchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4_sat(__clc_vec4_int32_t args_0) { + return __spirv_SConvert_Rchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4_sat(__clc_vec4_uint32_t args_0) { + return __spirv_SConvert_Rchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4_sat(__clc_vec4_int64_t args_0) { + return __spirv_SConvert_Rchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SConvert_Rchar4_sat(__clc_vec4_uint64_t args_0) { + return __spirv_SConvert_Rchar4_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar8.cl b/libclc/test/binding/core/SConvert_Rchar8.cl new file mode 100644 index 000000000000..faeb84735e86 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar8.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8(__clc_vec8_int16_t args_0) { + return __spirv_SConvert_Rchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8(__clc_vec8_uint16_t args_0) { + return __spirv_SConvert_Rchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8(__clc_vec8_int32_t args_0) { + return __spirv_SConvert_Rchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8(__clc_vec8_uint32_t args_0) { + return __spirv_SConvert_Rchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8(__clc_vec8_int64_t args_0) { + return __spirv_SConvert_Rchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8(__clc_vec8_uint64_t args_0) { + return __spirv_SConvert_Rchar8(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar8_sat.cl b/libclc/test/binding/core/SConvert_Rchar8_sat.cl new file mode 100644 index 000000000000..651cc1da6b6c --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar8_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8_sat(__clc_vec8_int16_t args_0) { + return __spirv_SConvert_Rchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8_sat(__clc_vec8_uint16_t args_0) { + return __spirv_SConvert_Rchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8_sat(__clc_vec8_int32_t args_0) { + return __spirv_SConvert_Rchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8_sat(__clc_vec8_uint32_t args_0) { + return __spirv_SConvert_Rchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8_sat(__clc_vec8_int64_t args_0) { + return __spirv_SConvert_Rchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SConvert_Rchar8_sat(__clc_vec8_uint64_t args_0) { + return __spirv_SConvert_Rchar8_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rchar_sat.cl b/libclc/test/binding/core/SConvert_Rchar_sat.cl new file mode 100644 index 000000000000..47ca7d93635d --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rchar_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar_sat(__clc_int16_t args_0) { + return __spirv_SConvert_Rchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar_sat(__clc_uint16_t args_0) { + return __spirv_SConvert_Rchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar_sat(__clc_int32_t args_0) { + return __spirv_SConvert_Rchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar_sat(__clc_uint32_t args_0) { + return __spirv_SConvert_Rchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar_sat(__clc_int64_t args_0) { + return __spirv_SConvert_Rchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SConvert_Rchar_sat(__clc_uint64_t args_0) { + return __spirv_SConvert_Rchar_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint.cl b/libclc/test/binding/core/SConvert_Rint.cl new file mode 100644 index 000000000000..859f22840c7c --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint(__clc_int8_t args_0) { + return __spirv_SConvert_Rint(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint(__clc_uint8_t args_0) { + return __spirv_SConvert_Rint(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint(__clc_int16_t args_0) { + return __spirv_SConvert_Rint(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint(__clc_uint16_t args_0) { + return __spirv_SConvert_Rint(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint(__clc_int64_t args_0) { + return __spirv_SConvert_Rint(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint(__clc_uint64_t args_0) { + return __spirv_SConvert_Rint(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint16.cl b/libclc/test/binding/core/SConvert_Rint16.cl new file mode 100644 index 000000000000..a4c88b7ca423 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint16.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16(__clc_vec16_int8_t args_0) { + return __spirv_SConvert_Rint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16(__clc_vec16_uint8_t args_0) { + return __spirv_SConvert_Rint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16(__clc_vec16_int16_t args_0) { + return __spirv_SConvert_Rint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16(__clc_vec16_uint16_t args_0) { + return __spirv_SConvert_Rint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16(__clc_vec16_int64_t args_0) { + return __spirv_SConvert_Rint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16(__clc_vec16_uint64_t args_0) { + return __spirv_SConvert_Rint16(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint16_sat.cl b/libclc/test/binding/core/SConvert_Rint16_sat.cl new file mode 100644 index 000000000000..c104c7236eb7 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint16_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16_sat(__clc_vec16_int8_t args_0) { + return __spirv_SConvert_Rint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16_sat(__clc_vec16_uint8_t args_0) { + return __spirv_SConvert_Rint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16_sat(__clc_vec16_int16_t args_0) { + return __spirv_SConvert_Rint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16_sat(__clc_vec16_uint16_t args_0) { + return __spirv_SConvert_Rint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16_sat(__clc_vec16_int64_t args_0) { + return __spirv_SConvert_Rint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SConvert_Rint16_sat(__clc_vec16_uint64_t args_0) { + return __spirv_SConvert_Rint16_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint2.cl b/libclc/test/binding/core/SConvert_Rint2.cl new file mode 100644 index 000000000000..982d2073c06e --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2(__clc_vec2_int8_t args_0) { + return __spirv_SConvert_Rint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2(__clc_vec2_uint8_t args_0) { + return __spirv_SConvert_Rint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2(__clc_vec2_int16_t args_0) { + return __spirv_SConvert_Rint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2(__clc_vec2_uint16_t args_0) { + return __spirv_SConvert_Rint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2(__clc_vec2_int64_t args_0) { + return __spirv_SConvert_Rint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2(__clc_vec2_uint64_t args_0) { + return __spirv_SConvert_Rint2(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint2_sat.cl b/libclc/test/binding/core/SConvert_Rint2_sat.cl new file mode 100644 index 000000000000..ee4257f1d2c5 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint2_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2_sat(__clc_vec2_int8_t args_0) { + return __spirv_SConvert_Rint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2_sat(__clc_vec2_uint8_t args_0) { + return __spirv_SConvert_Rint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2_sat(__clc_vec2_int16_t args_0) { + return __spirv_SConvert_Rint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2_sat(__clc_vec2_uint16_t args_0) { + return __spirv_SConvert_Rint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2_sat(__clc_vec2_int64_t args_0) { + return __spirv_SConvert_Rint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SConvert_Rint2_sat(__clc_vec2_uint64_t args_0) { + return __spirv_SConvert_Rint2_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint3.cl b/libclc/test/binding/core/SConvert_Rint3.cl new file mode 100644 index 000000000000..8589420ff2b2 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint3.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3(__clc_vec3_int8_t args_0) { + return __spirv_SConvert_Rint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3(__clc_vec3_uint8_t args_0) { + return __spirv_SConvert_Rint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3(__clc_vec3_int16_t args_0) { + return __spirv_SConvert_Rint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3(__clc_vec3_uint16_t args_0) { + return __spirv_SConvert_Rint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3(__clc_vec3_int64_t args_0) { + return __spirv_SConvert_Rint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3(__clc_vec3_uint64_t args_0) { + return __spirv_SConvert_Rint3(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint3_sat.cl b/libclc/test/binding/core/SConvert_Rint3_sat.cl new file mode 100644 index 000000000000..a250b994cfff --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint3_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3_sat(__clc_vec3_int8_t args_0) { + return __spirv_SConvert_Rint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3_sat(__clc_vec3_uint8_t args_0) { + return __spirv_SConvert_Rint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3_sat(__clc_vec3_int16_t args_0) { + return __spirv_SConvert_Rint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3_sat(__clc_vec3_uint16_t args_0) { + return __spirv_SConvert_Rint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3_sat(__clc_vec3_int64_t args_0) { + return __spirv_SConvert_Rint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SConvert_Rint3_sat(__clc_vec3_uint64_t args_0) { + return __spirv_SConvert_Rint3_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint4.cl b/libclc/test/binding/core/SConvert_Rint4.cl new file mode 100644 index 000000000000..05e2ffba1ebf --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint4.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4(__clc_vec4_int8_t args_0) { + return __spirv_SConvert_Rint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4(__clc_vec4_uint8_t args_0) { + return __spirv_SConvert_Rint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4(__clc_vec4_int16_t args_0) { + return __spirv_SConvert_Rint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4(__clc_vec4_uint16_t args_0) { + return __spirv_SConvert_Rint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4(__clc_vec4_int64_t args_0) { + return __spirv_SConvert_Rint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4(__clc_vec4_uint64_t args_0) { + return __spirv_SConvert_Rint4(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint4_sat.cl b/libclc/test/binding/core/SConvert_Rint4_sat.cl new file mode 100644 index 000000000000..5a65d911d9f0 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint4_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4_sat(__clc_vec4_int8_t args_0) { + return __spirv_SConvert_Rint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4_sat(__clc_vec4_uint8_t args_0) { + return __spirv_SConvert_Rint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4_sat(__clc_vec4_int16_t args_0) { + return __spirv_SConvert_Rint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4_sat(__clc_vec4_uint16_t args_0) { + return __spirv_SConvert_Rint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4_sat(__clc_vec4_int64_t args_0) { + return __spirv_SConvert_Rint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SConvert_Rint4_sat(__clc_vec4_uint64_t args_0) { + return __spirv_SConvert_Rint4_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint8.cl b/libclc/test/binding/core/SConvert_Rint8.cl new file mode 100644 index 000000000000..8a173d7ae230 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint8.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8(__clc_vec8_int8_t args_0) { + return __spirv_SConvert_Rint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8(__clc_vec8_uint8_t args_0) { + return __spirv_SConvert_Rint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8(__clc_vec8_int16_t args_0) { + return __spirv_SConvert_Rint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8(__clc_vec8_uint16_t args_0) { + return __spirv_SConvert_Rint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8(__clc_vec8_int64_t args_0) { + return __spirv_SConvert_Rint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8(__clc_vec8_uint64_t args_0) { + return __spirv_SConvert_Rint8(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint8_sat.cl b/libclc/test/binding/core/SConvert_Rint8_sat.cl new file mode 100644 index 000000000000..d2f3c3ee2817 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint8_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8_sat(__clc_vec8_int8_t args_0) { + return __spirv_SConvert_Rint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8_sat(__clc_vec8_uint8_t args_0) { + return __spirv_SConvert_Rint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8_sat(__clc_vec8_int16_t args_0) { + return __spirv_SConvert_Rint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8_sat(__clc_vec8_uint16_t args_0) { + return __spirv_SConvert_Rint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8_sat(__clc_vec8_int64_t args_0) { + return __spirv_SConvert_Rint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SConvert_Rint8_sat(__clc_vec8_uint64_t args_0) { + return __spirv_SConvert_Rint8_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rint_sat.cl b/libclc/test/binding/core/SConvert_Rint_sat.cl new file mode 100644 index 000000000000..8bdb0fc70c34 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rint_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint_sat(__clc_int8_t args_0) { + return __spirv_SConvert_Rint_sat(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint_sat(__clc_uint8_t args_0) { + return __spirv_SConvert_Rint_sat(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint_sat(__clc_int16_t args_0) { + return __spirv_SConvert_Rint_sat(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint_sat(__clc_uint16_t args_0) { + return __spirv_SConvert_Rint_sat(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint_sat(__clc_int64_t args_0) { + return __spirv_SConvert_Rint_sat(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SConvert_Rint_sat(__clc_uint64_t args_0) { + return __spirv_SConvert_Rint_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong.cl b/libclc/test/binding/core/SConvert_Rlong.cl new file mode 100644 index 000000000000..ea3eab871052 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong(__clc_int8_t args_0) { + return __spirv_SConvert_Rlong(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong(__clc_uint8_t args_0) { + return __spirv_SConvert_Rlong(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong(__clc_int16_t args_0) { + return __spirv_SConvert_Rlong(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong(__clc_uint16_t args_0) { + return __spirv_SConvert_Rlong(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong(__clc_int32_t args_0) { + return __spirv_SConvert_Rlong(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong(__clc_uint32_t args_0) { + return __spirv_SConvert_Rlong(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong16.cl b/libclc/test/binding/core/SConvert_Rlong16.cl new file mode 100644 index 000000000000..5d33465e8ff5 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong16.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16(__clc_vec16_int8_t args_0) { + return __spirv_SConvert_Rlong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16(__clc_vec16_uint8_t args_0) { + return __spirv_SConvert_Rlong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16(__clc_vec16_int16_t args_0) { + return __spirv_SConvert_Rlong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16(__clc_vec16_uint16_t args_0) { + return __spirv_SConvert_Rlong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16(__clc_vec16_int32_t args_0) { + return __spirv_SConvert_Rlong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16(__clc_vec16_uint32_t args_0) { + return __spirv_SConvert_Rlong16(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong16_sat.cl b/libclc/test/binding/core/SConvert_Rlong16_sat.cl new file mode 100644 index 000000000000..e20e3cc9f897 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong16_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16_sat(__clc_vec16_int8_t args_0) { + return __spirv_SConvert_Rlong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16_sat(__clc_vec16_uint8_t args_0) { + return __spirv_SConvert_Rlong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16_sat(__clc_vec16_int16_t args_0) { + return __spirv_SConvert_Rlong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16_sat(__clc_vec16_uint16_t args_0) { + return __spirv_SConvert_Rlong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16_sat(__clc_vec16_int32_t args_0) { + return __spirv_SConvert_Rlong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SConvert_Rlong16_sat(__clc_vec16_uint32_t args_0) { + return __spirv_SConvert_Rlong16_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong2.cl b/libclc/test/binding/core/SConvert_Rlong2.cl new file mode 100644 index 000000000000..f05ab251e9c5 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2(__clc_vec2_int8_t args_0) { + return __spirv_SConvert_Rlong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2(__clc_vec2_uint8_t args_0) { + return __spirv_SConvert_Rlong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2(__clc_vec2_int16_t args_0) { + return __spirv_SConvert_Rlong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2(__clc_vec2_uint16_t args_0) { + return __spirv_SConvert_Rlong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2(__clc_vec2_int32_t args_0) { + return __spirv_SConvert_Rlong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2(__clc_vec2_uint32_t args_0) { + return __spirv_SConvert_Rlong2(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong2_sat.cl b/libclc/test/binding/core/SConvert_Rlong2_sat.cl new file mode 100644 index 000000000000..0bcc9b14273a --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong2_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2_sat(__clc_vec2_int8_t args_0) { + return __spirv_SConvert_Rlong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2_sat(__clc_vec2_uint8_t args_0) { + return __spirv_SConvert_Rlong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2_sat(__clc_vec2_int16_t args_0) { + return __spirv_SConvert_Rlong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2_sat(__clc_vec2_uint16_t args_0) { + return __spirv_SConvert_Rlong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2_sat(__clc_vec2_int32_t args_0) { + return __spirv_SConvert_Rlong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SConvert_Rlong2_sat(__clc_vec2_uint32_t args_0) { + return __spirv_SConvert_Rlong2_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong3.cl b/libclc/test/binding/core/SConvert_Rlong3.cl new file mode 100644 index 000000000000..a155b2a05558 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong3.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3(__clc_vec3_int8_t args_0) { + return __spirv_SConvert_Rlong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3(__clc_vec3_uint8_t args_0) { + return __spirv_SConvert_Rlong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3(__clc_vec3_int16_t args_0) { + return __spirv_SConvert_Rlong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3(__clc_vec3_uint16_t args_0) { + return __spirv_SConvert_Rlong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3(__clc_vec3_int32_t args_0) { + return __spirv_SConvert_Rlong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3(__clc_vec3_uint32_t args_0) { + return __spirv_SConvert_Rlong3(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong3_sat.cl b/libclc/test/binding/core/SConvert_Rlong3_sat.cl new file mode 100644 index 000000000000..bc150b77fc54 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong3_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3_sat(__clc_vec3_int8_t args_0) { + return __spirv_SConvert_Rlong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3_sat(__clc_vec3_uint8_t args_0) { + return __spirv_SConvert_Rlong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3_sat(__clc_vec3_int16_t args_0) { + return __spirv_SConvert_Rlong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3_sat(__clc_vec3_uint16_t args_0) { + return __spirv_SConvert_Rlong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3_sat(__clc_vec3_int32_t args_0) { + return __spirv_SConvert_Rlong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SConvert_Rlong3_sat(__clc_vec3_uint32_t args_0) { + return __spirv_SConvert_Rlong3_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong4.cl b/libclc/test/binding/core/SConvert_Rlong4.cl new file mode 100644 index 000000000000..f8e0f0619473 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong4.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4(__clc_vec4_int8_t args_0) { + return __spirv_SConvert_Rlong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4(__clc_vec4_uint8_t args_0) { + return __spirv_SConvert_Rlong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4(__clc_vec4_int16_t args_0) { + return __spirv_SConvert_Rlong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4(__clc_vec4_uint16_t args_0) { + return __spirv_SConvert_Rlong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4(__clc_vec4_int32_t args_0) { + return __spirv_SConvert_Rlong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4(__clc_vec4_uint32_t args_0) { + return __spirv_SConvert_Rlong4(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong4_sat.cl b/libclc/test/binding/core/SConvert_Rlong4_sat.cl new file mode 100644 index 000000000000..24351d3dd33b --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong4_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4_sat(__clc_vec4_int8_t args_0) { + return __spirv_SConvert_Rlong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4_sat(__clc_vec4_uint8_t args_0) { + return __spirv_SConvert_Rlong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4_sat(__clc_vec4_int16_t args_0) { + return __spirv_SConvert_Rlong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4_sat(__clc_vec4_uint16_t args_0) { + return __spirv_SConvert_Rlong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4_sat(__clc_vec4_int32_t args_0) { + return __spirv_SConvert_Rlong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SConvert_Rlong4_sat(__clc_vec4_uint32_t args_0) { + return __spirv_SConvert_Rlong4_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong8.cl b/libclc/test/binding/core/SConvert_Rlong8.cl new file mode 100644 index 000000000000..6328de37c865 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong8.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8(__clc_vec8_int8_t args_0) { + return __spirv_SConvert_Rlong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8(__clc_vec8_uint8_t args_0) { + return __spirv_SConvert_Rlong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8(__clc_vec8_int16_t args_0) { + return __spirv_SConvert_Rlong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8(__clc_vec8_uint16_t args_0) { + return __spirv_SConvert_Rlong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8(__clc_vec8_int32_t args_0) { + return __spirv_SConvert_Rlong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8(__clc_vec8_uint32_t args_0) { + return __spirv_SConvert_Rlong8(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong8_sat.cl b/libclc/test/binding/core/SConvert_Rlong8_sat.cl new file mode 100644 index 000000000000..569d156bd16f --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong8_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8_sat(__clc_vec8_int8_t args_0) { + return __spirv_SConvert_Rlong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8_sat(__clc_vec8_uint8_t args_0) { + return __spirv_SConvert_Rlong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8_sat(__clc_vec8_int16_t args_0) { + return __spirv_SConvert_Rlong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8_sat(__clc_vec8_uint16_t args_0) { + return __spirv_SConvert_Rlong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8_sat(__clc_vec8_int32_t args_0) { + return __spirv_SConvert_Rlong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SConvert_Rlong8_sat(__clc_vec8_uint32_t args_0) { + return __spirv_SConvert_Rlong8_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rlong_sat.cl b/libclc/test/binding/core/SConvert_Rlong_sat.cl new file mode 100644 index 000000000000..7bea5f5f165a --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rlong_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong_sat(__clc_int8_t args_0) { + return __spirv_SConvert_Rlong_sat(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong_sat(__clc_uint8_t args_0) { + return __spirv_SConvert_Rlong_sat(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong_sat(__clc_int16_t args_0) { + return __spirv_SConvert_Rlong_sat(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong_sat(__clc_uint16_t args_0) { + return __spirv_SConvert_Rlong_sat(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong_sat(__clc_int32_t args_0) { + return __spirv_SConvert_Rlong_sat(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SConvert_Rlong_sat(__clc_uint32_t args_0) { + return __spirv_SConvert_Rlong_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort.cl b/libclc/test/binding/core/SConvert_Rshort.cl new file mode 100644 index 000000000000..3470ee1c5016 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort(__clc_int8_t args_0) { + return __spirv_SConvert_Rshort(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort(__clc_uint8_t args_0) { + return __spirv_SConvert_Rshort(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort(__clc_int32_t args_0) { + return __spirv_SConvert_Rshort(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort(__clc_uint32_t args_0) { + return __spirv_SConvert_Rshort(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort(__clc_int64_t args_0) { + return __spirv_SConvert_Rshort(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort(__clc_uint64_t args_0) { + return __spirv_SConvert_Rshort(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort16.cl b/libclc/test/binding/core/SConvert_Rshort16.cl new file mode 100644 index 000000000000..ff6ea77b8a86 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort16.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16(__clc_vec16_int8_t args_0) { + return __spirv_SConvert_Rshort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16(__clc_vec16_uint8_t args_0) { + return __spirv_SConvert_Rshort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16(__clc_vec16_int32_t args_0) { + return __spirv_SConvert_Rshort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16(__clc_vec16_uint32_t args_0) { + return __spirv_SConvert_Rshort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16(__clc_vec16_int64_t args_0) { + return __spirv_SConvert_Rshort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16(__clc_vec16_uint64_t args_0) { + return __spirv_SConvert_Rshort16(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort16_sat.cl b/libclc/test/binding/core/SConvert_Rshort16_sat.cl new file mode 100644 index 000000000000..ede586d89d10 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort16_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16_sat(__clc_vec16_int8_t args_0) { + return __spirv_SConvert_Rshort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16_sat(__clc_vec16_uint8_t args_0) { + return __spirv_SConvert_Rshort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16_sat(__clc_vec16_int32_t args_0) { + return __spirv_SConvert_Rshort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16_sat(__clc_vec16_uint32_t args_0) { + return __spirv_SConvert_Rshort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16_sat(__clc_vec16_int64_t args_0) { + return __spirv_SConvert_Rshort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SConvert_Rshort16_sat(__clc_vec16_uint64_t args_0) { + return __spirv_SConvert_Rshort16_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort2.cl b/libclc/test/binding/core/SConvert_Rshort2.cl new file mode 100644 index 000000000000..bd5463f5d04b --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2(__clc_vec2_int8_t args_0) { + return __spirv_SConvert_Rshort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2(__clc_vec2_uint8_t args_0) { + return __spirv_SConvert_Rshort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2(__clc_vec2_int32_t args_0) { + return __spirv_SConvert_Rshort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2(__clc_vec2_uint32_t args_0) { + return __spirv_SConvert_Rshort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2(__clc_vec2_int64_t args_0) { + return __spirv_SConvert_Rshort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2(__clc_vec2_uint64_t args_0) { + return __spirv_SConvert_Rshort2(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort2_sat.cl b/libclc/test/binding/core/SConvert_Rshort2_sat.cl new file mode 100644 index 000000000000..49531a889f6d --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort2_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2_sat(__clc_vec2_int8_t args_0) { + return __spirv_SConvert_Rshort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2_sat(__clc_vec2_uint8_t args_0) { + return __spirv_SConvert_Rshort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2_sat(__clc_vec2_int32_t args_0) { + return __spirv_SConvert_Rshort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2_sat(__clc_vec2_uint32_t args_0) { + return __spirv_SConvert_Rshort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2_sat(__clc_vec2_int64_t args_0) { + return __spirv_SConvert_Rshort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SConvert_Rshort2_sat(__clc_vec2_uint64_t args_0) { + return __spirv_SConvert_Rshort2_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort3.cl b/libclc/test/binding/core/SConvert_Rshort3.cl new file mode 100644 index 000000000000..9d091165b138 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort3.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3(__clc_vec3_int8_t args_0) { + return __spirv_SConvert_Rshort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3(__clc_vec3_uint8_t args_0) { + return __spirv_SConvert_Rshort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3(__clc_vec3_int32_t args_0) { + return __spirv_SConvert_Rshort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3(__clc_vec3_uint32_t args_0) { + return __spirv_SConvert_Rshort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3(__clc_vec3_int64_t args_0) { + return __spirv_SConvert_Rshort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3(__clc_vec3_uint64_t args_0) { + return __spirv_SConvert_Rshort3(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort3_sat.cl b/libclc/test/binding/core/SConvert_Rshort3_sat.cl new file mode 100644 index 000000000000..f0aee19db803 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort3_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3_sat(__clc_vec3_int8_t args_0) { + return __spirv_SConvert_Rshort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3_sat(__clc_vec3_uint8_t args_0) { + return __spirv_SConvert_Rshort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3_sat(__clc_vec3_int32_t args_0) { + return __spirv_SConvert_Rshort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3_sat(__clc_vec3_uint32_t args_0) { + return __spirv_SConvert_Rshort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3_sat(__clc_vec3_int64_t args_0) { + return __spirv_SConvert_Rshort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SConvert_Rshort3_sat(__clc_vec3_uint64_t args_0) { + return __spirv_SConvert_Rshort3_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort4.cl b/libclc/test/binding/core/SConvert_Rshort4.cl new file mode 100644 index 000000000000..8ff724eedd6a --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort4.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4(__clc_vec4_int8_t args_0) { + return __spirv_SConvert_Rshort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4(__clc_vec4_uint8_t args_0) { + return __spirv_SConvert_Rshort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4(__clc_vec4_int32_t args_0) { + return __spirv_SConvert_Rshort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4(__clc_vec4_uint32_t args_0) { + return __spirv_SConvert_Rshort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4(__clc_vec4_int64_t args_0) { + return __spirv_SConvert_Rshort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4(__clc_vec4_uint64_t args_0) { + return __spirv_SConvert_Rshort4(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort4_sat.cl b/libclc/test/binding/core/SConvert_Rshort4_sat.cl new file mode 100644 index 000000000000..ca9076a50235 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort4_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4_sat(__clc_vec4_int8_t args_0) { + return __spirv_SConvert_Rshort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4_sat(__clc_vec4_uint8_t args_0) { + return __spirv_SConvert_Rshort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4_sat(__clc_vec4_int32_t args_0) { + return __spirv_SConvert_Rshort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4_sat(__clc_vec4_uint32_t args_0) { + return __spirv_SConvert_Rshort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4_sat(__clc_vec4_int64_t args_0) { + return __spirv_SConvert_Rshort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SConvert_Rshort4_sat(__clc_vec4_uint64_t args_0) { + return __spirv_SConvert_Rshort4_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort8.cl b/libclc/test/binding/core/SConvert_Rshort8.cl new file mode 100644 index 000000000000..25ab06057ecb --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort8.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8(__clc_vec8_int8_t args_0) { + return __spirv_SConvert_Rshort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8(__clc_vec8_uint8_t args_0) { + return __spirv_SConvert_Rshort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8(__clc_vec8_int32_t args_0) { + return __spirv_SConvert_Rshort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8(__clc_vec8_uint32_t args_0) { + return __spirv_SConvert_Rshort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8(__clc_vec8_int64_t args_0) { + return __spirv_SConvert_Rshort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8(__clc_vec8_uint64_t args_0) { + return __spirv_SConvert_Rshort8(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort8_sat.cl b/libclc/test/binding/core/SConvert_Rshort8_sat.cl new file mode 100644 index 000000000000..92674fe96a2f --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort8_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8_sat(__clc_vec8_int8_t args_0) { + return __spirv_SConvert_Rshort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8_sat(__clc_vec8_uint8_t args_0) { + return __spirv_SConvert_Rshort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8_sat(__clc_vec8_int32_t args_0) { + return __spirv_SConvert_Rshort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8_sat(__clc_vec8_uint32_t args_0) { + return __spirv_SConvert_Rshort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8_sat(__clc_vec8_int64_t args_0) { + return __spirv_SConvert_Rshort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SConvert_Rshort8_sat(__clc_vec8_uint64_t args_0) { + return __spirv_SConvert_Rshort8_sat(args_0); +} diff --git a/libclc/test/binding/core/SConvert_Rshort_sat.cl b/libclc/test/binding/core/SConvert_Rshort_sat.cl new file mode 100644 index 000000000000..119b79a03650 --- /dev/null +++ b/libclc/test/binding/core/SConvert_Rshort_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort_sat(__clc_int8_t args_0) { + return __spirv_SConvert_Rshort_sat(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort_sat(__clc_uint8_t args_0) { + return __spirv_SConvert_Rshort_sat(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort_sat(__clc_int32_t args_0) { + return __spirv_SConvert_Rshort_sat(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort_sat(__clc_uint32_t args_0) { + return __spirv_SConvert_Rshort_sat(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort_sat(__clc_int64_t args_0) { + return __spirv_SConvert_Rshort_sat(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SConvert_Rshort_sat(__clc_uint64_t args_0) { + return __spirv_SConvert_Rshort_sat(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruchar.cl b/libclc/test/binding/core/SatConvertSToU_Ruchar.cl new file mode 100644 index 000000000000..8fd75cda1ffe --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruchar.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_SatConvertSToU_Ruchar(__clc_int8_t args_0) { + return __spirv_SatConvertSToU_Ruchar(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_SatConvertSToU_Ruchar(__clc_int16_t args_0) { + return __spirv_SatConvertSToU_Ruchar(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_SatConvertSToU_Ruchar(__clc_int32_t args_0) { + return __spirv_SatConvertSToU_Ruchar(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_SatConvertSToU_Ruchar(__clc_int64_t args_0) { + return __spirv_SatConvertSToU_Ruchar(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruchar16.cl b/libclc/test/binding/core/SatConvertSToU_Ruchar16.cl new file mode 100644 index 000000000000..082ce24ab7d7 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruchar16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_SatConvertSToU_Ruchar16(__clc_vec16_int8_t args_0) { + return __spirv_SatConvertSToU_Ruchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_SatConvertSToU_Ruchar16(__clc_vec16_int16_t args_0) { + return __spirv_SatConvertSToU_Ruchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_SatConvertSToU_Ruchar16(__clc_vec16_int32_t args_0) { + return __spirv_SatConvertSToU_Ruchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_SatConvertSToU_Ruchar16(__clc_vec16_int64_t args_0) { + return __spirv_SatConvertSToU_Ruchar16(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruchar2.cl b/libclc/test/binding/core/SatConvertSToU_Ruchar2.cl new file mode 100644 index 000000000000..97baa9d5a42c --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruchar2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_SatConvertSToU_Ruchar2(__clc_vec2_int8_t args_0) { + return __spirv_SatConvertSToU_Ruchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_SatConvertSToU_Ruchar2(__clc_vec2_int16_t args_0) { + return __spirv_SatConvertSToU_Ruchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_SatConvertSToU_Ruchar2(__clc_vec2_int32_t args_0) { + return __spirv_SatConvertSToU_Ruchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_SatConvertSToU_Ruchar2(__clc_vec2_int64_t args_0) { + return __spirv_SatConvertSToU_Ruchar2(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruchar3.cl b/libclc/test/binding/core/SatConvertSToU_Ruchar3.cl new file mode 100644 index 000000000000..9b3cc21cd690 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruchar3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_SatConvertSToU_Ruchar3(__clc_vec3_int8_t args_0) { + return __spirv_SatConvertSToU_Ruchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_SatConvertSToU_Ruchar3(__clc_vec3_int16_t args_0) { + return __spirv_SatConvertSToU_Ruchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_SatConvertSToU_Ruchar3(__clc_vec3_int32_t args_0) { + return __spirv_SatConvertSToU_Ruchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_SatConvertSToU_Ruchar3(__clc_vec3_int64_t args_0) { + return __spirv_SatConvertSToU_Ruchar3(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruchar4.cl b/libclc/test/binding/core/SatConvertSToU_Ruchar4.cl new file mode 100644 index 000000000000..88c2f9aad617 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruchar4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_SatConvertSToU_Ruchar4(__clc_vec4_int8_t args_0) { + return __spirv_SatConvertSToU_Ruchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_SatConvertSToU_Ruchar4(__clc_vec4_int16_t args_0) { + return __spirv_SatConvertSToU_Ruchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_SatConvertSToU_Ruchar4(__clc_vec4_int32_t args_0) { + return __spirv_SatConvertSToU_Ruchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_SatConvertSToU_Ruchar4(__clc_vec4_int64_t args_0) { + return __spirv_SatConvertSToU_Ruchar4(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruchar8.cl b/libclc/test/binding/core/SatConvertSToU_Ruchar8.cl new file mode 100644 index 000000000000..20bc47da42b6 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruchar8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_SatConvertSToU_Ruchar8(__clc_vec8_int8_t args_0) { + return __spirv_SatConvertSToU_Ruchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_SatConvertSToU_Ruchar8(__clc_vec8_int16_t args_0) { + return __spirv_SatConvertSToU_Ruchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_SatConvertSToU_Ruchar8(__clc_vec8_int32_t args_0) { + return __spirv_SatConvertSToU_Ruchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_SatConvertSToU_Ruchar8(__clc_vec8_int64_t args_0) { + return __spirv_SatConvertSToU_Ruchar8(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruint.cl b/libclc/test/binding/core/SatConvertSToU_Ruint.cl new file mode 100644 index 000000000000..ca28650dddec --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruint.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_SatConvertSToU_Ruint(__clc_int8_t args_0) { + return __spirv_SatConvertSToU_Ruint(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_SatConvertSToU_Ruint(__clc_int16_t args_0) { + return __spirv_SatConvertSToU_Ruint(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_SatConvertSToU_Ruint(__clc_int32_t args_0) { + return __spirv_SatConvertSToU_Ruint(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_SatConvertSToU_Ruint(__clc_int64_t args_0) { + return __spirv_SatConvertSToU_Ruint(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruint16.cl b/libclc/test/binding/core/SatConvertSToU_Ruint16.cl new file mode 100644 index 000000000000..1b494bc09a2d --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruint16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_SatConvertSToU_Ruint16(__clc_vec16_int8_t args_0) { + return __spirv_SatConvertSToU_Ruint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_SatConvertSToU_Ruint16(__clc_vec16_int16_t args_0) { + return __spirv_SatConvertSToU_Ruint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_SatConvertSToU_Ruint16(__clc_vec16_int32_t args_0) { + return __spirv_SatConvertSToU_Ruint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_SatConvertSToU_Ruint16(__clc_vec16_int64_t args_0) { + return __spirv_SatConvertSToU_Ruint16(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruint2.cl b/libclc/test/binding/core/SatConvertSToU_Ruint2.cl new file mode 100644 index 000000000000..644651bc1471 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruint2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_SatConvertSToU_Ruint2(__clc_vec2_int8_t args_0) { + return __spirv_SatConvertSToU_Ruint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_SatConvertSToU_Ruint2(__clc_vec2_int16_t args_0) { + return __spirv_SatConvertSToU_Ruint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_SatConvertSToU_Ruint2(__clc_vec2_int32_t args_0) { + return __spirv_SatConvertSToU_Ruint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_SatConvertSToU_Ruint2(__clc_vec2_int64_t args_0) { + return __spirv_SatConvertSToU_Ruint2(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruint3.cl b/libclc/test/binding/core/SatConvertSToU_Ruint3.cl new file mode 100644 index 000000000000..93c3b9168d75 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruint3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_SatConvertSToU_Ruint3(__clc_vec3_int8_t args_0) { + return __spirv_SatConvertSToU_Ruint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_SatConvertSToU_Ruint3(__clc_vec3_int16_t args_0) { + return __spirv_SatConvertSToU_Ruint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_SatConvertSToU_Ruint3(__clc_vec3_int32_t args_0) { + return __spirv_SatConvertSToU_Ruint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_SatConvertSToU_Ruint3(__clc_vec3_int64_t args_0) { + return __spirv_SatConvertSToU_Ruint3(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruint4.cl b/libclc/test/binding/core/SatConvertSToU_Ruint4.cl new file mode 100644 index 000000000000..85233c10772f --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruint4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_SatConvertSToU_Ruint4(__clc_vec4_int8_t args_0) { + return __spirv_SatConvertSToU_Ruint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_SatConvertSToU_Ruint4(__clc_vec4_int16_t args_0) { + return __spirv_SatConvertSToU_Ruint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_SatConvertSToU_Ruint4(__clc_vec4_int32_t args_0) { + return __spirv_SatConvertSToU_Ruint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_SatConvertSToU_Ruint4(__clc_vec4_int64_t args_0) { + return __spirv_SatConvertSToU_Ruint4(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Ruint8.cl b/libclc/test/binding/core/SatConvertSToU_Ruint8.cl new file mode 100644 index 000000000000..1f29bf1845e8 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Ruint8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_SatConvertSToU_Ruint8(__clc_vec8_int8_t args_0) { + return __spirv_SatConvertSToU_Ruint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_SatConvertSToU_Ruint8(__clc_vec8_int16_t args_0) { + return __spirv_SatConvertSToU_Ruint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_SatConvertSToU_Ruint8(__clc_vec8_int32_t args_0) { + return __spirv_SatConvertSToU_Ruint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_SatConvertSToU_Ruint8(__clc_vec8_int64_t args_0) { + return __spirv_SatConvertSToU_Ruint8(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rulong.cl b/libclc/test/binding/core/SatConvertSToU_Rulong.cl new file mode 100644 index 000000000000..1d7e3e8fe7eb --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rulong.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_SatConvertSToU_Rulong(__clc_int8_t args_0) { + return __spirv_SatConvertSToU_Rulong(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_SatConvertSToU_Rulong(__clc_int16_t args_0) { + return __spirv_SatConvertSToU_Rulong(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_SatConvertSToU_Rulong(__clc_int32_t args_0) { + return __spirv_SatConvertSToU_Rulong(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_SatConvertSToU_Rulong(__clc_int64_t args_0) { + return __spirv_SatConvertSToU_Rulong(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rulong16.cl b/libclc/test/binding/core/SatConvertSToU_Rulong16.cl new file mode 100644 index 000000000000..273ab08339e6 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rulong16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_SatConvertSToU_Rulong16(__clc_vec16_int8_t args_0) { + return __spirv_SatConvertSToU_Rulong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_SatConvertSToU_Rulong16(__clc_vec16_int16_t args_0) { + return __spirv_SatConvertSToU_Rulong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_SatConvertSToU_Rulong16(__clc_vec16_int32_t args_0) { + return __spirv_SatConvertSToU_Rulong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_SatConvertSToU_Rulong16(__clc_vec16_int64_t args_0) { + return __spirv_SatConvertSToU_Rulong16(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rulong2.cl b/libclc/test/binding/core/SatConvertSToU_Rulong2.cl new file mode 100644 index 000000000000..a3afb09b9670 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rulong2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_SatConvertSToU_Rulong2(__clc_vec2_int8_t args_0) { + return __spirv_SatConvertSToU_Rulong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_SatConvertSToU_Rulong2(__clc_vec2_int16_t args_0) { + return __spirv_SatConvertSToU_Rulong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_SatConvertSToU_Rulong2(__clc_vec2_int32_t args_0) { + return __spirv_SatConvertSToU_Rulong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_SatConvertSToU_Rulong2(__clc_vec2_int64_t args_0) { + return __spirv_SatConvertSToU_Rulong2(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rulong3.cl b/libclc/test/binding/core/SatConvertSToU_Rulong3.cl new file mode 100644 index 000000000000..7df1b86e0b84 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rulong3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_SatConvertSToU_Rulong3(__clc_vec3_int8_t args_0) { + return __spirv_SatConvertSToU_Rulong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_SatConvertSToU_Rulong3(__clc_vec3_int16_t args_0) { + return __spirv_SatConvertSToU_Rulong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_SatConvertSToU_Rulong3(__clc_vec3_int32_t args_0) { + return __spirv_SatConvertSToU_Rulong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_SatConvertSToU_Rulong3(__clc_vec3_int64_t args_0) { + return __spirv_SatConvertSToU_Rulong3(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rulong4.cl b/libclc/test/binding/core/SatConvertSToU_Rulong4.cl new file mode 100644 index 000000000000..5f77d9057b0c --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rulong4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_SatConvertSToU_Rulong4(__clc_vec4_int8_t args_0) { + return __spirv_SatConvertSToU_Rulong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_SatConvertSToU_Rulong4(__clc_vec4_int16_t args_0) { + return __spirv_SatConvertSToU_Rulong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_SatConvertSToU_Rulong4(__clc_vec4_int32_t args_0) { + return __spirv_SatConvertSToU_Rulong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_SatConvertSToU_Rulong4(__clc_vec4_int64_t args_0) { + return __spirv_SatConvertSToU_Rulong4(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rulong8.cl b/libclc/test/binding/core/SatConvertSToU_Rulong8.cl new file mode 100644 index 000000000000..7e2701d7fdb2 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rulong8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_SatConvertSToU_Rulong8(__clc_vec8_int8_t args_0) { + return __spirv_SatConvertSToU_Rulong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_SatConvertSToU_Rulong8(__clc_vec8_int16_t args_0) { + return __spirv_SatConvertSToU_Rulong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_SatConvertSToU_Rulong8(__clc_vec8_int32_t args_0) { + return __spirv_SatConvertSToU_Rulong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_SatConvertSToU_Rulong8(__clc_vec8_int64_t args_0) { + return __spirv_SatConvertSToU_Rulong8(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rushort.cl b/libclc/test/binding/core/SatConvertSToU_Rushort.cl new file mode 100644 index 000000000000..30f44941980d --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rushort.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_SatConvertSToU_Rushort(__clc_int8_t args_0) { + return __spirv_SatConvertSToU_Rushort(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_SatConvertSToU_Rushort(__clc_int16_t args_0) { + return __spirv_SatConvertSToU_Rushort(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_SatConvertSToU_Rushort(__clc_int32_t args_0) { + return __spirv_SatConvertSToU_Rushort(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_SatConvertSToU_Rushort(__clc_int64_t args_0) { + return __spirv_SatConvertSToU_Rushort(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rushort16.cl b/libclc/test/binding/core/SatConvertSToU_Rushort16.cl new file mode 100644 index 000000000000..c3c691a5923c --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rushort16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_SatConvertSToU_Rushort16(__clc_vec16_int8_t args_0) { + return __spirv_SatConvertSToU_Rushort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_SatConvertSToU_Rushort16(__clc_vec16_int16_t args_0) { + return __spirv_SatConvertSToU_Rushort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_SatConvertSToU_Rushort16(__clc_vec16_int32_t args_0) { + return __spirv_SatConvertSToU_Rushort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_SatConvertSToU_Rushort16(__clc_vec16_int64_t args_0) { + return __spirv_SatConvertSToU_Rushort16(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rushort2.cl b/libclc/test/binding/core/SatConvertSToU_Rushort2.cl new file mode 100644 index 000000000000..3219c1eb1f7c --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rushort2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_SatConvertSToU_Rushort2(__clc_vec2_int8_t args_0) { + return __spirv_SatConvertSToU_Rushort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_SatConvertSToU_Rushort2(__clc_vec2_int16_t args_0) { + return __spirv_SatConvertSToU_Rushort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_SatConvertSToU_Rushort2(__clc_vec2_int32_t args_0) { + return __spirv_SatConvertSToU_Rushort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_SatConvertSToU_Rushort2(__clc_vec2_int64_t args_0) { + return __spirv_SatConvertSToU_Rushort2(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rushort3.cl b/libclc/test/binding/core/SatConvertSToU_Rushort3.cl new file mode 100644 index 000000000000..4a3a95f19725 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rushort3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_SatConvertSToU_Rushort3(__clc_vec3_int8_t args_0) { + return __spirv_SatConvertSToU_Rushort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_SatConvertSToU_Rushort3(__clc_vec3_int16_t args_0) { + return __spirv_SatConvertSToU_Rushort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_SatConvertSToU_Rushort3(__clc_vec3_int32_t args_0) { + return __spirv_SatConvertSToU_Rushort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_SatConvertSToU_Rushort3(__clc_vec3_int64_t args_0) { + return __spirv_SatConvertSToU_Rushort3(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rushort4.cl b/libclc/test/binding/core/SatConvertSToU_Rushort4.cl new file mode 100644 index 000000000000..88de27dbe470 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rushort4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_SatConvertSToU_Rushort4(__clc_vec4_int8_t args_0) { + return __spirv_SatConvertSToU_Rushort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_SatConvertSToU_Rushort4(__clc_vec4_int16_t args_0) { + return __spirv_SatConvertSToU_Rushort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_SatConvertSToU_Rushort4(__clc_vec4_int32_t args_0) { + return __spirv_SatConvertSToU_Rushort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_SatConvertSToU_Rushort4(__clc_vec4_int64_t args_0) { + return __spirv_SatConvertSToU_Rushort4(args_0); +} diff --git a/libclc/test/binding/core/SatConvertSToU_Rushort8.cl b/libclc/test/binding/core/SatConvertSToU_Rushort8.cl new file mode 100644 index 000000000000..33971c00ce55 --- /dev/null +++ b/libclc/test/binding/core/SatConvertSToU_Rushort8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_SatConvertSToU_Rushort8(__clc_vec8_int8_t args_0) { + return __spirv_SatConvertSToU_Rushort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_SatConvertSToU_Rushort8(__clc_vec8_int16_t args_0) { + return __spirv_SatConvertSToU_Rushort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_SatConvertSToU_Rushort8(__clc_vec8_int32_t args_0) { + return __spirv_SatConvertSToU_Rushort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_SatConvertSToU_Rushort8(__clc_vec8_int64_t args_0) { + return __spirv_SatConvertSToU_Rushort8(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rchar.cl b/libclc/test/binding/core/SatConvertUToS_Rchar.cl new file mode 100644 index 000000000000..29664c0ea803 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rchar.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_SatConvertUToS_Rchar(__clc_uint8_t args_0) { + return __spirv_SatConvertUToS_Rchar(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SatConvertUToS_Rchar(__clc_uint16_t args_0) { + return __spirv_SatConvertUToS_Rchar(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SatConvertUToS_Rchar(__clc_uint32_t args_0) { + return __spirv_SatConvertUToS_Rchar(args_0); +} + +__attribute__((overloadable)) __clc_int8_t +test___spirv_SatConvertUToS_Rchar(__clc_uint64_t args_0) { + return __spirv_SatConvertUToS_Rchar(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rchar16.cl b/libclc/test/binding/core/SatConvertUToS_Rchar16.cl new file mode 100644 index 000000000000..5a7045ae3553 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rchar16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SatConvertUToS_Rchar16(__clc_vec16_uint8_t args_0) { + return __spirv_SatConvertUToS_Rchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SatConvertUToS_Rchar16(__clc_vec16_uint16_t args_0) { + return __spirv_SatConvertUToS_Rchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SatConvertUToS_Rchar16(__clc_vec16_uint32_t args_0) { + return __spirv_SatConvertUToS_Rchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_SatConvertUToS_Rchar16(__clc_vec16_uint64_t args_0) { + return __spirv_SatConvertUToS_Rchar16(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rchar2.cl b/libclc/test/binding/core/SatConvertUToS_Rchar2.cl new file mode 100644 index 000000000000..84bf45bd5003 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rchar2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SatConvertUToS_Rchar2(__clc_vec2_uint8_t args_0) { + return __spirv_SatConvertUToS_Rchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SatConvertUToS_Rchar2(__clc_vec2_uint16_t args_0) { + return __spirv_SatConvertUToS_Rchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SatConvertUToS_Rchar2(__clc_vec2_uint32_t args_0) { + return __spirv_SatConvertUToS_Rchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_SatConvertUToS_Rchar2(__clc_vec2_uint64_t args_0) { + return __spirv_SatConvertUToS_Rchar2(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rchar3.cl b/libclc/test/binding/core/SatConvertUToS_Rchar3.cl new file mode 100644 index 000000000000..6fc5b4d95a39 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rchar3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SatConvertUToS_Rchar3(__clc_vec3_uint8_t args_0) { + return __spirv_SatConvertUToS_Rchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SatConvertUToS_Rchar3(__clc_vec3_uint16_t args_0) { + return __spirv_SatConvertUToS_Rchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SatConvertUToS_Rchar3(__clc_vec3_uint32_t args_0) { + return __spirv_SatConvertUToS_Rchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_SatConvertUToS_Rchar3(__clc_vec3_uint64_t args_0) { + return __spirv_SatConvertUToS_Rchar3(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rchar4.cl b/libclc/test/binding/core/SatConvertUToS_Rchar4.cl new file mode 100644 index 000000000000..7682e4244b7a --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rchar4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SatConvertUToS_Rchar4(__clc_vec4_uint8_t args_0) { + return __spirv_SatConvertUToS_Rchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SatConvertUToS_Rchar4(__clc_vec4_uint16_t args_0) { + return __spirv_SatConvertUToS_Rchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SatConvertUToS_Rchar4(__clc_vec4_uint32_t args_0) { + return __spirv_SatConvertUToS_Rchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_SatConvertUToS_Rchar4(__clc_vec4_uint64_t args_0) { + return __spirv_SatConvertUToS_Rchar4(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rchar8.cl b/libclc/test/binding/core/SatConvertUToS_Rchar8.cl new file mode 100644 index 000000000000..2843bdb92f90 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rchar8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SatConvertUToS_Rchar8(__clc_vec8_uint8_t args_0) { + return __spirv_SatConvertUToS_Rchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SatConvertUToS_Rchar8(__clc_vec8_uint16_t args_0) { + return __spirv_SatConvertUToS_Rchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SatConvertUToS_Rchar8(__clc_vec8_uint32_t args_0) { + return __spirv_SatConvertUToS_Rchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_SatConvertUToS_Rchar8(__clc_vec8_uint64_t args_0) { + return __spirv_SatConvertUToS_Rchar8(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rint.cl b/libclc/test/binding/core/SatConvertUToS_Rint.cl new file mode 100644 index 000000000000..3a46415d1f80 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rint.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_SatConvertUToS_Rint(__clc_uint8_t args_0) { + return __spirv_SatConvertUToS_Rint(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SatConvertUToS_Rint(__clc_uint16_t args_0) { + return __spirv_SatConvertUToS_Rint(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SatConvertUToS_Rint(__clc_uint32_t args_0) { + return __spirv_SatConvertUToS_Rint(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_SatConvertUToS_Rint(__clc_uint64_t args_0) { + return __spirv_SatConvertUToS_Rint(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rint16.cl b/libclc/test/binding/core/SatConvertUToS_Rint16.cl new file mode 100644 index 000000000000..f5e7701e139a --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rint16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SatConvertUToS_Rint16(__clc_vec16_uint8_t args_0) { + return __spirv_SatConvertUToS_Rint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SatConvertUToS_Rint16(__clc_vec16_uint16_t args_0) { + return __spirv_SatConvertUToS_Rint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SatConvertUToS_Rint16(__clc_vec16_uint32_t args_0) { + return __spirv_SatConvertUToS_Rint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_SatConvertUToS_Rint16(__clc_vec16_uint64_t args_0) { + return __spirv_SatConvertUToS_Rint16(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rint2.cl b/libclc/test/binding/core/SatConvertUToS_Rint2.cl new file mode 100644 index 000000000000..22761803d7e9 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rint2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SatConvertUToS_Rint2(__clc_vec2_uint8_t args_0) { + return __spirv_SatConvertUToS_Rint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SatConvertUToS_Rint2(__clc_vec2_uint16_t args_0) { + return __spirv_SatConvertUToS_Rint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SatConvertUToS_Rint2(__clc_vec2_uint32_t args_0) { + return __spirv_SatConvertUToS_Rint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_SatConvertUToS_Rint2(__clc_vec2_uint64_t args_0) { + return __spirv_SatConvertUToS_Rint2(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rint3.cl b/libclc/test/binding/core/SatConvertUToS_Rint3.cl new file mode 100644 index 000000000000..df85cf90ab4a --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rint3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SatConvertUToS_Rint3(__clc_vec3_uint8_t args_0) { + return __spirv_SatConvertUToS_Rint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SatConvertUToS_Rint3(__clc_vec3_uint16_t args_0) { + return __spirv_SatConvertUToS_Rint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SatConvertUToS_Rint3(__clc_vec3_uint32_t args_0) { + return __spirv_SatConvertUToS_Rint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_SatConvertUToS_Rint3(__clc_vec3_uint64_t args_0) { + return __spirv_SatConvertUToS_Rint3(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rint4.cl b/libclc/test/binding/core/SatConvertUToS_Rint4.cl new file mode 100644 index 000000000000..608a796d033a --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rint4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SatConvertUToS_Rint4(__clc_vec4_uint8_t args_0) { + return __spirv_SatConvertUToS_Rint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SatConvertUToS_Rint4(__clc_vec4_uint16_t args_0) { + return __spirv_SatConvertUToS_Rint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SatConvertUToS_Rint4(__clc_vec4_uint32_t args_0) { + return __spirv_SatConvertUToS_Rint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_SatConvertUToS_Rint4(__clc_vec4_uint64_t args_0) { + return __spirv_SatConvertUToS_Rint4(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rint8.cl b/libclc/test/binding/core/SatConvertUToS_Rint8.cl new file mode 100644 index 000000000000..9fcd191035dc --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rint8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SatConvertUToS_Rint8(__clc_vec8_uint8_t args_0) { + return __spirv_SatConvertUToS_Rint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SatConvertUToS_Rint8(__clc_vec8_uint16_t args_0) { + return __spirv_SatConvertUToS_Rint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SatConvertUToS_Rint8(__clc_vec8_uint32_t args_0) { + return __spirv_SatConvertUToS_Rint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_SatConvertUToS_Rint8(__clc_vec8_uint64_t args_0) { + return __spirv_SatConvertUToS_Rint8(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rlong.cl b/libclc/test/binding/core/SatConvertUToS_Rlong.cl new file mode 100644 index 000000000000..a5ddae5394ca --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rlong.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int64_t +test___spirv_SatConvertUToS_Rlong(__clc_uint8_t args_0) { + return __spirv_SatConvertUToS_Rlong(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SatConvertUToS_Rlong(__clc_uint16_t args_0) { + return __spirv_SatConvertUToS_Rlong(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SatConvertUToS_Rlong(__clc_uint32_t args_0) { + return __spirv_SatConvertUToS_Rlong(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_SatConvertUToS_Rlong(__clc_uint64_t args_0) { + return __spirv_SatConvertUToS_Rlong(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rlong16.cl b/libclc/test/binding/core/SatConvertUToS_Rlong16.cl new file mode 100644 index 000000000000..4da3f1960dbe --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rlong16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SatConvertUToS_Rlong16(__clc_vec16_uint8_t args_0) { + return __spirv_SatConvertUToS_Rlong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SatConvertUToS_Rlong16(__clc_vec16_uint16_t args_0) { + return __spirv_SatConvertUToS_Rlong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SatConvertUToS_Rlong16(__clc_vec16_uint32_t args_0) { + return __spirv_SatConvertUToS_Rlong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_SatConvertUToS_Rlong16(__clc_vec16_uint64_t args_0) { + return __spirv_SatConvertUToS_Rlong16(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rlong2.cl b/libclc/test/binding/core/SatConvertUToS_Rlong2.cl new file mode 100644 index 000000000000..a232f4296b0b --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rlong2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SatConvertUToS_Rlong2(__clc_vec2_uint8_t args_0) { + return __spirv_SatConvertUToS_Rlong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SatConvertUToS_Rlong2(__clc_vec2_uint16_t args_0) { + return __spirv_SatConvertUToS_Rlong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SatConvertUToS_Rlong2(__clc_vec2_uint32_t args_0) { + return __spirv_SatConvertUToS_Rlong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_SatConvertUToS_Rlong2(__clc_vec2_uint64_t args_0) { + return __spirv_SatConvertUToS_Rlong2(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rlong3.cl b/libclc/test/binding/core/SatConvertUToS_Rlong3.cl new file mode 100644 index 000000000000..34556d38e5a5 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rlong3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SatConvertUToS_Rlong3(__clc_vec3_uint8_t args_0) { + return __spirv_SatConvertUToS_Rlong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SatConvertUToS_Rlong3(__clc_vec3_uint16_t args_0) { + return __spirv_SatConvertUToS_Rlong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SatConvertUToS_Rlong3(__clc_vec3_uint32_t args_0) { + return __spirv_SatConvertUToS_Rlong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_SatConvertUToS_Rlong3(__clc_vec3_uint64_t args_0) { + return __spirv_SatConvertUToS_Rlong3(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rlong4.cl b/libclc/test/binding/core/SatConvertUToS_Rlong4.cl new file mode 100644 index 000000000000..d9d845b57d32 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rlong4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SatConvertUToS_Rlong4(__clc_vec4_uint8_t args_0) { + return __spirv_SatConvertUToS_Rlong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SatConvertUToS_Rlong4(__clc_vec4_uint16_t args_0) { + return __spirv_SatConvertUToS_Rlong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SatConvertUToS_Rlong4(__clc_vec4_uint32_t args_0) { + return __spirv_SatConvertUToS_Rlong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_SatConvertUToS_Rlong4(__clc_vec4_uint64_t args_0) { + return __spirv_SatConvertUToS_Rlong4(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rlong8.cl b/libclc/test/binding/core/SatConvertUToS_Rlong8.cl new file mode 100644 index 000000000000..8f68358668f7 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rlong8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SatConvertUToS_Rlong8(__clc_vec8_uint8_t args_0) { + return __spirv_SatConvertUToS_Rlong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SatConvertUToS_Rlong8(__clc_vec8_uint16_t args_0) { + return __spirv_SatConvertUToS_Rlong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SatConvertUToS_Rlong8(__clc_vec8_uint32_t args_0) { + return __spirv_SatConvertUToS_Rlong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_SatConvertUToS_Rlong8(__clc_vec8_uint64_t args_0) { + return __spirv_SatConvertUToS_Rlong8(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rshort.cl b/libclc/test/binding/core/SatConvertUToS_Rshort.cl new file mode 100644 index 000000000000..20d5689373fd --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rshort.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_SatConvertUToS_Rshort(__clc_uint8_t args_0) { + return __spirv_SatConvertUToS_Rshort(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SatConvertUToS_Rshort(__clc_uint16_t args_0) { + return __spirv_SatConvertUToS_Rshort(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SatConvertUToS_Rshort(__clc_uint32_t args_0) { + return __spirv_SatConvertUToS_Rshort(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_SatConvertUToS_Rshort(__clc_uint64_t args_0) { + return __spirv_SatConvertUToS_Rshort(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rshort16.cl b/libclc/test/binding/core/SatConvertUToS_Rshort16.cl new file mode 100644 index 000000000000..adc69a2c94b2 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rshort16.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SatConvertUToS_Rshort16(__clc_vec16_uint8_t args_0) { + return __spirv_SatConvertUToS_Rshort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SatConvertUToS_Rshort16(__clc_vec16_uint16_t args_0) { + return __spirv_SatConvertUToS_Rshort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SatConvertUToS_Rshort16(__clc_vec16_uint32_t args_0) { + return __spirv_SatConvertUToS_Rshort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_SatConvertUToS_Rshort16(__clc_vec16_uint64_t args_0) { + return __spirv_SatConvertUToS_Rshort16(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rshort2.cl b/libclc/test/binding/core/SatConvertUToS_Rshort2.cl new file mode 100644 index 000000000000..f5a0eb2a850b --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rshort2.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SatConvertUToS_Rshort2(__clc_vec2_uint8_t args_0) { + return __spirv_SatConvertUToS_Rshort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SatConvertUToS_Rshort2(__clc_vec2_uint16_t args_0) { + return __spirv_SatConvertUToS_Rshort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SatConvertUToS_Rshort2(__clc_vec2_uint32_t args_0) { + return __spirv_SatConvertUToS_Rshort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_SatConvertUToS_Rshort2(__clc_vec2_uint64_t args_0) { + return __spirv_SatConvertUToS_Rshort2(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rshort3.cl b/libclc/test/binding/core/SatConvertUToS_Rshort3.cl new file mode 100644 index 000000000000..ee8130d85c82 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rshort3.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SatConvertUToS_Rshort3(__clc_vec3_uint8_t args_0) { + return __spirv_SatConvertUToS_Rshort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SatConvertUToS_Rshort3(__clc_vec3_uint16_t args_0) { + return __spirv_SatConvertUToS_Rshort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SatConvertUToS_Rshort3(__clc_vec3_uint32_t args_0) { + return __spirv_SatConvertUToS_Rshort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_SatConvertUToS_Rshort3(__clc_vec3_uint64_t args_0) { + return __spirv_SatConvertUToS_Rshort3(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rshort4.cl b/libclc/test/binding/core/SatConvertUToS_Rshort4.cl new file mode 100644 index 000000000000..9a614dde9d76 --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rshort4.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SatConvertUToS_Rshort4(__clc_vec4_uint8_t args_0) { + return __spirv_SatConvertUToS_Rshort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SatConvertUToS_Rshort4(__clc_vec4_uint16_t args_0) { + return __spirv_SatConvertUToS_Rshort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SatConvertUToS_Rshort4(__clc_vec4_uint32_t args_0) { + return __spirv_SatConvertUToS_Rshort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_SatConvertUToS_Rshort4(__clc_vec4_uint64_t args_0) { + return __spirv_SatConvertUToS_Rshort4(args_0); +} diff --git a/libclc/test/binding/core/SatConvertUToS_Rshort8.cl b/libclc/test/binding/core/SatConvertUToS_Rshort8.cl new file mode 100644 index 000000000000..f0f7a290787a --- /dev/null +++ b/libclc/test/binding/core/SatConvertUToS_Rshort8.cl @@ -0,0 +1,36 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SatConvertUToS_Rshort8(__clc_vec8_uint8_t args_0) { + return __spirv_SatConvertUToS_Rshort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SatConvertUToS_Rshort8(__clc_vec8_uint16_t args_0) { + return __spirv_SatConvertUToS_Rshort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SatConvertUToS_Rshort8(__clc_vec8_uint32_t args_0) { + return __spirv_SatConvertUToS_Rshort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_SatConvertUToS_Rshort8(__clc_vec8_uint64_t args_0) { + return __spirv_SatConvertUToS_Rshort8(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar.cl b/libclc/test/binding/core/UConvert_Ruchar.cl new file mode 100644 index 000000000000..e3b4ac9678b0 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar(__clc_int16_t args_0) { + return __spirv_UConvert_Ruchar(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar(__clc_uint16_t args_0) { + return __spirv_UConvert_Ruchar(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar(__clc_int32_t args_0) { + return __spirv_UConvert_Ruchar(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar(__clc_uint32_t args_0) { + return __spirv_UConvert_Ruchar(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar(__clc_int64_t args_0) { + return __spirv_UConvert_Ruchar(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar(__clc_uint64_t args_0) { + return __spirv_UConvert_Ruchar(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar16.cl b/libclc/test/binding/core/UConvert_Ruchar16.cl new file mode 100644 index 000000000000..b5121d78f0c3 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar16.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16(__clc_vec16_int16_t args_0) { + return __spirv_UConvert_Ruchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16(__clc_vec16_uint16_t args_0) { + return __spirv_UConvert_Ruchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16(__clc_vec16_int32_t args_0) { + return __spirv_UConvert_Ruchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16(__clc_vec16_uint32_t args_0) { + return __spirv_UConvert_Ruchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16(__clc_vec16_int64_t args_0) { + return __spirv_UConvert_Ruchar16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16(__clc_vec16_uint64_t args_0) { + return __spirv_UConvert_Ruchar16(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar16_sat.cl b/libclc/test/binding/core/UConvert_Ruchar16_sat.cl new file mode 100644 index 000000000000..15bee307a13e --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar16_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16_sat(__clc_vec16_int16_t args_0) { + return __spirv_UConvert_Ruchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16_sat(__clc_vec16_uint16_t args_0) { + return __spirv_UConvert_Ruchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16_sat(__clc_vec16_int32_t args_0) { + return __spirv_UConvert_Ruchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16_sat(__clc_vec16_uint32_t args_0) { + return __spirv_UConvert_Ruchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16_sat(__clc_vec16_int64_t args_0) { + return __spirv_UConvert_Ruchar16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_UConvert_Ruchar16_sat(__clc_vec16_uint64_t args_0) { + return __spirv_UConvert_Ruchar16_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar2.cl b/libclc/test/binding/core/UConvert_Ruchar2.cl new file mode 100644 index 000000000000..c9ba50728e57 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2(__clc_vec2_int16_t args_0) { + return __spirv_UConvert_Ruchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2(__clc_vec2_uint16_t args_0) { + return __spirv_UConvert_Ruchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2(__clc_vec2_int32_t args_0) { + return __spirv_UConvert_Ruchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2(__clc_vec2_uint32_t args_0) { + return __spirv_UConvert_Ruchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2(__clc_vec2_int64_t args_0) { + return __spirv_UConvert_Ruchar2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2(__clc_vec2_uint64_t args_0) { + return __spirv_UConvert_Ruchar2(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar2_sat.cl b/libclc/test/binding/core/UConvert_Ruchar2_sat.cl new file mode 100644 index 000000000000..ae2396272519 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar2_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2_sat(__clc_vec2_int16_t args_0) { + return __spirv_UConvert_Ruchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2_sat(__clc_vec2_uint16_t args_0) { + return __spirv_UConvert_Ruchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2_sat(__clc_vec2_int32_t args_0) { + return __spirv_UConvert_Ruchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2_sat(__clc_vec2_uint32_t args_0) { + return __spirv_UConvert_Ruchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2_sat(__clc_vec2_int64_t args_0) { + return __spirv_UConvert_Ruchar2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_UConvert_Ruchar2_sat(__clc_vec2_uint64_t args_0) { + return __spirv_UConvert_Ruchar2_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar3.cl b/libclc/test/binding/core/UConvert_Ruchar3.cl new file mode 100644 index 000000000000..e1f6d117e5bb --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar3.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3(__clc_vec3_int16_t args_0) { + return __spirv_UConvert_Ruchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3(__clc_vec3_uint16_t args_0) { + return __spirv_UConvert_Ruchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3(__clc_vec3_int32_t args_0) { + return __spirv_UConvert_Ruchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3(__clc_vec3_uint32_t args_0) { + return __spirv_UConvert_Ruchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3(__clc_vec3_int64_t args_0) { + return __spirv_UConvert_Ruchar3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3(__clc_vec3_uint64_t args_0) { + return __spirv_UConvert_Ruchar3(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar3_sat.cl b/libclc/test/binding/core/UConvert_Ruchar3_sat.cl new file mode 100644 index 000000000000..90afdde1bef9 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar3_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3_sat(__clc_vec3_int16_t args_0) { + return __spirv_UConvert_Ruchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3_sat(__clc_vec3_uint16_t args_0) { + return __spirv_UConvert_Ruchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3_sat(__clc_vec3_int32_t args_0) { + return __spirv_UConvert_Ruchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3_sat(__clc_vec3_uint32_t args_0) { + return __spirv_UConvert_Ruchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3_sat(__clc_vec3_int64_t args_0) { + return __spirv_UConvert_Ruchar3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_UConvert_Ruchar3_sat(__clc_vec3_uint64_t args_0) { + return __spirv_UConvert_Ruchar3_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar4.cl b/libclc/test/binding/core/UConvert_Ruchar4.cl new file mode 100644 index 000000000000..5ad13eb6bec4 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar4.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4(__clc_vec4_int16_t args_0) { + return __spirv_UConvert_Ruchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4(__clc_vec4_uint16_t args_0) { + return __spirv_UConvert_Ruchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4(__clc_vec4_int32_t args_0) { + return __spirv_UConvert_Ruchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4(__clc_vec4_uint32_t args_0) { + return __spirv_UConvert_Ruchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4(__clc_vec4_int64_t args_0) { + return __spirv_UConvert_Ruchar4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4(__clc_vec4_uint64_t args_0) { + return __spirv_UConvert_Ruchar4(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar4_sat.cl b/libclc/test/binding/core/UConvert_Ruchar4_sat.cl new file mode 100644 index 000000000000..75aed18559d1 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar4_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4_sat(__clc_vec4_int16_t args_0) { + return __spirv_UConvert_Ruchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4_sat(__clc_vec4_uint16_t args_0) { + return __spirv_UConvert_Ruchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4_sat(__clc_vec4_int32_t args_0) { + return __spirv_UConvert_Ruchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4_sat(__clc_vec4_uint32_t args_0) { + return __spirv_UConvert_Ruchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4_sat(__clc_vec4_int64_t args_0) { + return __spirv_UConvert_Ruchar4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_UConvert_Ruchar4_sat(__clc_vec4_uint64_t args_0) { + return __spirv_UConvert_Ruchar4_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar8.cl b/libclc/test/binding/core/UConvert_Ruchar8.cl new file mode 100644 index 000000000000..9c3ef35fd2da --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar8.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8(__clc_vec8_int16_t args_0) { + return __spirv_UConvert_Ruchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8(__clc_vec8_uint16_t args_0) { + return __spirv_UConvert_Ruchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8(__clc_vec8_int32_t args_0) { + return __spirv_UConvert_Ruchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8(__clc_vec8_uint32_t args_0) { + return __spirv_UConvert_Ruchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8(__clc_vec8_int64_t args_0) { + return __spirv_UConvert_Ruchar8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8(__clc_vec8_uint64_t args_0) { + return __spirv_UConvert_Ruchar8(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar8_sat.cl b/libclc/test/binding/core/UConvert_Ruchar8_sat.cl new file mode 100644 index 000000000000..b845bc9a1f2c --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar8_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8_sat(__clc_vec8_int16_t args_0) { + return __spirv_UConvert_Ruchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8_sat(__clc_vec8_uint16_t args_0) { + return __spirv_UConvert_Ruchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8_sat(__clc_vec8_int32_t args_0) { + return __spirv_UConvert_Ruchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8_sat(__clc_vec8_uint32_t args_0) { + return __spirv_UConvert_Ruchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8_sat(__clc_vec8_int64_t args_0) { + return __spirv_UConvert_Ruchar8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_UConvert_Ruchar8_sat(__clc_vec8_uint64_t args_0) { + return __spirv_UConvert_Ruchar8_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruchar_sat.cl b/libclc/test/binding/core/UConvert_Ruchar_sat.cl new file mode 100644 index 000000000000..db22796f18f2 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruchar_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar_sat(__clc_int16_t args_0) { + return __spirv_UConvert_Ruchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar_sat(__clc_uint16_t args_0) { + return __spirv_UConvert_Ruchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar_sat(__clc_int32_t args_0) { + return __spirv_UConvert_Ruchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar_sat(__clc_uint32_t args_0) { + return __spirv_UConvert_Ruchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar_sat(__clc_int64_t args_0) { + return __spirv_UConvert_Ruchar_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_UConvert_Ruchar_sat(__clc_uint64_t args_0) { + return __spirv_UConvert_Ruchar_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint.cl b/libclc/test/binding/core/UConvert_Ruint.cl new file mode 100644 index 000000000000..000c8fe0cbc3 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint(__clc_int8_t args_0) { + return __spirv_UConvert_Ruint(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint(__clc_uint8_t args_0) { + return __spirv_UConvert_Ruint(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint(__clc_int16_t args_0) { + return __spirv_UConvert_Ruint(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint(__clc_uint16_t args_0) { + return __spirv_UConvert_Ruint(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint(__clc_int64_t args_0) { + return __spirv_UConvert_Ruint(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint(__clc_uint64_t args_0) { + return __spirv_UConvert_Ruint(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint16.cl b/libclc/test/binding/core/UConvert_Ruint16.cl new file mode 100644 index 000000000000..8cfa8603dccb --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint16.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16(__clc_vec16_int8_t args_0) { + return __spirv_UConvert_Ruint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16(__clc_vec16_uint8_t args_0) { + return __spirv_UConvert_Ruint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16(__clc_vec16_int16_t args_0) { + return __spirv_UConvert_Ruint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16(__clc_vec16_uint16_t args_0) { + return __spirv_UConvert_Ruint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16(__clc_vec16_int64_t args_0) { + return __spirv_UConvert_Ruint16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16(__clc_vec16_uint64_t args_0) { + return __spirv_UConvert_Ruint16(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint16_sat.cl b/libclc/test/binding/core/UConvert_Ruint16_sat.cl new file mode 100644 index 000000000000..770ddef3ed1d --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint16_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16_sat(__clc_vec16_int8_t args_0) { + return __spirv_UConvert_Ruint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16_sat(__clc_vec16_uint8_t args_0) { + return __spirv_UConvert_Ruint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16_sat(__clc_vec16_int16_t args_0) { + return __spirv_UConvert_Ruint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16_sat(__clc_vec16_uint16_t args_0) { + return __spirv_UConvert_Ruint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16_sat(__clc_vec16_int64_t args_0) { + return __spirv_UConvert_Ruint16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_UConvert_Ruint16_sat(__clc_vec16_uint64_t args_0) { + return __spirv_UConvert_Ruint16_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint2.cl b/libclc/test/binding/core/UConvert_Ruint2.cl new file mode 100644 index 000000000000..e341cf0c7d36 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2(__clc_vec2_int8_t args_0) { + return __spirv_UConvert_Ruint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2(__clc_vec2_uint8_t args_0) { + return __spirv_UConvert_Ruint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2(__clc_vec2_int16_t args_0) { + return __spirv_UConvert_Ruint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2(__clc_vec2_uint16_t args_0) { + return __spirv_UConvert_Ruint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2(__clc_vec2_int64_t args_0) { + return __spirv_UConvert_Ruint2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2(__clc_vec2_uint64_t args_0) { + return __spirv_UConvert_Ruint2(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint2_sat.cl b/libclc/test/binding/core/UConvert_Ruint2_sat.cl new file mode 100644 index 000000000000..27bdda62f81e --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint2_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2_sat(__clc_vec2_int8_t args_0) { + return __spirv_UConvert_Ruint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2_sat(__clc_vec2_uint8_t args_0) { + return __spirv_UConvert_Ruint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2_sat(__clc_vec2_int16_t args_0) { + return __spirv_UConvert_Ruint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2_sat(__clc_vec2_uint16_t args_0) { + return __spirv_UConvert_Ruint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2_sat(__clc_vec2_int64_t args_0) { + return __spirv_UConvert_Ruint2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_UConvert_Ruint2_sat(__clc_vec2_uint64_t args_0) { + return __spirv_UConvert_Ruint2_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint3.cl b/libclc/test/binding/core/UConvert_Ruint3.cl new file mode 100644 index 000000000000..c713f1aaa39b --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint3.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3(__clc_vec3_int8_t args_0) { + return __spirv_UConvert_Ruint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3(__clc_vec3_uint8_t args_0) { + return __spirv_UConvert_Ruint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3(__clc_vec3_int16_t args_0) { + return __spirv_UConvert_Ruint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3(__clc_vec3_uint16_t args_0) { + return __spirv_UConvert_Ruint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3(__clc_vec3_int64_t args_0) { + return __spirv_UConvert_Ruint3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3(__clc_vec3_uint64_t args_0) { + return __spirv_UConvert_Ruint3(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint3_sat.cl b/libclc/test/binding/core/UConvert_Ruint3_sat.cl new file mode 100644 index 000000000000..c58caf5e7279 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint3_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3_sat(__clc_vec3_int8_t args_0) { + return __spirv_UConvert_Ruint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3_sat(__clc_vec3_uint8_t args_0) { + return __spirv_UConvert_Ruint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3_sat(__clc_vec3_int16_t args_0) { + return __spirv_UConvert_Ruint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3_sat(__clc_vec3_uint16_t args_0) { + return __spirv_UConvert_Ruint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3_sat(__clc_vec3_int64_t args_0) { + return __spirv_UConvert_Ruint3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_UConvert_Ruint3_sat(__clc_vec3_uint64_t args_0) { + return __spirv_UConvert_Ruint3_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint4.cl b/libclc/test/binding/core/UConvert_Ruint4.cl new file mode 100644 index 000000000000..ff9e404cc5ec --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint4.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4(__clc_vec4_int8_t args_0) { + return __spirv_UConvert_Ruint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4(__clc_vec4_uint8_t args_0) { + return __spirv_UConvert_Ruint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4(__clc_vec4_int16_t args_0) { + return __spirv_UConvert_Ruint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4(__clc_vec4_uint16_t args_0) { + return __spirv_UConvert_Ruint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4(__clc_vec4_int64_t args_0) { + return __spirv_UConvert_Ruint4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4(__clc_vec4_uint64_t args_0) { + return __spirv_UConvert_Ruint4(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint4_sat.cl b/libclc/test/binding/core/UConvert_Ruint4_sat.cl new file mode 100644 index 000000000000..9fc0619a5e7e --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint4_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4_sat(__clc_vec4_int8_t args_0) { + return __spirv_UConvert_Ruint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4_sat(__clc_vec4_uint8_t args_0) { + return __spirv_UConvert_Ruint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4_sat(__clc_vec4_int16_t args_0) { + return __spirv_UConvert_Ruint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4_sat(__clc_vec4_uint16_t args_0) { + return __spirv_UConvert_Ruint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4_sat(__clc_vec4_int64_t args_0) { + return __spirv_UConvert_Ruint4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_UConvert_Ruint4_sat(__clc_vec4_uint64_t args_0) { + return __spirv_UConvert_Ruint4_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint8.cl b/libclc/test/binding/core/UConvert_Ruint8.cl new file mode 100644 index 000000000000..48b5504a0212 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint8.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8(__clc_vec8_int8_t args_0) { + return __spirv_UConvert_Ruint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8(__clc_vec8_uint8_t args_0) { + return __spirv_UConvert_Ruint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8(__clc_vec8_int16_t args_0) { + return __spirv_UConvert_Ruint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8(__clc_vec8_uint16_t args_0) { + return __spirv_UConvert_Ruint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8(__clc_vec8_int64_t args_0) { + return __spirv_UConvert_Ruint8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8(__clc_vec8_uint64_t args_0) { + return __spirv_UConvert_Ruint8(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint8_sat.cl b/libclc/test/binding/core/UConvert_Ruint8_sat.cl new file mode 100644 index 000000000000..4899031ab7ec --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint8_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8_sat(__clc_vec8_int8_t args_0) { + return __spirv_UConvert_Ruint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8_sat(__clc_vec8_uint8_t args_0) { + return __spirv_UConvert_Ruint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8_sat(__clc_vec8_int16_t args_0) { + return __spirv_UConvert_Ruint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8_sat(__clc_vec8_uint16_t args_0) { + return __spirv_UConvert_Ruint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8_sat(__clc_vec8_int64_t args_0) { + return __spirv_UConvert_Ruint8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_UConvert_Ruint8_sat(__clc_vec8_uint64_t args_0) { + return __spirv_UConvert_Ruint8_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Ruint_sat.cl b/libclc/test/binding/core/UConvert_Ruint_sat.cl new file mode 100644 index 000000000000..895d349ca283 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Ruint_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint_sat(__clc_int8_t args_0) { + return __spirv_UConvert_Ruint_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint_sat(__clc_uint8_t args_0) { + return __spirv_UConvert_Ruint_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint_sat(__clc_int16_t args_0) { + return __spirv_UConvert_Ruint_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint_sat(__clc_uint16_t args_0) { + return __spirv_UConvert_Ruint_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint_sat(__clc_int64_t args_0) { + return __spirv_UConvert_Ruint_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_UConvert_Ruint_sat(__clc_uint64_t args_0) { + return __spirv_UConvert_Ruint_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong.cl b/libclc/test/binding/core/UConvert_Rulong.cl new file mode 100644 index 000000000000..51b471b6c931 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong(__clc_int8_t args_0) { + return __spirv_UConvert_Rulong(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong(__clc_uint8_t args_0) { + return __spirv_UConvert_Rulong(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong(__clc_int16_t args_0) { + return __spirv_UConvert_Rulong(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong(__clc_uint16_t args_0) { + return __spirv_UConvert_Rulong(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong(__clc_int32_t args_0) { + return __spirv_UConvert_Rulong(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong(__clc_uint32_t args_0) { + return __spirv_UConvert_Rulong(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong16.cl b/libclc/test/binding/core/UConvert_Rulong16.cl new file mode 100644 index 000000000000..10f4c6821d35 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong16.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16(__clc_vec16_int8_t args_0) { + return __spirv_UConvert_Rulong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16(__clc_vec16_uint8_t args_0) { + return __spirv_UConvert_Rulong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16(__clc_vec16_int16_t args_0) { + return __spirv_UConvert_Rulong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16(__clc_vec16_uint16_t args_0) { + return __spirv_UConvert_Rulong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16(__clc_vec16_int32_t args_0) { + return __spirv_UConvert_Rulong16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16(__clc_vec16_uint32_t args_0) { + return __spirv_UConvert_Rulong16(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong16_sat.cl b/libclc/test/binding/core/UConvert_Rulong16_sat.cl new file mode 100644 index 000000000000..a2add5a98ed2 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong16_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16_sat(__clc_vec16_int8_t args_0) { + return __spirv_UConvert_Rulong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16_sat(__clc_vec16_uint8_t args_0) { + return __spirv_UConvert_Rulong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16_sat(__clc_vec16_int16_t args_0) { + return __spirv_UConvert_Rulong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16_sat(__clc_vec16_uint16_t args_0) { + return __spirv_UConvert_Rulong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16_sat(__clc_vec16_int32_t args_0) { + return __spirv_UConvert_Rulong16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_UConvert_Rulong16_sat(__clc_vec16_uint32_t args_0) { + return __spirv_UConvert_Rulong16_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong2.cl b/libclc/test/binding/core/UConvert_Rulong2.cl new file mode 100644 index 000000000000..5fc1c530d44c --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2(__clc_vec2_int8_t args_0) { + return __spirv_UConvert_Rulong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2(__clc_vec2_uint8_t args_0) { + return __spirv_UConvert_Rulong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2(__clc_vec2_int16_t args_0) { + return __spirv_UConvert_Rulong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2(__clc_vec2_uint16_t args_0) { + return __spirv_UConvert_Rulong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2(__clc_vec2_int32_t args_0) { + return __spirv_UConvert_Rulong2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2(__clc_vec2_uint32_t args_0) { + return __spirv_UConvert_Rulong2(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong2_sat.cl b/libclc/test/binding/core/UConvert_Rulong2_sat.cl new file mode 100644 index 000000000000..ca634ef14ee5 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong2_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2_sat(__clc_vec2_int8_t args_0) { + return __spirv_UConvert_Rulong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2_sat(__clc_vec2_uint8_t args_0) { + return __spirv_UConvert_Rulong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2_sat(__clc_vec2_int16_t args_0) { + return __spirv_UConvert_Rulong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2_sat(__clc_vec2_uint16_t args_0) { + return __spirv_UConvert_Rulong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2_sat(__clc_vec2_int32_t args_0) { + return __spirv_UConvert_Rulong2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_UConvert_Rulong2_sat(__clc_vec2_uint32_t args_0) { + return __spirv_UConvert_Rulong2_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong3.cl b/libclc/test/binding/core/UConvert_Rulong3.cl new file mode 100644 index 000000000000..95bb0a29cae9 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong3.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3(__clc_vec3_int8_t args_0) { + return __spirv_UConvert_Rulong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3(__clc_vec3_uint8_t args_0) { + return __spirv_UConvert_Rulong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3(__clc_vec3_int16_t args_0) { + return __spirv_UConvert_Rulong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3(__clc_vec3_uint16_t args_0) { + return __spirv_UConvert_Rulong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3(__clc_vec3_int32_t args_0) { + return __spirv_UConvert_Rulong3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3(__clc_vec3_uint32_t args_0) { + return __spirv_UConvert_Rulong3(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong3_sat.cl b/libclc/test/binding/core/UConvert_Rulong3_sat.cl new file mode 100644 index 000000000000..b1bbeb63eb6b --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong3_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3_sat(__clc_vec3_int8_t args_0) { + return __spirv_UConvert_Rulong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3_sat(__clc_vec3_uint8_t args_0) { + return __spirv_UConvert_Rulong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3_sat(__clc_vec3_int16_t args_0) { + return __spirv_UConvert_Rulong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3_sat(__clc_vec3_uint16_t args_0) { + return __spirv_UConvert_Rulong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3_sat(__clc_vec3_int32_t args_0) { + return __spirv_UConvert_Rulong3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_UConvert_Rulong3_sat(__clc_vec3_uint32_t args_0) { + return __spirv_UConvert_Rulong3_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong4.cl b/libclc/test/binding/core/UConvert_Rulong4.cl new file mode 100644 index 000000000000..af3bfd7f9c63 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong4.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4(__clc_vec4_int8_t args_0) { + return __spirv_UConvert_Rulong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4(__clc_vec4_uint8_t args_0) { + return __spirv_UConvert_Rulong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4(__clc_vec4_int16_t args_0) { + return __spirv_UConvert_Rulong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4(__clc_vec4_uint16_t args_0) { + return __spirv_UConvert_Rulong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4(__clc_vec4_int32_t args_0) { + return __spirv_UConvert_Rulong4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4(__clc_vec4_uint32_t args_0) { + return __spirv_UConvert_Rulong4(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong4_sat.cl b/libclc/test/binding/core/UConvert_Rulong4_sat.cl new file mode 100644 index 000000000000..36bed83ecf1e --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong4_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4_sat(__clc_vec4_int8_t args_0) { + return __spirv_UConvert_Rulong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4_sat(__clc_vec4_uint8_t args_0) { + return __spirv_UConvert_Rulong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4_sat(__clc_vec4_int16_t args_0) { + return __spirv_UConvert_Rulong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4_sat(__clc_vec4_uint16_t args_0) { + return __spirv_UConvert_Rulong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4_sat(__clc_vec4_int32_t args_0) { + return __spirv_UConvert_Rulong4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_UConvert_Rulong4_sat(__clc_vec4_uint32_t args_0) { + return __spirv_UConvert_Rulong4_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong8.cl b/libclc/test/binding/core/UConvert_Rulong8.cl new file mode 100644 index 000000000000..f16233dc01aa --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong8.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8(__clc_vec8_int8_t args_0) { + return __spirv_UConvert_Rulong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8(__clc_vec8_uint8_t args_0) { + return __spirv_UConvert_Rulong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8(__clc_vec8_int16_t args_0) { + return __spirv_UConvert_Rulong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8(__clc_vec8_uint16_t args_0) { + return __spirv_UConvert_Rulong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8(__clc_vec8_int32_t args_0) { + return __spirv_UConvert_Rulong8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8(__clc_vec8_uint32_t args_0) { + return __spirv_UConvert_Rulong8(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong8_sat.cl b/libclc/test/binding/core/UConvert_Rulong8_sat.cl new file mode 100644 index 000000000000..1724ab7d0142 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong8_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8_sat(__clc_vec8_int8_t args_0) { + return __spirv_UConvert_Rulong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8_sat(__clc_vec8_uint8_t args_0) { + return __spirv_UConvert_Rulong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8_sat(__clc_vec8_int16_t args_0) { + return __spirv_UConvert_Rulong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8_sat(__clc_vec8_uint16_t args_0) { + return __spirv_UConvert_Rulong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8_sat(__clc_vec8_int32_t args_0) { + return __spirv_UConvert_Rulong8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_UConvert_Rulong8_sat(__clc_vec8_uint32_t args_0) { + return __spirv_UConvert_Rulong8_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rulong_sat.cl b/libclc/test/binding/core/UConvert_Rulong_sat.cl new file mode 100644 index 000000000000..f98724668f22 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rulong_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong_sat(__clc_int8_t args_0) { + return __spirv_UConvert_Rulong_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong_sat(__clc_uint8_t args_0) { + return __spirv_UConvert_Rulong_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong_sat(__clc_int16_t args_0) { + return __spirv_UConvert_Rulong_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong_sat(__clc_uint16_t args_0) { + return __spirv_UConvert_Rulong_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong_sat(__clc_int32_t args_0) { + return __spirv_UConvert_Rulong_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_UConvert_Rulong_sat(__clc_uint32_t args_0) { + return __spirv_UConvert_Rulong_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort.cl b/libclc/test/binding/core/UConvert_Rushort.cl new file mode 100644 index 000000000000..7336f7bfe2b8 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort(__clc_int8_t args_0) { + return __spirv_UConvert_Rushort(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort(__clc_uint8_t args_0) { + return __spirv_UConvert_Rushort(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort(__clc_int32_t args_0) { + return __spirv_UConvert_Rushort(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort(__clc_uint32_t args_0) { + return __spirv_UConvert_Rushort(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort(__clc_int64_t args_0) { + return __spirv_UConvert_Rushort(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort(__clc_uint64_t args_0) { + return __spirv_UConvert_Rushort(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort16.cl b/libclc/test/binding/core/UConvert_Rushort16.cl new file mode 100644 index 000000000000..ca2d62e43fbc --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort16.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16(__clc_vec16_int8_t args_0) { + return __spirv_UConvert_Rushort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16(__clc_vec16_uint8_t args_0) { + return __spirv_UConvert_Rushort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16(__clc_vec16_int32_t args_0) { + return __spirv_UConvert_Rushort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16(__clc_vec16_uint32_t args_0) { + return __spirv_UConvert_Rushort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16(__clc_vec16_int64_t args_0) { + return __spirv_UConvert_Rushort16(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16(__clc_vec16_uint64_t args_0) { + return __spirv_UConvert_Rushort16(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort16_sat.cl b/libclc/test/binding/core/UConvert_Rushort16_sat.cl new file mode 100644 index 000000000000..c40d7be98ea2 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort16_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16_sat(__clc_vec16_int8_t args_0) { + return __spirv_UConvert_Rushort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16_sat(__clc_vec16_uint8_t args_0) { + return __spirv_UConvert_Rushort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16_sat(__clc_vec16_int32_t args_0) { + return __spirv_UConvert_Rushort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16_sat(__clc_vec16_uint32_t args_0) { + return __spirv_UConvert_Rushort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16_sat(__clc_vec16_int64_t args_0) { + return __spirv_UConvert_Rushort16_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_UConvert_Rushort16_sat(__clc_vec16_uint64_t args_0) { + return __spirv_UConvert_Rushort16_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort2.cl b/libclc/test/binding/core/UConvert_Rushort2.cl new file mode 100644 index 000000000000..d77bac291bc4 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2(__clc_vec2_int8_t args_0) { + return __spirv_UConvert_Rushort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2(__clc_vec2_uint8_t args_0) { + return __spirv_UConvert_Rushort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2(__clc_vec2_int32_t args_0) { + return __spirv_UConvert_Rushort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2(__clc_vec2_uint32_t args_0) { + return __spirv_UConvert_Rushort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2(__clc_vec2_int64_t args_0) { + return __spirv_UConvert_Rushort2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2(__clc_vec2_uint64_t args_0) { + return __spirv_UConvert_Rushort2(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort2_sat.cl b/libclc/test/binding/core/UConvert_Rushort2_sat.cl new file mode 100644 index 000000000000..dc909174e773 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort2_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2_sat(__clc_vec2_int8_t args_0) { + return __spirv_UConvert_Rushort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2_sat(__clc_vec2_uint8_t args_0) { + return __spirv_UConvert_Rushort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2_sat(__clc_vec2_int32_t args_0) { + return __spirv_UConvert_Rushort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2_sat(__clc_vec2_uint32_t args_0) { + return __spirv_UConvert_Rushort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2_sat(__clc_vec2_int64_t args_0) { + return __spirv_UConvert_Rushort2_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_UConvert_Rushort2_sat(__clc_vec2_uint64_t args_0) { + return __spirv_UConvert_Rushort2_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort3.cl b/libclc/test/binding/core/UConvert_Rushort3.cl new file mode 100644 index 000000000000..e8c6f4be3f55 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort3.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3(__clc_vec3_int8_t args_0) { + return __spirv_UConvert_Rushort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3(__clc_vec3_uint8_t args_0) { + return __spirv_UConvert_Rushort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3(__clc_vec3_int32_t args_0) { + return __spirv_UConvert_Rushort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3(__clc_vec3_uint32_t args_0) { + return __spirv_UConvert_Rushort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3(__clc_vec3_int64_t args_0) { + return __spirv_UConvert_Rushort3(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3(__clc_vec3_uint64_t args_0) { + return __spirv_UConvert_Rushort3(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort3_sat.cl b/libclc/test/binding/core/UConvert_Rushort3_sat.cl new file mode 100644 index 000000000000..95a6c68525a0 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort3_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3_sat(__clc_vec3_int8_t args_0) { + return __spirv_UConvert_Rushort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3_sat(__clc_vec3_uint8_t args_0) { + return __spirv_UConvert_Rushort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3_sat(__clc_vec3_int32_t args_0) { + return __spirv_UConvert_Rushort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3_sat(__clc_vec3_uint32_t args_0) { + return __spirv_UConvert_Rushort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3_sat(__clc_vec3_int64_t args_0) { + return __spirv_UConvert_Rushort3_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_UConvert_Rushort3_sat(__clc_vec3_uint64_t args_0) { + return __spirv_UConvert_Rushort3_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort4.cl b/libclc/test/binding/core/UConvert_Rushort4.cl new file mode 100644 index 000000000000..dd8177f982d9 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort4.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4(__clc_vec4_int8_t args_0) { + return __spirv_UConvert_Rushort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4(__clc_vec4_uint8_t args_0) { + return __spirv_UConvert_Rushort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4(__clc_vec4_int32_t args_0) { + return __spirv_UConvert_Rushort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4(__clc_vec4_uint32_t args_0) { + return __spirv_UConvert_Rushort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4(__clc_vec4_int64_t args_0) { + return __spirv_UConvert_Rushort4(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4(__clc_vec4_uint64_t args_0) { + return __spirv_UConvert_Rushort4(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort4_sat.cl b/libclc/test/binding/core/UConvert_Rushort4_sat.cl new file mode 100644 index 000000000000..1e0424ef8fac --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort4_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4_sat(__clc_vec4_int8_t args_0) { + return __spirv_UConvert_Rushort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4_sat(__clc_vec4_uint8_t args_0) { + return __spirv_UConvert_Rushort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4_sat(__clc_vec4_int32_t args_0) { + return __spirv_UConvert_Rushort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4_sat(__clc_vec4_uint32_t args_0) { + return __spirv_UConvert_Rushort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4_sat(__clc_vec4_int64_t args_0) { + return __spirv_UConvert_Rushort4_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_UConvert_Rushort4_sat(__clc_vec4_uint64_t args_0) { + return __spirv_UConvert_Rushort4_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort8.cl b/libclc/test/binding/core/UConvert_Rushort8.cl new file mode 100644 index 000000000000..834e1551f411 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort8.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8(__clc_vec8_int8_t args_0) { + return __spirv_UConvert_Rushort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8(__clc_vec8_uint8_t args_0) { + return __spirv_UConvert_Rushort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8(__clc_vec8_int32_t args_0) { + return __spirv_UConvert_Rushort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8(__clc_vec8_uint32_t args_0) { + return __spirv_UConvert_Rushort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8(__clc_vec8_int64_t args_0) { + return __spirv_UConvert_Rushort8(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8(__clc_vec8_uint64_t args_0) { + return __spirv_UConvert_Rushort8(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort8_sat.cl b/libclc/test/binding/core/UConvert_Rushort8_sat.cl new file mode 100644 index 000000000000..18861083b554 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort8_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8_sat(__clc_vec8_int8_t args_0) { + return __spirv_UConvert_Rushort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8_sat(__clc_vec8_uint8_t args_0) { + return __spirv_UConvert_Rushort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8_sat(__clc_vec8_int32_t args_0) { + return __spirv_UConvert_Rushort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8_sat(__clc_vec8_uint32_t args_0) { + return __spirv_UConvert_Rushort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8_sat(__clc_vec8_int64_t args_0) { + return __spirv_UConvert_Rushort8_sat(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_UConvert_Rushort8_sat(__clc_vec8_uint64_t args_0) { + return __spirv_UConvert_Rushort8_sat(args_0); +} diff --git a/libclc/test/binding/core/UConvert_Rushort_sat.cl b/libclc/test/binding/core/UConvert_Rushort_sat.cl new file mode 100644 index 000000000000..378efa0aed48 --- /dev/null +++ b/libclc/test/binding/core/UConvert_Rushort_sat.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort_sat(__clc_int8_t args_0) { + return __spirv_UConvert_Rushort_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort_sat(__clc_uint8_t args_0) { + return __spirv_UConvert_Rushort_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort_sat(__clc_int32_t args_0) { + return __spirv_UConvert_Rushort_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort_sat(__clc_uint32_t args_0) { + return __spirv_UConvert_Rushort_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort_sat(__clc_int64_t args_0) { + return __spirv_UConvert_Rushort_sat(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_UConvert_Rushort_sat(__clc_uint64_t args_0) { + return __spirv_UConvert_Rushort_sat(args_0); +} diff --git a/libclc/test/binding/core/VectorTimesScalar.cl b/libclc/test/binding/core/VectorTimesScalar.cl new file mode 100644 index 000000000000..2d75ad61fb0a --- /dev/null +++ b/libclc/test/binding/core/VectorTimesScalar.cl @@ -0,0 +1,112 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_VectorTimesScalar(__clc_vec2_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_VectorTimesScalar(__clc_vec3_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_VectorTimesScalar(__clc_vec4_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_VectorTimesScalar(__clc_vec8_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_VectorTimesScalar(__clc_vec16_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_VectorTimesScalar(__clc_vec2_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_VectorTimesScalar(__clc_vec3_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_VectorTimesScalar(__clc_vec4_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_VectorTimesScalar(__clc_vec8_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_VectorTimesScalar(__clc_vec16_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_VectorTimesScalar(__clc_vec2_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_VectorTimesScalar(__clc_vec3_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_VectorTimesScalar(__clc_vec4_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_VectorTimesScalar(__clc_vec8_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_VectorTimesScalar(__clc_vec16_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_VectorTimesScalar(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/shuffle.cl b/libclc/test/binding/ocl/shuffle.cl new file mode 100644 index 000000000000..1cb0ed1d8c7a --- /dev/null +++ b/libclc/test/binding/ocl/shuffle.cl @@ -0,0 +1,1086 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_shuffle(__clc_vec2_int8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_shuffle(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_shuffle(__clc_vec2_int16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_shuffle(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_shuffle(__clc_vec2_int32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_shuffle(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_shuffle(__clc_vec2_int64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_shuffle(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_shuffle(__clc_vec2_fp32_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_shuffle(__clc_vec2_fp64_t args_0, __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_shuffle(__clc_vec2_fp16_t args_0, __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_shuffle(__clc_vec4_int8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_shuffle(__clc_vec4_uint8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_shuffle(__clc_vec4_int16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_shuffle(__clc_vec4_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_shuffle(__clc_vec4_int32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_shuffle(__clc_vec4_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_shuffle(__clc_vec4_int64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_shuffle(__clc_vec4_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_shuffle(__clc_vec4_fp32_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_shuffle(__clc_vec4_fp64_t args_0, __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_shuffle(__clc_vec4_fp16_t args_0, __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_shuffle(__clc_vec8_int8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_shuffle(__clc_vec8_uint8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_shuffle(__clc_vec8_int16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_shuffle(__clc_vec8_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_shuffle(__clc_vec8_int32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_shuffle(__clc_vec8_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_shuffle(__clc_vec8_int64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_shuffle(__clc_vec8_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_shuffle(__clc_vec8_fp32_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_shuffle(__clc_vec8_fp64_t args_0, __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_shuffle(__clc_vec8_fp16_t args_0, __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_shuffle(__clc_vec16_int8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_shuffle(__clc_vec16_uint8_t args_0, + __clc_vec2_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_shuffle(__clc_vec16_int16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_shuffle(__clc_vec16_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_shuffle(__clc_vec16_int32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_shuffle(__clc_vec16_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_shuffle(__clc_vec16_int64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_shuffle(__clc_vec16_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_shuffle(__clc_vec16_fp32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_shuffle(__clc_vec16_fp64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_shuffle(__clc_vec16_fp16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_shuffle(__clc_vec2_int8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_shuffle(__clc_vec2_uint8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_shuffle(__clc_vec2_int16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_shuffle(__clc_vec2_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_shuffle(__clc_vec2_int32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_shuffle(__clc_vec2_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_shuffle(__clc_vec2_int64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_shuffle(__clc_vec2_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_shuffle(__clc_vec2_fp32_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_shuffle(__clc_vec2_fp64_t args_0, __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_shuffle(__clc_vec2_fp16_t args_0, __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_shuffle(__clc_vec4_int8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_shuffle(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_shuffle(__clc_vec4_int16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_shuffle(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_shuffle(__clc_vec4_int32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_shuffle(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_shuffle(__clc_vec4_int64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_shuffle(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_shuffle(__clc_vec4_fp32_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_shuffle(__clc_vec4_fp64_t args_0, __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_shuffle(__clc_vec4_fp16_t args_0, __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_shuffle(__clc_vec8_int8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_shuffle(__clc_vec8_uint8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_shuffle(__clc_vec8_int16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_shuffle(__clc_vec8_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_shuffle(__clc_vec8_int32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_shuffle(__clc_vec8_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_shuffle(__clc_vec8_int64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_shuffle(__clc_vec8_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_shuffle(__clc_vec8_fp32_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_shuffle(__clc_vec8_fp64_t args_0, __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_shuffle(__clc_vec8_fp16_t args_0, __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_shuffle(__clc_vec16_int8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_shuffle(__clc_vec16_uint8_t args_0, + __clc_vec4_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_shuffle(__clc_vec16_int16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_shuffle(__clc_vec16_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_shuffle(__clc_vec16_int32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_shuffle(__clc_vec16_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_shuffle(__clc_vec16_int64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_shuffle(__clc_vec16_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_shuffle(__clc_vec16_fp32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_shuffle(__clc_vec16_fp64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_shuffle(__clc_vec16_fp16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_shuffle(__clc_vec2_int8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_shuffle(__clc_vec2_uint8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_shuffle(__clc_vec2_int16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_shuffle(__clc_vec2_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_shuffle(__clc_vec2_int32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_shuffle(__clc_vec2_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_shuffle(__clc_vec2_int64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_shuffle(__clc_vec2_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_shuffle(__clc_vec2_fp32_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_shuffle(__clc_vec2_fp64_t args_0, __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_shuffle(__clc_vec2_fp16_t args_0, __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_shuffle(__clc_vec4_int8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_shuffle(__clc_vec4_uint8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_shuffle(__clc_vec4_int16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_shuffle(__clc_vec4_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_shuffle(__clc_vec4_int32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_shuffle(__clc_vec4_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_shuffle(__clc_vec4_int64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_shuffle(__clc_vec4_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_shuffle(__clc_vec4_fp32_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_shuffle(__clc_vec4_fp64_t args_0, __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_shuffle(__clc_vec4_fp16_t args_0, __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_shuffle(__clc_vec8_int8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_shuffle(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_shuffle(__clc_vec8_int16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_shuffle(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_shuffle(__clc_vec8_int32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_shuffle(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_shuffle(__clc_vec8_int64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_shuffle(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_shuffle(__clc_vec8_fp32_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_shuffle(__clc_vec8_fp64_t args_0, __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_shuffle(__clc_vec8_fp16_t args_0, __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_shuffle(__clc_vec16_int8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_shuffle(__clc_vec16_uint8_t args_0, + __clc_vec8_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_shuffle(__clc_vec16_int16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_shuffle(__clc_vec16_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_shuffle(__clc_vec16_int32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_shuffle(__clc_vec16_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_shuffle(__clc_vec16_int64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_shuffle(__clc_vec16_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_shuffle(__clc_vec16_fp32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_shuffle(__clc_vec16_fp64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_shuffle(__clc_vec16_fp16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_shuffle(__clc_vec2_int8_t args_0, __clc_vec16_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_shuffle(__clc_vec2_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_shuffle(__clc_vec2_int16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_shuffle(__clc_vec2_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_shuffle(__clc_vec2_int32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_shuffle(__clc_vec2_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_shuffle(__clc_vec2_int64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_shuffle(__clc_vec2_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_shuffle(__clc_vec2_fp32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_shuffle(__clc_vec2_fp64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_shuffle(__clc_vec2_fp16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_shuffle(__clc_vec4_int8_t args_0, __clc_vec16_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_shuffle(__clc_vec4_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_shuffle(__clc_vec4_int16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_shuffle(__clc_vec4_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_shuffle(__clc_vec4_int32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_shuffle(__clc_vec4_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_shuffle(__clc_vec4_int64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_shuffle(__clc_vec4_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_shuffle(__clc_vec4_fp32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_shuffle(__clc_vec4_fp64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_shuffle(__clc_vec4_fp16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_shuffle(__clc_vec8_int8_t args_0, __clc_vec16_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_shuffle(__clc_vec8_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_shuffle(__clc_vec8_int16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_shuffle(__clc_vec8_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_shuffle(__clc_vec8_int32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_shuffle(__clc_vec8_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_shuffle(__clc_vec8_int64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_shuffle(__clc_vec8_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_shuffle(__clc_vec8_fp32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_shuffle(__clc_vec8_fp64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_shuffle(__clc_vec8_fp16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_shuffle(__clc_vec16_int8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_shuffle(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_shuffle(__clc_vec16_int16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_shuffle(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_shuffle(__clc_vec16_int32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_shuffle(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_shuffle(__clc_vec16_int64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_shuffle(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_shuffle(__clc_vec16_fp32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_shuffle(__clc_vec16_fp64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_shuffle(__clc_vec16_fp16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_shuffle(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/shuffle2.cl b/libclc/test/binding/ocl/shuffle2.cl new file mode 100644 index 000000000000..bbfd8956c35b --- /dev/null +++ b/libclc/test/binding/ocl/shuffle2.cl @@ -0,0 +1,1201 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_shuffle2(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_shuffle2(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_shuffle2(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_shuffle2(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_shuffle2(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_shuffle2(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_shuffle2(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_shuffle2(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_shuffle2(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_shuffle2(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_shuffle2(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_shuffle2(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_shuffle2(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_shuffle2(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_shuffle2(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_shuffle2(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_shuffle2(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_shuffle2(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_shuffle2(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_shuffle2(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_shuffle2(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_shuffle2(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_shuffle2(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_shuffle2(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_shuffle2(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_shuffle2(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_shuffle2(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_shuffle2(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_shuffle2(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_shuffle2(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_shuffle2(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_shuffle2(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_shuffle2(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_shuffle2(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_shuffle2(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_shuffle2(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_shuffle2(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_shuffle2(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_shuffle2(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_shuffle2(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_shuffle2(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_shuffle2(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_shuffle2(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_shuffle2(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_shuffle2(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_shuffle2(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_shuffle2(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_shuffle2(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_shuffle2(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_shuffle2(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_shuffle2(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_shuffle2(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_shuffle2(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_shuffle2(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_shuffle2(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_shuffle2(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_shuffle2(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_shuffle2(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_shuffle2(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_shuffle2(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_shuffle2(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_shuffle2(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_shuffle2(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_shuffle2(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_shuffle2(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_shuffle2(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_shuffle2(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_shuffle2(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_shuffle2(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_shuffle2(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_shuffle2(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_shuffle2(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_shuffle2(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_shuffle2(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_shuffle2(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_shuffle2(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_shuffle2(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_shuffle2(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_shuffle2(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_shuffle2(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_shuffle2(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_shuffle2(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_shuffle2(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_shuffle2(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_shuffle2(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_shuffle2(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_shuffle2(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_shuffle2(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_shuffle2(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_shuffle2(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_shuffle2(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_shuffle2(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_shuffle2(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_shuffle2(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_shuffle2(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_shuffle2(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_shuffle2(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_shuffle2(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_shuffle2(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_shuffle2(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_shuffle2(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_shuffle2(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_shuffle2(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_shuffle2(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_shuffle2(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_shuffle2(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_shuffle2(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_shuffle2(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_shuffle2(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_shuffle2(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_shuffle2(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_shuffle2(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_shuffle2(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_shuffle2(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_shuffle2(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_shuffle2(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_shuffle2(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_shuffle2(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_shuffle2(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_shuffle2(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_shuffle2(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_shuffle2(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_shuffle2(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_shuffle2(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_shuffle2(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_shuffle2(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_shuffle2(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_shuffle2(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_shuffle2(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_shuffle2(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_shuffle2(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_shuffle2(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_shuffle2(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_shuffle2(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_shuffle2(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_shuffle2(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_shuffle2(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_shuffle2(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_shuffle2(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_shuffle2(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_shuffle2(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_shuffle2(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_shuffle2(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_shuffle2(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_shuffle2(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_shuffle2(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_shuffle2(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_shuffle2(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_shuffle2(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_shuffle2(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_shuffle2(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_shuffle2(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_shuffle2(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_shuffle2(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_shuffle2(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_shuffle2(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_shuffle2(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_shuffle2(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_shuffle2(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_shuffle2(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_shuffle2(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_shuffle2(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_shuffle2(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_shuffle2(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_shuffle2(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_shuffle2(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_shuffle2(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_shuffle2(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_shuffle2(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_shuffle2(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_shuffle2(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_shuffle2(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_shuffle2(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_shuffle2(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_shuffle2(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_shuffle2(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_shuffle2(args_0, args_1, args_2); +} + +#endif diff --git a/libclc/utils/gen-libclc-test.py b/libclc/utils/gen-libclc-test.py index e2af837254d7..2dc3d5b311fe 100755 --- a/libclc/utils/gen-libclc-test.py +++ b/libclc/utils/gen-libclc-test.py @@ -13,7 +13,6 @@ def ignore_function(fun): blacklist = [ - "Convert", "GenericCastToPtrExplicit", "GenericPtrMemSemantics", "GroupAll", @@ -27,9 +26,7 @@ def ignore_function(fun): "GroupSMin", "GroupUMax", "GroupUMin", - "printf", - "VectorTimesScalar", - "shuffle" + "printf" ] return any([fun.find(b) != -1 for b in blacklist])