diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index ce58dff5833fd..900d65e8db056 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -1216,7 +1216,8 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr { } def SYCLIntelNumSimdWorkItems : InheritableAttr { - let Spellings = [CXX11<"intelfpga","num_simd_work_items">]; + let Spellings = [CXX11<"intelfpga","num_simd_work_items">, + CXX11<"intel","num_simd_work_items">]; let Args = [ExprArgument<"Value">]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let Subjects = SubjectList<[Function], ErrorDiag>; @@ -1225,7 +1226,8 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr { } def SYCLIntelMaxWorkGroupSize : InheritableAttr { - let Spellings = [CXX11<"intelfpga","max_work_group_size">]; + let Spellings = [CXX11<"intelfpga","max_work_group_size">, + CXX11<"intel","max_work_group_size">]; let Args = [UnsignedArgument<"XDim">, UnsignedArgument<"YDim">, UnsignedArgument<"ZDim">]; @@ -1236,7 +1238,8 @@ def SYCLIntelMaxWorkGroupSize : InheritableAttr { } def SYCLIntelMaxGlobalWorkDim : InheritableAttr { - let Spellings = [CXX11<"intelfpga","max_global_work_dim">]; + let Spellings = [CXX11<"intelfpga","max_global_work_dim">, + CXX11<"intel","max_global_work_dim">]; let Args = [UnsignedArgument<"Number">]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let Subjects = SubjectList<[Function], ErrorDiag>; @@ -1245,7 +1248,8 @@ def SYCLIntelMaxGlobalWorkDim : InheritableAttr { } def SYCLIntelNoGlobalWorkOffset : InheritableAttr { - let Spellings = [CXX11<"intelfpga","no_global_work_offset">]; + let Spellings = [CXX11<"intelfpga","no_global_work_offset">, + CXX11<"intel","no_global_work_offset">]; let Args = [BoolArgument<"Enabled", 1>]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let Subjects = SubjectList<[Function], ErrorDiag>; @@ -1686,7 +1690,8 @@ def Mode : Attr { } def SYCLIntelFPGAIVDep : Attr { - let Spellings = [CXX11<"intelfpga","ivdep">]; + let Spellings = [CXX11<"intelfpga","ivdep">, + CXX11<"intel","ivdep">]; let Args = [ ExprArgument<"SafelenExpr">, ExprArgument<"ArrayExpr">, UnsignedArgument<"SafelenValue"> @@ -1732,7 +1737,8 @@ def SYCLIntelFPGAIVDep : Attr { } def SYCLIntelFPGAII : Attr { - let Spellings = [CXX11<"intelfpga","ii">]; + let Spellings = [CXX11<"intelfpga","ii">, + CXX11<"intel","ii">]; let Args = [ExprArgument<"IntervalExpr">]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let HasCustomTypeTransform = 1; @@ -1745,7 +1751,8 @@ def SYCLIntelFPGAII : Attr { } def SYCLIntelFPGAMaxConcurrency : Attr { - let Spellings = [CXX11<"intelfpga","max_concurrency">]; + let Spellings = [CXX11<"intelfpga","max_concurrency">, + CXX11<"intel","max_concurrency">]; let Args = [ExprArgument<"NThreadsExpr">]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let HasCustomTypeTransform = 1; @@ -1758,7 +1765,8 @@ def SYCLIntelFPGAMaxConcurrency : Attr { } def SYCLIntelFPGALoopCoalesce : Attr { - let Spellings = [CXX11<"intelfpga","loop_coalesce">]; + let Spellings = [CXX11<"intelfpga","loop_coalesce">, + CXX11<"intel","loop_coalesce">]; let Args = [ExprArgument<"NExpr">]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let HasCustomTypeTransform = 1; @@ -1771,7 +1779,8 @@ def SYCLIntelFPGALoopCoalesce : Attr { } def SYCLIntelFPGADisableLoopPipelining : Attr { - let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">]; + let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">, + CXX11<"intel","disable_loop_pipelining">]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let HasCustomTypeTransform = 1; let AdditionalMembers = [{ @@ -1783,7 +1792,8 @@ def SYCLIntelFPGADisableLoopPipelining : Attr { } def SYCLIntelFPGAMaxInterleaving : Attr { - let Spellings = [CXX11<"intelfpga","max_interleaving">]; + let Spellings = [CXX11<"intelfpga","max_interleaving">, + CXX11<"intel","max_interleaving">]; let Args = [ExprArgument<"NExpr">]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let HasCustomTypeTransform = 1; @@ -1796,7 +1806,8 @@ def SYCLIntelFPGAMaxInterleaving : Attr { } def SYCLIntelFPGASpeculatedIterations : Attr { - let Spellings = [CXX11<"intelfpga","speculated_iterations">]; + let Spellings = [CXX11<"intelfpga","speculated_iterations">, + CXX11<"intel","speculated_iterations">]; let Args = [ExprArgument<"NExpr">]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let HasCustomTypeTransform = 1; @@ -1841,7 +1852,8 @@ def IntelFPGALocalOrStaticVar : SubsetSubject; def IntelFPGADoublePump : Attr { - let Spellings = [CXX11<"intelfpga", "doublepump">]; + let Spellings = [CXX11<"intelfpga", "doublepump">, + CXX11<"intel", "doublepump">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar, Field], ErrorDiag>; let LangOpts = [SYCLIsDevice, SYCLIsHost]; @@ -1849,7 +1861,8 @@ def IntelFPGADoublePump : Attr { } def IntelFPGASinglePump : Attr { - let Spellings = [CXX11<"intelfpga", "singlepump">]; + let Spellings = [CXX11<"intelfpga", "singlepump">, + CXX11<"intel", "singlepump">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar, Field], ErrorDiag>; let LangOpts = [SYCLIsDevice, SYCLIsHost]; @@ -1857,7 +1870,8 @@ def IntelFPGASinglePump : Attr { } def IntelFPGAMemory : Attr { - let Spellings = [CXX11<"intelfpga", "memory">]; + let Spellings = [CXX11<"intelfpga", "memory">, + CXX11<"intel", "fpga_memory">]; let Args = [EnumArgument<"Kind", "MemoryKind", ["MLAB", "BLOCK_RAM", ""], ["MLAB", "BlockRAM", "Default"], 1>]; @@ -1877,7 +1891,8 @@ def IntelFPGAMemory : Attr { } def IntelFPGARegister : Attr { - let Spellings = [CXX11<"intelfpga", "register">]; + let Spellings = [CXX11<"intelfpga", "register">, + CXX11<"intel", "fpga_register">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar, Field], ErrorDiag>; let LangOpts = [SYCLIsDevice, SYCLIsHost]; @@ -1886,7 +1901,8 @@ def IntelFPGARegister : Attr { // One integral argument. def IntelFPGABankWidth : Attr { - let Spellings = [CXX11<"intelfpga","bankwidth">]; + let Spellings = [CXX11<"intelfpga","bankwidth">, + CXX11<"intel","bankwidth">]; let Args = [ExprArgument<"Value">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; @@ -1903,7 +1919,8 @@ def IntelFPGABankWidth : Attr { } def IntelFPGANumBanks : Attr { - let Spellings = [CXX11<"intelfpga","numbanks">]; + let Spellings = [CXX11<"intelfpga","numbanks">, + CXX11<"intel","numbanks">]; let Args = [ExprArgument<"Value">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; @@ -1920,7 +1937,8 @@ def IntelFPGANumBanks : Attr { } def IntelFPGAPrivateCopies : InheritableAttr { - let Spellings = [CXX11<"intelfpga","private_copies">]; + let Spellings = [CXX11<"intelfpga","private_copies">, + CXX11<"intel","private_copies">]; let Args = [ExprArgument<"Value">]; let LangOpts = [SYCLIsDevice, SYCLIsHost]; let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>; @@ -1937,7 +1955,8 @@ def IntelFPGAPrivateCopies : InheritableAttr { // Two string arguments. def IntelFPGAMerge : Attr { - let Spellings = [CXX11<"intelfpga","merge">]; + let Spellings = [CXX11<"intelfpga","merge">, + CXX11<"intel","merge">]; let Args = [StringArgument<"Name">, StringArgument<"Direction">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar, Field], ErrorDiag>; @@ -1946,7 +1965,8 @@ def IntelFPGAMerge : Attr { } def IntelFPGAMaxReplicates : Attr { - let Spellings = [CXX11<"intelfpga","max_replicates">]; + let Spellings = [CXX11<"intelfpga","max_replicates">, + CXX11<"intel","max_replicates">]; let Args = [ExprArgument<"Value">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; @@ -1963,7 +1983,8 @@ def IntelFPGAMaxReplicates : Attr { } def IntelFPGASimpleDualPort : Attr { - let Spellings = [CXX11<"intelfpga","simple_dual_port">]; + let Spellings = [CXX11<"intelfpga","simple_dual_port">, + CXX11<"intel","simple_dual_port">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; let LangOpts = [SYCLIsDevice, SYCLIsHost]; @@ -1988,7 +2009,8 @@ def SYCLIntelPipeIO : Attr { // Variadic integral arguments. def IntelFPGABankBits : Attr { - let Spellings = [CXX11<"intelfpga", "bank_bits">]; + let Spellings = [CXX11<"intelfpga", "bank_bits">, + CXX11<"intel", "bank_bits">]; let Args = [VariadicExprArgument<"Args">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; @@ -2005,7 +2027,8 @@ def IntelFPGABankBits : Attr { } def IntelFPGAForcePow2Depth : Attr { - let Spellings = [CXX11<"intelfpga","force_pow2_depth">]; + let Spellings = [CXX11<"intelfpga","force_pow2_depth">, + CXX11<"intel","force_pow2_depth">]; let Args = [ExprArgument<"Value">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index f9bb41bf0635a..6f89749f9d062 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -1860,7 +1860,7 @@ as ``-mlong-calls`` and ``-mno-long-calls``. def IntelFPGADoublePumpAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "doublepump (IntelFPGA)"; + let Heading = "intel::doublepump"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to implement the variable or struct member in a memory @@ -1870,7 +1870,7 @@ that is clocked at twice the rate of its accessors. def IntelFPGASinglePumpAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "singlepump (IntelFPGA)"; + let Heading = "intel::singlepump"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to implement the variable or struct member in a memory @@ -1880,7 +1880,7 @@ that is clocked at the same rate as its accessors. def IntelFPGAMemoryAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "memory (IntelFPGA)"; + let Heading = "intel::fpga_memory"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to implement the variable or struct member in memory @@ -1891,7 +1891,7 @@ it indicates what type of memory to use. def IntelFPGARegisterAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "register (IntelFPGA)"; + let Heading = "intel::fpga_register"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to promote the variable or struct member to register(s) @@ -1901,7 +1901,7 @@ if possible. def IntelFPGABankWidthAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "bankwidth (IntelFPGA)"; + let Heading = "intel::bankwidth"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to implement the variable or struct member in a memory @@ -1911,7 +1911,7 @@ with banks that are N bytes wide. def IntelFPGANumBanksAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "numbanks (IntelFPGA)"; + let Heading = "intel::numbanks"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to implement the variable or struct member in a memory @@ -1921,7 +1921,7 @@ with N banks. def IntelFPGAPrivateCopiesAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "private_copies (IntelFPGA)"; + let Heading = "intel::private_copies"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to replicate the memory generated for the variable or @@ -1932,7 +1932,7 @@ threads or loop iterations. def IntelFPGAMergeAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "merge (IntelFPGA)"; + let Heading = "intel::merge"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to merge the memories used to implement any variable or @@ -1944,7 +1944,7 @@ depth-wise or width-wise manner. def IntelFPGAMaxReplicatesAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "max_replicates (IntelFPGA)"; + let Heading = "intel::max_replicates"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to replicate the memory generated for the variable or @@ -1955,7 +1955,7 @@ simultaneous accesses from different load/store sites in the program. def IntelFPGASimpleDualPortAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "simple_dual_port (IntelFPGA)"; + let Heading = "intel::simple_dual_port"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to implement the variable or struct member in a memory @@ -1966,7 +1966,7 @@ loads). def IntelFPGABankBitsDocs : Documentation { let Category = DocCatVariable; - let Heading = "bank_bits (IntelFPGA)"; + let Heading = "intel::bank_bits"; let Content = [{ This attribute may be attached to a variable or struct member declaration and instructs the backend to implement the variable or struct member in a banked @@ -1977,7 +1977,7 @@ pointer address bits to bank on. def IntelFPGAForcePow2DepthAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "force_pow2_depth (IntelFPGA)"; + let Heading = "intel::force_pow2_depth"; let Content = [{ This attribute may be attached to a variable or struct member declaration and provides explicit control over the geometry of memory blocks used in a given @@ -2034,11 +2034,11 @@ function, and no effect otherwise. def SYCLIntelNumSimdWorkItemsAttrDocs : Documentation { let Category = DocCatFunction; - let Heading = "num_simd_work_items (IntelFPGA)"; + let Heading = "intel::num_simd_work_items"; let Content = [{ Applies to a device function/lambda function. Indicates the number of work items that should be processed in parallel. Valid values are positive integers. -If ``intelfpga::num_simd_work_items`` is applied to a function called from a +If ``intel::num_simd_work_items`` is applied to a function called from a device kernel, the attribute is ignored and it is not propagated to a kernel. }]; } @@ -2075,36 +2075,36 @@ In OpenCL C, this attribute is available in GNU spelling def SYCLIntelMaxWorkGroupSizeAttrDocs : Documentation { let Category = DocCatFunction; - let Heading = "max_work_group_size (IntelFPGA)"; + let Heading = "intel::max_work_group_size"; let Content = [{ Applies to a device function/lambda function. Indicates the maximum dimensions of a work group. Values must be positive integers. This is similar to reqd_work_group_size, but allows work groups that are smaller or equal to the specified sizes. -If ``intelfpga::max_work_group_size`` is applied to a function called from a +If ``intel::max_work_group_size`` is applied to a function called from a device kernel, the attribute is ignored and it is not propagated to a kernel. }]; } def SYCLIntelMaxGlobalWorkDimAttrDocs : Documentation { let Category = DocCatFunction; - let Heading = "max_global_work_dim (IntelFPGA)"; + let Heading = "intel::max_global_work_dim"; let Content = [{ Applies to a device function/lambda function or function call operator (of a function object). Indicates the largest valid global work dimension that will be accepted when running the kernel on a device. Valid values are integers in a range of [0, 3]. A kernel with max_global_work_dim(0) must be invoked with a -'single_task' and if ``intelfpga::max_work_group_size`` or +'single_task' and if ``intel::max_work_group_size`` or ``cl::reqd_work_group_size`` are applied to the kernel as well - they shall have arguments of (1, 1, 1). -If ``intelfpga::max_global_work_dim`` is applied to a function called from a +If ``intel::max_global_work_dim`` is applied to a function called from a device kernel, the attribute is ignored and it is not propagated to a kernel. }]; } def SYCLIntelNoGlobalWorkOffsetAttrDocs : Documentation { let Category = DocCatFunction; - let Heading = "no_global_work_offset (IntelFPGA)"; + let Heading = "intel::no_global_work_offset"; let Content = [{ Applies to a device function/lambda function or function call operator (of a function object). If 1, compiler doesn't use the global work offset values for @@ -2139,7 +2139,7 @@ with which a pipe interfaces. The id argument is the name of the I/O interface. def SYCLIntelFPGAIVDepAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "ivdep"; + let Heading = "intel::ivdep"; let Content = [{ This attribute applies to a loop. If no additional arguments are provided, it indicates that the backend may assume that the loop carries no dependences. @@ -2161,7 +2161,7 @@ the no-array ivdep's safelen, with the correspondent treatment by the backend. def SYCLIntelFPGAIIAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "ii"; + let Heading = "intel::ii"; let Content = [{ This attribute applies to a loop. Indicates that the loop should be pipelined with an initiation interval of N. N must be a positive integer. Cannot be @@ -2171,7 +2171,7 @@ applied multiple times to the same loop. def SYCLIntelFPGAMaxConcurrencyAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "max_concurrency"; + let Heading = "intel::max_concurrency"; let Content = [{ This attribute applies to a loop. Indicates that the loop should allow no more than N threads or iterations to execute it simultaneously. N must be a non @@ -2182,7 +2182,7 @@ be applied multiple times to the same loop. def SYCLIntelFPGALoopCoalesceAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "loop_coalesce"; + let Heading = "intel::loop_coalesce"; let Content = [{ This attribute applies to a loop. Indicates that the loop nest should be coalesced into a single loop without affecting functionality. Parameter N is @@ -2193,7 +2193,7 @@ of the nested loop levels should be coalesced. def SYCLIntelFPGADisableLoopPipeliningAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "disable_loop_pipelining"; + let Heading = "intel::disable_loop_pipelining"; let Content = [{ This attribute applies to a loop. Disables pipelining of the loop data path, causing the loop to be executed serially. Cannot be used on the same loop in @@ -2204,7 +2204,7 @@ or ivdep. def SYCLIntelFPGAMaxInterleavingAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "max_interleaving"; + let Heading = "intel::max_interleaving"; let Content = [{ This attribute applies to a loop. Places a maximum limit N on the number of interleaved invocations of an inner loop by an outer loop (note, this does not @@ -2217,7 +2217,7 @@ used on the same loop in conjunction with disable_loop_pipelining. def SYCLIntelFPGASpeculatedIterationsAttrDocs : Documentation { let Category = DocCatVariable; - let Heading = "speculated_iterations"; + let Heading = "intel::speculated_iterations"; let Content = [{ This attribute applies to a loop. Specifies the number of concurrent speculated iterations that will be in flight for a loop invocation (i.e. the exit diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index eedd3cd677ccd..de9a5fccca4b3 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -11073,6 +11073,11 @@ def err_ivdep_declrefexpr_arg : Error< def warn_ivdep_redundant : Warning <"ignoring redundant Intel FPGA loop " "attribute 'ivdep': safelen %select{INF|%1}0 >= safelen %select{INF|%3}2">, InGroup; +def warn_attribute_spelling_deprecated : Warning< + "attribute %0 is deprecated">, + InGroup; +def note_spelling_suggestion : Note< + "did you mean to use %0 instead?">; // errors of expect.with.probability def err_probability_not_constant_float : Error< diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index f3b9fb4023b87..b7c79732e69d7 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -318,6 +318,14 @@ static bool checkAttrMutualExclusion(Sema &S, Decl *D, const Attr &AL) { return false; } +static bool checkDeprecatedSYCLAttributeSpelling(Sema &S, + const ParsedAttr &Attr) { + if (Attr.getScopeName()->isStr("intelfpga")) + return S.Diag(Attr.getLoc(), diag::warn_attribute_spelling_deprecated) + << "'" + Attr.getNormalizedFullName() + "'"; + return false; +} + /// Check if IdxExpr is a valid parameter index for a function or /// instance method D. May output an error. /// @@ -2924,6 +2932,12 @@ static bool checkWorkGroupSizeValues(Sema &S, Decl *D, const ParsedAttr &Attr, Result &= false; } } + + if (Attr.getKind() == ParsedAttr::AT_SYCLIntelMaxWorkGroupSize && + checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::max_work_group_size'"; + if (const auto *A = D->getAttr()) { if (!(WGSize[0] >= A->getXDim() && WGSize[1] >= A->getYDim() && WGSize[2] >= A->getZDim())) { @@ -3002,6 +3016,10 @@ static void handleNumSimdWorkItemsAttr(Sema &S, Decl *D, if (D->getAttr()) S.Diag(Attr.getLoc(), diag::warn_duplicate_attribute) << Attr; + if (checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::num_simd_work_items'"; + S.addIntelSYCLSingleArgFunctionAttr(D, Attr, E); } @@ -3031,10 +3049,13 @@ static void handleMaxGlobalWorkDimAttr(Sema &S, Decl *D, return; } } - if (D->getAttr()) S.Diag(Attr.getLoc(), diag::warn_duplicate_attribute) << Attr; + if (checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::max_global_work_dim'"; + D->addAttr(::new (S.Context) SYCLIntelMaxGlobalWorkDimAttr( S.Context, Attr, MaxGlobalWorkDim)); } @@ -5168,6 +5189,11 @@ static void handleNoGlobalWorkOffsetAttr(Sema &S, Decl *D, S.Diag(Attr.getLoc(), diag::warn_boolean_attribute_argument_is_not_valid) << Attr; + if (Attr.getKind() == ParsedAttr::AT_SYCLIntelNoGlobalWorkOffset && + checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::no_global_work_offset'"; + D->addAttr(::new (S.Context) SYCLIntelNoGlobalWorkOffsetAttr(S.Context, Attr, Enabled)); } @@ -5192,6 +5218,15 @@ static void handleIntelFPGAPumpAttr(Sema &S, Decl *D, const ParsedAttr &Attr) { D->addAttr(IntelFPGAMemoryAttr::CreateImplicit( S.Context, IntelFPGAMemoryAttr::Default)); + if (Attr.getKind() == ParsedAttr::AT_IntelFPGADoublePump && + checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::doublepump'"; + else if (Attr.getKind() == ParsedAttr::AT_IntelFPGASinglePump && + checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::singlepump'"; + handleSimpleAttribute(S, D, Attr); } @@ -5229,6 +5264,10 @@ static void handleIntelFPGAMemoryAttr(Sema &S, Decl *D, if (MA->isImplicit()) D->dropAttr(); + if (checkDeprecatedSYCLAttributeSpelling(S, AL)) + S.Diag(AL.getLoc(), diag::note_spelling_suggestion) + << "'intel::fpga_memory'"; + D->addAttr(::new (S.Context) IntelFPGAMemoryAttr(S.Context, AL, Kind)); } @@ -5279,6 +5318,10 @@ static void handleIntelFPGARegisterAttr(Sema &S, Decl *D, if (checkIntelFPGARegisterAttrCompatibility(S, D, Attr)) return; + if (checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::fpga_register'"; + handleSimpleAttribute(S, D, Attr); } @@ -5298,6 +5341,15 @@ static void handleOneConstantPowerTwoValueAttr(Sema &S, Decl *D, if (checkAttrMutualExclusion(S, D, Attr)) return; + if (Attr.getKind() == ParsedAttr::AT_IntelFPGABankWidth && + checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::bankwidth'"; + else if (Attr.getKind() == ParsedAttr::AT_IntelFPGANumBanks && + checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::numbanks'"; + S.AddOneConstantPowerTwoValueAttr(D, Attr, Attr.getArgAsExpr(0)); } @@ -5315,6 +5367,10 @@ static void handleIntelFPGASimpleDualPortAttr(Sema &S, Decl *D, D->addAttr(IntelFPGAMemoryAttr::CreateImplicit( S.Context, IntelFPGAMemoryAttr::Default)); + if (checkDeprecatedSYCLAttributeSpelling(S, AL)) + S.Diag(AL.getLoc(), diag::note_spelling_suggestion) + << "'intel::simple_dual_port'"; + D->addAttr(::new (S.Context) IntelFPGASimpleDualPortAttr(S.Context, AL)); } @@ -5329,6 +5385,10 @@ static void handleIntelFPGAMaxReplicatesAttr(Sema &S, Decl *D, if (checkAttrMutualExclusion(S, D, Attr)) return; + if (checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::max_replicates'"; + S.AddOneConstantValueAttr(D, Attr, Attr.getArgAsExpr(0)); } @@ -5363,6 +5423,9 @@ static void handleIntelFPGAMergeAttr(Sema &S, Decl *D, const ParsedAttr &AL) { D->addAttr(IntelFPGAMemoryAttr::CreateImplicit( S.Context, IntelFPGAMemoryAttr::Default)); + if (checkDeprecatedSYCLAttributeSpelling(S, AL)) + S.Diag(AL.getLoc(), diag::note_spelling_suggestion) << "'intel::merge'"; + D->addAttr(::new (S.Context) IntelFPGAMergeAttr(S.Context, AL, Results[0], Results[1])); } @@ -5390,6 +5453,10 @@ static void handleIntelFPGABankBitsAttr(Sema &S, Decl *D, Args.push_back(Attr.getArgAsExpr(I)); } + if (checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::bank_bits'"; + S.AddIntelFPGABankBitsAttr(D, Attr, Args.data(), Args.size()); } @@ -5463,6 +5530,10 @@ static void handleIntelFPGAPrivateCopiesAttr(Sema &S, Decl *D, if (checkAttrMutualExclusion(S, D, Attr)) return; + if (checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::private_copies'"; + S.AddOneConstantValueAttr( D, Attr, Attr.getArgAsExpr(0)); } @@ -5481,6 +5552,10 @@ static void handleIntelFPGAForcePow2DepthAttr(Sema &S, Decl *D, D->addAttr(IntelFPGAMemoryAttr::CreateImplicit( S.Context, IntelFPGAMemoryAttr::Default)); + if (checkDeprecatedSYCLAttributeSpelling(S, Attr)) + S.Diag(Attr.getLoc(), diag::note_spelling_suggestion) + << "'intel::force_pow2_depth'"; + S.AddOneConstantValueAttr(D, Attr, Attr.getArgAsExpr(0)); } diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp index a0b6550136f92..8a169f8585365 100644 --- a/clang/lib/Sema/SemaStmtAttr.cpp +++ b/clang/lib/Sema/SemaStmtAttr.cpp @@ -74,6 +74,14 @@ static Attr *handleSuppressAttr(Sema &S, Stmt *St, const ParsedAttr &A, S.Context, A, DiagnosticIdentifiers.data(), DiagnosticIdentifiers.size()); } +static bool checkDeprecatedSYCLLoopAttributeSpelling(Sema &S, + const ParsedAttr &A) { + if (A.getScopeName()->isStr("intelfpga")) + return S.Diag(A.getLoc(), diag::warn_attribute_spelling_deprecated) + << "'" + A.getNormalizedFullName() + "'"; + return false; +} + template static Attr *handleIntelFPGALoopAttr(Sema &S, const ParsedAttr &A) { if(S.LangOpts.SYCLIsHost) @@ -95,6 +103,31 @@ static Attr *handleIntelFPGALoopAttr(Sema &S, const ParsedAttr &A) { } } + if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGAII && + checkDeprecatedSYCLLoopAttributeSpelling(S, A)) { + S.Diag(A.getLoc(), diag::note_spelling_suggestion) << "'intel::ii'"; + } else if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGAMaxConcurrency && + checkDeprecatedSYCLLoopAttributeSpelling(S, A)) { + S.Diag(A.getLoc(), diag::note_spelling_suggestion) + << "'intel::max_concurrency'"; + } else if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGAMaxConcurrency && + checkDeprecatedSYCLLoopAttributeSpelling(S, A)) { + S.Diag(A.getLoc(), diag::note_spelling_suggestion) + << "'intel::max_concurrency'"; + } else if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGAMaxInterleaving && + checkDeprecatedSYCLLoopAttributeSpelling(S, A)) { + S.Diag(A.getLoc(), diag::note_spelling_suggestion) + << "'intel::max_interleaving'"; + } else if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGASpeculatedIterations && + checkDeprecatedSYCLLoopAttributeSpelling(S, A)) { + S.Diag(A.getLoc(), diag::note_spelling_suggestion) + << "'intel::speculated_iterations'"; + } else if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGALoopCoalesce && + checkDeprecatedSYCLLoopAttributeSpelling(S, A)) { + S.Diag(A.getLoc(), diag::note_spelling_suggestion) + << "'intel::loop_coalesce'"; + } + return S.BuildSYCLIntelFPGALoopAttr( A, A.getNumArgs() ? A.getArgAsExpr(0) : nullptr); } @@ -111,6 +144,10 @@ Attr *handleIntelFPGALoopAttr( return nullptr; } + if (checkDeprecatedSYCLLoopAttributeSpelling(S, A)) + S.Diag(A.getLoc(), diag::note_spelling_suggestion) + << "'intel::disable_loop_pipelining'"; + return new (S.Context) SYCLIntelFPGADisableLoopPipeliningAttr(S.Context, A); } @@ -272,6 +309,9 @@ static Attr *handleIntelFPGAIVDepAttr(Sema &S, const ParsedAttr &A) { return nullptr; } + if (checkDeprecatedSYCLLoopAttributeSpelling(S, A)) + S.Diag(A.getLoc(), diag::note_spelling_suggestion) << "'intel::ivdep'"; + return S.BuildSYCLIntelFPGAIVDepAttr( A, NumArgs >= 1 ? A.getArgAsExpr(0) : nullptr, NumArgs == 2 ? A.getArgAsExpr(1) : nullptr); diff --git a/clang/test/CodeGenSYCL/intel-fpga-ivdep-array.cpp b/clang/test/CodeGenSYCL/intel-fpga-ivdep-array.cpp index a59d4733e59c3..1bf92431c530d 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-ivdep-array.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-ivdep-array.cpp @@ -8,8 +8,7 @@ void ivdep_array_no_safelen() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep(a)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(a)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_ARR:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}{{[[:space:]]}} @@ -25,8 +24,7 @@ void ivdep_array_with_safelen() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep(a, 5)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(a, 5)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_ARR_SAFELEN:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}{{[[:space:]]}} @@ -47,11 +45,10 @@ void ivdep_multiple_arrays() { int c[10]; // CHECK: %[[ARRAY_D:[0-9a-z]+]] = alloca [10 x i32] int d[10]; - [[intelfpga::ivdep(a, 5)]] - [[intelfpga::ivdep(b, 5)]] - [[intelfpga::ivdep(c)]] - [[intelfpga::ivdep(d)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(a, 5)]] + [[intel::ivdep(b, 5)]] + [[intel::ivdep(c)]] + [[intel::ivdep(d)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_MUL_ARR:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_MUL_ARR:[0-9]+]] @@ -72,9 +69,8 @@ void ivdep_array_and_global() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep]] - [[intelfpga::ivdep(a)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep]] + [[intel::ivdep(a)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_ARR_AND_GLOB:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_ARR_AND_GLOB:[0-9]+]] @@ -91,9 +87,8 @@ void ivdep_array_and_inf_global() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep]] - [[intelfpga::ivdep(a, 8)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep]] + [[intel::ivdep(a, 8)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_ARR_AND_INF_GLOB:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_ARR_AND_INF_GLOB:[0-9]+]] @@ -110,9 +105,8 @@ void ivdep_array_and_greater_global() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep(9)]] - [[intelfpga::ivdep(a, 8)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(9)]] + [[intel::ivdep(a, 8)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_ARR_AND_GREAT_GLOB:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_ARR_AND_GREAT_GLOB:[0-9]+]] @@ -131,10 +125,9 @@ void ivdep_mul_arrays_and_global() { int b[10]; // CHECK: %[[ARRAY_C:[0-9a-z]+]] = alloca [10 x i32] int c[10]; - [[intelfpga::ivdep(5)]] - [[intelfpga::ivdep(b, 6)]] - [[intelfpga::ivdep(c)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(5)]] + [[intel::ivdep(b, 6)]] + [[intel::ivdep(c)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_MUL_ARR_AND_GLOB:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_MUL_ARR_AND_GLOB:[0-9]+]] @@ -149,7 +142,7 @@ void ivdep_mul_arrays_and_global() { void ivdep_ptr() { int *ptr; // CHECK: %[[PTR:[0-9a-z]+]] = alloca i32 addrspace(4)* - [[intelfpga::ivdep(ptr, 5)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(ptr, 5)]] for (int i = 0; i != 10; ++i) ptr[i] = 0; // CHECK: %[[PTR_LOAD:[0-9a-z]+]] = load i32 addrspace(4)*, i32 addrspace(4)** %[[PTR]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds i32, i32 addrspace(4)* %[[PTR_LOAD]], i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_PTR:[0-9]+]] @@ -163,13 +156,13 @@ void ivdep_struct() { int arr[10]; } s; // CHECK: %[[STRUCT:[0-9a-z]+]] = alloca %struct.{{.+}}.S - [[intelfpga::ivdep(s.arr, 5)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(s.arr, 5)]] for (int i = 0; i != 10; ++i) s.arr[i] = 0; // CHECK: %[[STRUCT_ARR:[0-9a-z]+]] = getelementptr inbounds %struct.{{.+}}.S, %struct.{{.+}}.S* %[[STRUCT]], i32 0, i32 1 // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[STRUCT_ARR]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_STRUCT_ARR:[0-9]+]] // CHECK: br label %for.cond, !llvm.loop ![[MD_LOOP_STRUCT_ARR:[0-9]+]] - [[intelfpga::ivdep(s.ptr, 5)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(s.ptr, 5)]] for (int i = 0; i != 10; ++i) s.ptr[i] = 0; // CHECK: %[[STRUCT_PTR:[0-9a-z]+]] = getelementptr inbounds %struct.{{.+}}.S, %struct.{{.+}}.S* %[[STRUCT]], i32 0, i32 0 // CHECK: %[[LOAD_STRUCT_PTR:[0-9a-z]+]] = load i32 addrspace(4)*, i32 addrspace(4)** %[[STRUCT_PTR]] diff --git a/clang/test/CodeGenSYCL/intel-fpga-ivdep-embedded-loops.cpp b/clang/test/CodeGenSYCL/intel-fpga-ivdep-embedded-loops.cpp index 72434fe3480af..d19f62e19163f 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-ivdep-embedded-loops.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-ivdep-embedded-loops.cpp @@ -6,10 +6,8 @@ void ivdep_inner_loop_access() { // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32] int a[10]; - [[intelfpga::ivdep]] - for (int i = 0; i != 10; ++i) { - [[intelfpga::ivdep(3)]] - for (int j = 0; j != 10; ++j) { + [[intel::ivdep]] for (int i = 0; i != 10; ++i) { + [[intel::ivdep(3)]] for (int j = 0; j != 10; ++j) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_INNER_ACCESS:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_INNER_ACCESS]] a[i] = a[(i + j) % 10]; @@ -25,13 +23,11 @@ void ivdep_inner_loop_access() { void ivdep_embedded_global_safelen() { // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32] int a[10]; - [[intelfpga::ivdep]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_OUTER_GLOB_SFLN:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_OUTER_GLOB_SFLN]] a[i] = a[i % 2]; - [[intelfpga::ivdep]] - for (int j = 0; j != 10; ++j) { + [[intel::ivdep]] for (int j = 0; j != 10; ++j) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_INNER_GLOB_SFLN:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_INNER_GLOB_SFLN]] a[i] = a[(i + j) % 10]; @@ -47,13 +43,11 @@ void ivdep_embedded_global_safelen() { void ivdep_embedded_various_safelens() { // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32] int a[10]; - [[intelfpga::ivdep(a, 4)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(a, 4)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_OUTER_VAR_SFLN:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_OUTER_VAR_SFLN]] a[i] = a[i % 2]; - [[intelfpga::ivdep(a, 2)]] - for (int j = 0; j != 10; ++j) { + [[intel::ivdep(a, 2)]] for (int j = 0; j != 10; ++j) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_INNER_VAR_SFLN:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_INNER_VAR_SFLN]] a[i] = a[(i + j) % 10]; @@ -73,16 +67,14 @@ void ivdep_embedded_multiple_arrays() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep(a, 3), intelfpga::ivdep(b, 4)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(a, 3), intel::ivdep(b, 4)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_OUTER_MUL_ARRS:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_OUTER_MUL_ARRS]] a[i] = a[i % 2]; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_OUTER_MUL_ARRS:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_OUTER_MUL_ARRS]] b[i] = b[i % 2]; - [[intelfpga::ivdep(2)]] - for (int j = 0; j != 10; ++j) { + [[intel::ivdep(2)]] for (int j = 0; j != 10; ++j) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_INNER_MUL_ARRS:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_INNER_MUL_ARRS:[0-9]+]] a[i] = b[(i + j) % 10]; @@ -104,16 +96,14 @@ void ivdep_embedded_multiple_arrays_global() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep(a)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(a)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_OUTER_MUL_ARRS_GLOB:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_OUTER_MUL_ARRS_GLOB]] a[i] = a[i % 2]; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}{{[[:space:]]}} // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}{{[[:space:]]}} b[i] = b[i % 2]; - [[intelfpga::ivdep]] - for (int j = 0; j != 10; ++j) { + [[intel::ivdep]] for (int j = 0; j != 10; ++j) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_INNER_MUL_ARRS_GLOB:[0-9]+]] // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_INNER_MUL_ARRS_GLOB:[0-9]+]] a[i] = b[(i + j) % 10]; @@ -127,18 +117,15 @@ void ivdep_embedded_multiple_arrays_global() { // CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_embedded_multiple_dimensionsv() void ivdep_embedded_multiple_dimensions() { int a[10]; - [[intelfpga::ivdep]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_DIM_1_MUL_DIMS:[0-9]+]] a[i] = i; - [[intelfpga::ivdep]] - for (int j = 0; j != 10; ++j) { + [[intel::ivdep]] for (int j = 0; j != 10; ++j) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_DIM_2_MUL_DIMS:[0-9]+]] a[j] += j; - [[intelfpga::ivdep]] - for (int k = 0; k != 10; ++k) { - // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_DIM_3_MUL_DIMS:[0-9]+]] - a[k] += k; + [[intel::ivdep]] for (int k = 0; k != 10; ++k) { + // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_DIM_3_MUL_DIMS:[0-9]+]] + a[k] += k; // CHECK: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_LOOP_DIM_3_MUL_DIMS:[0-9]+]] } // CHECK: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_LOOP_DIM_2_MUL_DIMS:[0-9]+]] diff --git a/clang/test/CodeGenSYCL/intel-fpga-ivdep-global.cpp b/clang/test/CodeGenSYCL/intel-fpga-ivdep-global.cpp index c6a0298336136..1792b1502ec5c 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-ivdep-global.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-ivdep-global.cpp @@ -8,8 +8,7 @@ void ivdep_no_param() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_NO_PARAM:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_NO_PARAM:[0-9]+]] @@ -29,8 +28,7 @@ void ivdep_no_param_multiple_geps() { int b[10]; // CHECK: %[[TMP:[0-9a-z]+]] = alloca i32 int t; - [[intelfpga::ivdep]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_MUL_GEPS:[0-9]+]] t = a[i]; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_MUL_GEPS:[0-9]+]] @@ -50,8 +48,7 @@ void ivdep_safelen() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep(5)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(5)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_SAFELEN:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_SAFELEN:[0-9]+]] @@ -68,9 +65,8 @@ void ivdep_conflicting_safelen() { int a[10]; // CHECK: %[[ARRAY_B:[0-9a-z]+]] = alloca [10 x i32] int b[10]; - [[intelfpga::ivdep(5)]] - [[intelfpga::ivdep(4)]] - for (int i = 0; i != 10; ++i) { + [[intel::ivdep(5)]] + [[intel::ivdep(4)]] for (int i = 0; i != 10; ++i) { // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_A]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_A_CONFL_SAFELEN:[0-9]+]] a[i] = 0; // CHECK: %{{[0-9a-z]+}} = getelementptr inbounds [10 x i32], [10 x i32]* %[[ARRAY_B]], i64 0, i64 %{{[0-9a-z]+}}, !llvm.index.group ![[IDX_GROUP_B_CONFL_SAFELEN:[0-9]+]] diff --git a/clang/test/CodeGenSYCL/intel-fpga-local.cpp b/clang/test/CodeGenSYCL/intel-fpga-local.cpp index ad02d32e2aca1..55cde17b43358 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-local.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-local.cpp @@ -40,99 +40,99 @@ // CHECK-HOST-NOT: llvm.ptr.annotation void attrs_on_static() { - const static int static_numbanks [[intelfpga::numbanks(4)]] = 20; + const static int static_numbanks [[intel::numbanks(4)]] = 20; const static int static_annotate [[clang::annotate("foobar")]] = 30; - const static int static_force_p2d [[intelfpga::force_pow2_depth(0)]] = 40; + const static int static_force_p2d [[intel::force_pow2_depth(0)]] = 40; } void attrs_on_var() { // CHECK-DEVICE: %[[VAR_NUMBANKS:[0-9]+]] = bitcast{{.*}}%numbanks // CHECK-DEVICE: %[[VAR_NUMBANKS1:numbanks[0-9]+]] = bitcast{{.*}}%numbanks // CHECK-DEVICE: @llvm.var.annotation{{.*}}%[[VAR_NUMBANKS1]],{{.*}}[[ANN_numbanks_4]] - int numbanks [[intelfpga::numbanks(4)]]; + int numbanks [[intel::numbanks(4)]]; // CHECK-DEVICE: %[[VAR_REGISTER:[0-9]+]] = bitcast{{.*}}%reg // CHECK-DEVICE: %[[VAR_REGISTER1:reg[0-9]+]] = bitcast{{.*}}%reg // CHECK-DEVICE: @llvm.var.annotation{{.*}}%[[VAR_REGISTER1]],{{.*}}[[ANN_register]] - int reg [[intelfpga::register]]; + int reg [[intel::fpga_register]]; // CHECK-DEVICE: %[[VAR_MEMORY:[0-9]+]] = bitcast{{.*}}%memory // CHECK-DEVICE: %[[VAR_MEMORY1:memory[0-9]+]] = bitcast{{.*}}%memory // CHECK-DEVICE: @llvm.var.annotation{{.*}}%[[VAR_MEMORY1]],{{.*}}[[ANN_memory_default]] - int memory [[intelfpga::memory]]; + int memory [[intel::fpga_memory]]; // CHECK-DEVICE: %[[VAR_SIZE_MLAB:[0-9]+]] = bitcast{{.*}}size_mlab // CHECK-DEVICE: %[[VAR_SIZE_MLAB1:size_mlab[0-9]+]] = bitcast{{.*}}size_mlab // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_SIZE_MLAB1]],{{.*}}[[ANN_mlab_sizeinfo_500]] - [[intelfpga::memory("MLAB")]] int size_mlab[500]; + [[intel::fpga_memory("MLAB")]] int size_mlab[500]; // CHECK-DEVICE: %[[VAR_size_blockram:[0-9]+]] = bitcast{{.*}}size_blockram // CHECK-DEVICE: %[[VAR_size_blockram1:size_blockram[0-9]+]] = bitcast{{.*}}size_blockram // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_size_blockram1]],{{.*}}[[ANN_blockram_sizeinfo_10_2]] - [[intelfpga::memory("BLOCK_RAM")]] int size_blockram[10][2]; + [[intel::fpga_memory("BLOCK_RAM")]] int size_blockram[10][2]; // CHECK-DEVICE: %[[VAR_BANKWIDTH:[0-9]+]] = bitcast{{.*}}%bankwidth // CHECK-DEVICE: %[[VAR_BANKWIDTH1:bankwidth[a-z0-9]+]] = bitcast{{.*}}%bankwidth // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_BANKWIDTH1]],{{.*}}[[ANN_bankwidth_4]] - int bankwidth [[intelfpga::bankwidth(4)]]; + int bankwidth [[intel::bankwidth(4)]]; // CHECK-DEVICE: %[[VAR_PRIV_COPIES:[0-9]+]] = bitcast{{.*}}%priv_copies // CHECK-DEVICE: %[[VAR_PRIV_COPIES1:priv_copies[0-9]+]] = bitcast{{.*}}%priv_copies // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_PRIV_COPIES1]],{{.*}}[[ANN_private_copies_8]] - int priv_copies [[intelfpga::private_copies(8)]]; + int priv_copies [[intel::private_copies(8)]]; // CHECK-DEVICE: %[[VAR_SINGLEPUMP:[0-9]+]] = bitcast{{.*}}%singlepump // CHECK-DEVICE: %[[VAR_SINGLEPUMP1:singlepump[0-9]+]] = bitcast{{.*}}%singlepump // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_SINGLEPUMP1]],{{.*}}[[ANN_singlepump]] - int singlepump [[intelfpga::singlepump]]; + int singlepump [[intel::singlepump]]; // CHECK-DEVICE: %[[VAR_DOUBLEPUMP:[0-9]+]] = bitcast{{.*}}%doublepump // CHECK-DEVICE: %[[VAR_DOUBLEPUMP1:doublepump[0-9]+]] = bitcast{{.*}}%doublepump // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_DOUBLEPUMP1]],{{.*}}[[ANN_doublepump]] - int doublepump [[intelfpga::doublepump]]; + int doublepump [[intel::doublepump]]; // CHECK-DEVICE: %[[VAR_MERGE_DEPTH:[0-9]+]] = bitcast{{.*}}%merge_depth // CHECK-DEVICE: %[[VAR_MERGE_DEPTH1:merge_depth[0-9]+]] = bitcast{{.*}}%merge_depth // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_MERGE_DEPTH1]],{{.*}}[[ANN_merge_depth]] - int merge_depth [[intelfpga::merge("foo", "depth")]]; + int merge_depth [[intel::merge("foo", "depth")]]; // CHECK-DEVICE: %[[VAR_MERGE_WIDTH:[0-9]+]] = bitcast{{.*}}%merge_width // CHECK-DEVICE: %[[VAR_MERGE_WIDTH1:merge_width[0-9]+]] = bitcast{{.*}}%merge_width // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_MERGE_WIDTH1]],{{.*}}[[ANN_merge_width]] - int merge_width [[intelfpga::merge("bar", "width")]]; + int merge_width [[intel::merge("bar", "width")]]; // CHECK-DEVICE: %[[VAR_MAXREPL:[0-9]+]] = bitcast{{.*}}%max_repl // CHECK-DEVICE: %[[VAR_MAXREPL1:max_repl[0-9]+]] = bitcast{{.*}}%max_repl // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_MAXREPL1]],{{.*}}[[ANN_max_replicates_2]] - int max_repl [[intelfpga::max_replicates(2)]]; + int max_repl [[intel::max_replicates(2)]]; // CHECK-DEVICE: %[[VAR_DUALPORT:[0-9]+]] = bitcast{{.*}}%dualport // CHECK-DEVICE: %[[VAR_DUALPORT1:dualport[0-9]+]] = bitcast{{.*}}%dualport // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_DUALPORT1]],{{.*}}[[ANN_simple_dual_port]] - int dualport [[intelfpga::simple_dual_port]]; + int dualport [[intel::simple_dual_port]]; // CHECK-DEVICE: %[[VAR_BANKBITS:[0-9]+]] = bitcast{{.*}}%bankbits // CHECK-DEVICE: %[[VAR_BANKBITS1:bankbits[0-9]+]] = bitcast{{.*}}%bankbits // CHECK-DEVICE: @llvm.var.annotation{{.*}}%[[VAR_BANKBITS1]],{{.*}}[[ANN_bankbits_4_5]] - int bankbits [[intelfpga::bank_bits(4,5)]]; + int bankbits [[intel::bank_bits(4, 5)]]; // CHECK-DEVICE: %[[VAR_BANKBITS_NUMBANKS:[0-9]+]] = bitcast{{.*}}%bankbits_numbanks_mlab // CHECK-DEVICE: %[[VAR_BANKBITS_NUMBANKS1:bankbits_numbanks_mlab[0-9]+]] = bitcast{{.*}}%bankbits_numbanks_mlab // CHECK-DEVICE: @llvm.var.annotation{{.*}}%[[VAR_BANKBITS_NUMBANKS1]],{{.*}}[[ANN_bankbits_numbanks_mlab]] - [[intelfpga::bank_bits(5,4,3), intelfpga::numbanks(8), intelfpga::memory("MLAB")]] int bankbits_numbanks_mlab; + [[intel::bank_bits(5, 4, 3), intel::numbanks(8), intel::fpga_memory("MLAB")]] int bankbits_numbanks_mlab; // CHECK-DEVICE: %[[VAR_BANK_BITS_WIDTH:[0-9]+]] = bitcast{{.*}}%bank_bits_width // CHECK-DEVICE: %[[VAR_BANK_BITS_WIDTH1:bank_bits_width[0-9]+]] = bitcast{{.*}}%bank_bits_width // CHECK-DEVICE: @llvm.var.annotation{{.*}}%[[VAR_BANK_BITS_WIDTH1]],{{.*}}[[ANN_bankbits_bankwidth]] - [[intelfpga::bank_bits(0), intelfpga::bankwidth(16)]] int bank_bits_width[10][2]; + [[intel::bank_bits(0), intel::bankwidth(16)]] int bank_bits_width[10][2]; // CHECK-DEVICE: %[[VAR_FP2D:[0-9]+]] = bitcast{{.*}}%force_p2d // CHECK-DEVICE: %[[VAR_FP2D1:force_p2d[0-9]+]] = bitcast{{.*}}%force_p2d // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[VAR_FP2D1]],{{.*}}[[ANN_force_pow2_depth_0]] - int force_p2d [[intelfpga::force_pow2_depth(0)]]; + int force_p2d [[intel::force_pow2_depth(0)]]; } void attrs_on_struct() { struct attrs_on_struct { - int numbanks [[intelfpga::numbanks(4)]] ; - int reg [[intelfpga::register]]; - int memory [[intelfpga::memory]]; - int memory_blockram [[intelfpga::memory("BLOCK_RAM")]]; - int memory_mlab [[intelfpga::memory("MLAB")]]; - int bankwidth [[intelfpga::bankwidth(4)]]; - int privatecopies [[intelfpga::private_copies(8)]]; - int singlepump [[intelfpga::singlepump]]; - int doublepump [[intelfpga::doublepump]]; - int merge_depth [[intelfpga::merge("foo", "depth")]]; - int merge_width [[intelfpga::merge("bar", "width")]]; - int maxreplicates [[intelfpga::max_replicates(2)]]; - int dualport [[intelfpga::simple_dual_port]]; - int bankbits [[intelfpga::bank_bits(4, 5)]]; - int force_p2d [[intelfpga::force_pow2_depth(1)]]; + int numbanks [[intel::numbanks(4)]]; + int reg [[intel::fpga_register]]; + int memory [[intel::fpga_memory]]; + int memory_blockram [[intel::fpga_memory("BLOCK_RAM")]]; + int memory_mlab [[intel::fpga_memory("MLAB")]]; + int bankwidth [[intel::bankwidth(4)]]; + int privatecopies [[intel::private_copies(8)]]; + int singlepump [[intel::singlepump]]; + int doublepump [[intel::doublepump]]; + int merge_depth [[intel::merge("foo", "depth")]]; + int merge_width [[intel::merge("bar", "width")]]; + int maxreplicates [[intel::max_replicates(2)]]; + int dualport [[intel::simple_dual_port]]; + int bankbits [[intel::bank_bits(4, 5)]]; + int force_p2d [[intel::force_pow2_depth(1)]]; } s; // CHECK-DEVICE: %[[FIELD_NUMBANKS:.*]] = getelementptr inbounds %struct.{{.*}}.attrs_on_struct{{.*}} @@ -189,30 +189,30 @@ template void attrs_with_template_param() { // CHECK-DEVICE: %[[TEMPL_NUMBANKS:numbanks[0-9]+]] = bitcast{{.*}}%numbanks // CHECK-DEVICE: @llvm.var.annotation{{.*}}%[[TEMPL_NUMBANKS]],{{.*}}[[ANN_numbanks_4]] - int numbanks [[intelfpga::numbanks(A)]]; + int numbanks [[intel::numbanks(A)]]; // CHECK-DEVICE: %[[TEMPL_BANKWIDTH:bankwidth[a-z0-9]+]] = bitcast{{.*}}%bankwidth // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[TEMPL_BANKWIDTH]],{{.*}}[[ANN_bankwidth_4]] - int bankwidth [[intelfpga::bankwidth(A)]]; + int bankwidth [[intel::bankwidth(A)]]; // CHECK-DEVICE: %[[TEMPL_PRIV_COPIES:priv_copies[0-9]+]] = bitcast{{.*}}%priv_copies // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[TEMPL_PRIV_COPIES]],{{.*}}[[ANN_private_copies_4]] - int priv_copies [[intelfpga::private_copies(A)]]; + int priv_copies [[intel::private_copies(A)]]; // CHECK-DEVICE: %[[TEMPL_MAXREPL:max_repl[0-9]+]] = bitcast{{.*}}%max_repl // CHECK-DEVICE: llvm.var.annotation{{.*}}%[[TEMPL_MAXREPL]],{{.*}}[[ANN_max_replicates_4]] - int max_repl [[intelfpga::max_replicates(A)]]; + int max_repl [[intel::max_replicates(A)]]; // CHECK-DEVICE: %[[TEMPL_BANKBITS:bankbits[0-9]+]] = bitcast{{.*}}%bankbits // CHECK-DEVICE: @llvm.var.annotation{{.*}}%[[TEMPL_BANKBITS]],{{.*}}[[ANN_bankbits_4_5]] - int bankbits [[intelfpga::bank_bits(A, B)]]; + int bankbits [[intel::bank_bits(A, B)]]; // CHECK-DEVICE: %[[TEMPL_FP2D:force_p2d[0-9]+]] = bitcast{{.*}}%force_p2d // CHECK-DEVICE: @llvm.var.annotation{{.*}}%[[TEMPL_FP2D]]{{.*}}[[ANN_force_pow2_depth_1]] - int force_p2d [[intelfpga::force_pow2_depth(C)]]; + int force_p2d [[intel::force_pow2_depth(C)]]; struct templ_on_struct_fields { - int numbanks [[intelfpga::numbanks(A)]] ; - int bankwidth [[intelfpga::bankwidth(A)]]; - int privatecopies [[intelfpga::private_copies(A)]]; - int maxreplicates [[intelfpga::max_replicates(A)]]; - int bankbits [[intelfpga::bank_bits(A, B)]]; - int force_p2d [[intelfpga::force_pow2_depth(C)]]; + int numbanks [[intel::numbanks(A)]]; + int bankwidth [[intel::bankwidth(A)]]; + int privatecopies [[intel::private_copies(A)]]; + int maxreplicates [[intel::max_replicates(A)]]; + int bankbits [[intel::bank_bits(A, B)]]; + int force_p2d [[intel::force_pow2_depth(C)]]; } s; // CHECK-DEVICE: %[[FIELD_NUMBANKS:.*]] = getelementptr inbounds %struct.{{.*}}.templ_on_struct_fields{{.*}} @@ -237,7 +237,7 @@ void attrs_with_template_param() { void field_addrspace_cast() { struct state { - [[intelfpga::numbanks(2)]] int mem[8]; + [[intel::numbanks(2)]] int mem[8]; // The initialization code is not relevant to this example. // It prevents the compiler from optimizing away access to this struct. diff --git a/clang/test/CodeGenSYCL/intel-fpga-loops.cpp b/clang/test/CodeGenSYCL/intel-fpga-loops.cpp index ce7fb46b9c66c..f9f01bb3c02a1 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-loops.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-loops.cpp @@ -17,7 +17,7 @@ void disable_loop_pipelining() { int a[10]; // CHECK: ![[MD_DLP]] = distinct !{![[MD_DLP]], ![[MD_dlp:[0-9]+]]} // CHECK-NEXT: ![[MD_dlp]] = !{!"llvm.loop.intel.pipelining.enable", i32 0} - [[intelfpga::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) + [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) a[i] = 0; } @@ -26,14 +26,12 @@ void ii() { int a[10]; // CHECK: ![[MD_II]] = distinct !{![[MD_II]], ![[MD_ii_count:[0-9]+]]} // CHECK-NEXT: ![[MD_ii_count]] = !{!"llvm.loop.ii.count", i32 4} - [[intelfpga::ii(A)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ii(A)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // CHECK: ![[MD_II_2]] = distinct !{![[MD_II_2]], ![[MD_ii_count_2:[0-9]+]]} // CHECK-NEXT: ![[MD_ii_count_2]] = !{!"llvm.loop.ii.count", i32 8} - [[intelfpga::ii(8)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ii(8)]] for (int i = 0; i != 10; ++i) + a[i] = 0; } template @@ -41,14 +39,12 @@ void max_concurrency() { int a[10]; // CHECK: ![[MD_MC]] = distinct !{![[MD_MC]], ![[MD_max_concurrency:[0-9]+]]} // CHECK-NEXT: ![[MD_max_concurrency]] = !{!"llvm.loop.max_concurrency.count", i32 0} - [[intelfpga::max_concurrency(A)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::max_concurrency(A)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // CHECK: ![[MD_MC_2]] = distinct !{![[MD_MC_2]], ![[MD_max_concurrency_2:[0-9]+]]} // CHECK-NEXT: ![[MD_max_concurrency_2]] = !{!"llvm.loop.max_concurrency.count", i32 4} - [[intelfpga::max_concurrency(4)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::max_concurrency(4)]] for (int i = 0; i != 10; ++i) + a[i] = 0; } template @@ -56,15 +52,15 @@ void loop_coalesce() { int a[10]; // CHECK: ![[MD_LC]] = distinct !{![[MD_LC]], ![[MD_loop_coalesce:[0-9]+]]} // CHECK-NEXT: ![[MD_loop_coalesce]] = !{!"llvm.loop.coalesce.count", i32 2} - [[intelfpga::loop_coalesce(A)]] for (int i = 0; i != 10; ++i) + [[intel::loop_coalesce(A)]] for (int i = 0; i != 10; ++i) a[i] = 0; // CHECK: ![[MD_LC_2]] = distinct !{![[MD_LC_2]], ![[MD_loop_coalesce_2:[0-9]+]]} // CHECK-NEXT: ![[MD_loop_coalesce_2]] = !{!"llvm.loop.coalesce.count", i32 4} - [[intelfpga::loop_coalesce(4)]] for (int i = 0; i != 10; ++i) + [[intel::loop_coalesce(4)]] for (int i = 0; i != 10; ++i) a[i] = 0; // CHECK: ![[MD_LC_3]] = distinct !{![[MD_LC_3]], ![[MD_loop_coalesce_3:[0-9]+]]} // CHECK-NEXT: ![[MD_loop_coalesce_3]] = !{!"llvm.loop.coalesce.enable"} - [[intelfpga::loop_coalesce]] for (int i = 0; i != 10; ++i) + [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) a[i] = 0; } @@ -73,11 +69,11 @@ void max_interleaving() { int a[10]; // CHECK: ![[MD_MI]] = distinct !{![[MD_MI]], ![[MD_max_interleaving:[0-9]+]]} // CHECK-NEXT: ![[MD_max_interleaving]] = !{!"llvm.loop.max_interleaving.count", i32 3} - [[intelfpga::max_interleaving(A)]] for (int i = 0; i != 10; ++i) + [[intel::max_interleaving(A)]] for (int i = 0; i != 10; ++i) a[i] = 0; // CHECK: ![[MD_MI_2]] = distinct !{![[MD_MI_2]], ![[MD_max_interleaving_2:[0-9]+]]} // CHECK-NEXT: ![[MD_max_interleaving_2]] = !{!"llvm.loop.max_interleaving.count", i32 2} - [[intelfpga::max_interleaving(2)]] for (int i = 0; i != 10; ++i) + [[intel::max_interleaving(2)]] for (int i = 0; i != 10; ++i) a[i] = 0; } @@ -86,11 +82,11 @@ void speculated_iterations() { int a[10]; // CHECK: ![[MD_SI]] = distinct !{![[MD_SI]], ![[MD_speculated_iterations:[0-9]+]]} // CHECK-NEXT: ![[MD_speculated_iterations]] = !{!"llvm.loop.intel.speculated.iterations.count", i32 4} - [[intelfpga::speculated_iterations(A)]] for (int i = 0; i != 10; ++i) + [[intel::speculated_iterations(A)]] for (int i = 0; i != 10; ++i) a[i] = 0; // CHECK: ![[MD_SI_2]] = distinct !{![[MD_SI_2]], ![[MD_speculated_iterations_2:[0-9]+]]} // CHECK-NEXT: ![[MD_speculated_iterations_2]] = !{!"llvm.loop.intel.speculated.iterations.count", i32 5} - [[intelfpga::speculated_iterations(5)]] for (int i = 0; i != 10; ++i) + [[intel::speculated_iterations(5)]] for (int i = 0; i != 10; ++i) a[i] = 0; } diff --git a/clang/test/CodeGenSYCL/intel-fpga-no-global-work-offset.cpp b/clang/test/CodeGenSYCL/intel-fpga-no-global-work-offset.cpp index 3b2ffd1cae5e4..a4d93478134a1 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-no-global-work-offset.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-no-global-work-offset.cpp @@ -2,7 +2,7 @@ class Foo { public: - [[intelfpga::no_global_work_offset(1)]] void operator()() const {} + [[intel::no_global_work_offset(1)]] void operator()() const {} }; template @@ -15,10 +15,10 @@ void bar() { kernel(boo); kernel( - []() [[intelfpga::no_global_work_offset]]{}); + []() [[intel::no_global_work_offset]]{}); kernel( - []() [[intelfpga::no_global_work_offset(0)]]{}); + []() [[intel::no_global_work_offset(0)]]{}); } // CHECK: define spir_kernel void @{{.*}}kernel_name1() {{.*}} !no_global_work_offset ![[NUM5:[0-9]+]] diff --git a/clang/test/CodeGenSYCL/intel-max-global-work-dim.cpp b/clang/test/CodeGenSYCL/intel-max-global-work-dim.cpp index 0fcd1ab014864..673f45d511502 100644 --- a/clang/test/CodeGenSYCL/intel-max-global-work-dim.cpp +++ b/clang/test/CodeGenSYCL/intel-max-global-work-dim.cpp @@ -2,7 +2,7 @@ class Foo { public: - [[intelfpga::max_global_work_dim(1)]] void operator()() const {} + [[intel::max_global_work_dim(1)]] void operator()() const {} }; template @@ -15,7 +15,7 @@ void bar() { kernel(boo); kernel( - []() [[intelfpga::max_global_work_dim(2)]] {}); + []() [[intel::max_global_work_dim(2)]]{}); } // CHECK: define spir_kernel void @{{.*}}kernel_name1() {{.*}} !max_global_work_dim ![[NUM1:[0-9]+]] diff --git a/clang/test/CodeGenSYCL/intel-max-work-group-size.cpp b/clang/test/CodeGenSYCL/intel-max-work-group-size.cpp index e9b4360701e09..87117c585e0d1 100644 --- a/clang/test/CodeGenSYCL/intel-max-work-group-size.cpp +++ b/clang/test/CodeGenSYCL/intel-max-work-group-size.cpp @@ -2,7 +2,7 @@ class Foo { public: - [[intelfpga::max_work_group_size(1, 1, 1)]] void operator()() const {} + [[intel::max_work_group_size(1, 1, 1)]] void operator()() const {} }; template @@ -15,7 +15,7 @@ void bar() { kernel(boo); kernel( - []() [[intelfpga::max_work_group_size(8, 8, 8)]] {}); + []() [[intel::max_work_group_size(8, 8, 8)]]{}); } // CHECK: define spir_kernel void @{{.*}}kernel_name1() {{.*}} !max_work_group_size ![[NUM1:[0-9]+]] diff --git a/clang/test/CodeGenSYCL/num-simd-work-items.cpp b/clang/test/CodeGenSYCL/num-simd-work-items.cpp index b88cfbf5ff917..3173971cd0ce6 100644 --- a/clang/test/CodeGenSYCL/num-simd-work-items.cpp +++ b/clang/test/CodeGenSYCL/num-simd-work-items.cpp @@ -2,13 +2,13 @@ class Foo { public: - [[intelfpga::num_simd_work_items(1)]] void operator()() const {} + [[intel::num_simd_work_items(1)]] void operator()() const {} }; template class Functor { public: - [[intelfpga::num_simd_work_items(SIZE)]] void operator()() const {} + [[intel::num_simd_work_items(SIZE)]] void operator()() const {} }; template @@ -21,7 +21,7 @@ void bar() { kernel(boo); kernel( - []() [[intelfpga::num_simd_work_items(42)]] {}); + []() [[intel::num_simd_work_items(42)]]{}); Functor<2> f; kernel(f); diff --git a/clang/test/SemaSYCL/check-notdirect-attribute-propagation.cpp b/clang/test/SemaSYCL/check-notdirect-attribute-propagation.cpp index 3dd98f12b0120..777ef128123eb 100644 --- a/clang/test/SemaSYCL/check-notdirect-attribute-propagation.cpp +++ b/clang/test/SemaSYCL/check-notdirect-attribute-propagation.cpp @@ -3,7 +3,7 @@ // RUN: %clang_cc1 %s -fsyntax-only -ast-dump -fsycl -fsycl-is-device -triple spir64 | FileCheck %s #ifndef TRIGGER_ERROR -[[intelfpga::no_global_work_offset]] void not_direct_one() {} // expected-no-diagnostics +[[intel::no_global_work_offset]] void not_direct_one() {} // expected-no-diagnostics [[intel::reqd_sub_group_size(1)]] void func_one() { not_direct_one(); @@ -12,7 +12,7 @@ #else [[cl::reqd_work_group_size(2, 2, 2)]] void not_direct_two() {} // expected-note {{conflicting attribute is here}} -[[intelfpga::max_work_group_size(1, 1, 1)]] // expected-note {{conflicting attribute is here}} +[[intel::max_work_group_size(1, 1, 1)]] // expected-note {{conflicting attribute is here}} void func_two() { not_direct_two(); diff --git a/clang/test/SemaSYCL/device-indirectly-callable-attr.cpp b/clang/test/SemaSYCL/device-indirectly-callable-attr.cpp index 7d8ff0e817983..d0ae74e5981dd 100644 --- a/clang/test/SemaSYCL/device-indirectly-callable-attr.cpp +++ b/clang/test/SemaSYCL/device-indirectly-callable-attr.cpp @@ -8,14 +8,17 @@ int N; [[intel::device_indirectly_callable(3)]] // expected-error {{'device_indirectly_callable' attribute takes no arguments}} -void bar() {} +void +bar() {} [[intel::device_indirectly_callable]] // expected-error {{'device_indirectly_callable' attribute cannot be applied to a static function or function in an anonymous namespace}} -static void func1() {} +static void +func1() {} namespace { - [[intel::device_indirectly_callable]] // expected-error {{'device_indirectly_callable' attribute cannot be applied to a static function or function in an anonymous namespace}} - void func2() {} +[[intel::device_indirectly_callable]] // expected-error {{'device_indirectly_callable' attribute cannot be applied to a static function or function in an anonymous namespace}} +void +func2() {} } class A { @@ -40,7 +43,8 @@ void foo() { #else [[intel::device_indirectly_callable]] // expected-warning {{'device_indirectly_callable' attribute ignored}} -void baz() {} +void +baz() {} #endif // NO_SYCL diff --git a/clang/test/SemaSYCL/intel-fpga-local.cpp b/clang/test/SemaSYCL/intel-fpga-local.cpp index 4d637a4a9213f..08f914f06a999 100644 --- a/clang/test/SemaSYCL/intel-fpga-local.cpp +++ b/clang/test/SemaSYCL/intel-fpga-local.cpp @@ -6,28 +6,28 @@ void check_ast() //CHECK: VarDecl{{.*}}doublepump //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit //CHECK: IntelFPGADoublePumpAttr - [[intelfpga::doublepump]] unsigned int doublepump[64]; + [[intel::doublepump]] unsigned int doublepump[64]; //CHECK: VarDecl{{.*}}memory //CHECK: IntelFPGAMemoryAttr - [[intelfpga::memory]] unsigned int memory[64]; + [[intel::fpga_memory]] unsigned int memory[64]; //CHECK: VarDecl{{.*}}memory_mlab //CHECK: IntelFPGAMemoryAttr{{.*}}MLAB - [[intelfpga::memory("MLAB")]] unsigned int memory_mlab[64]; + [[intel::fpga_memory("MLAB")]] unsigned int memory_mlab[64]; //CHECK: VarDecl{{.*}}mem_blockram //CHECK: IntelFPGAMemoryAttr{{.*}}BlockRAM - [[intelfpga::memory("BLOCK_RAM")]] unsigned int mem_blockram[32]; + [[intel::fpga_memory("BLOCK_RAM")]] unsigned int mem_blockram[32]; //CHECK: VarDecl{{.*}}reg //CHECK: IntelFPGARegisterAttr - [[intelfpga::register]] unsigned int reg[64]; + [[intel::fpga_register]] unsigned int reg[64]; //CHECK: VarDecl{{.*}}singlepump //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit //CHECK: IntelFPGASinglePumpAttr - [[intelfpga::singlepump]] unsigned int singlepump[64]; + [[intel::singlepump]] unsigned int singlepump[64]; //CHECK: VarDecl{{.*}}bankwidth //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -35,7 +35,7 @@ void check_ast() //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}4 //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}} - [[intelfpga::bankwidth(4)]] unsigned int bankwidth[32]; + [[intel::bankwidth(4)]] unsigned int bankwidth[32]; //CHECK: VarDecl{{.*}}numbanks //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -43,7 +43,7 @@ void check_ast() //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}8 //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}} - [[intelfpga::numbanks(8)]] unsigned int numbanks[32]; + [[intel::numbanks(8)]] unsigned int numbanks[32]; //CHECK: VarDecl{{.*}}private_copies //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -51,19 +51,17 @@ void check_ast() //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}8 //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}} - [[intelfpga::private_copies(8)]] unsigned int private_copies[64]; + [[intel::private_copies(8)]] unsigned int private_copies[64]; //CHECK: VarDecl{{.*}}merge_depth //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit //CHECK: IntelFPGAMergeAttr{{.*}}"mrg1" "depth"{{$}} - [[intelfpga::merge("mrg1","depth")]] - unsigned int merge_depth[64]; + [[intel::merge("mrg1", "depth")]] unsigned int merge_depth[64]; //CHECK: VarDecl{{.*}}merge_width //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit //CHECK: IntelFPGAMergeAttr{{.*}}"mrg2" "width"{{$}} - [[intelfpga::merge("mrg2","width")]] - unsigned int merge_width[64]; + [[intel::merge("mrg2", "width")]] unsigned int merge_width[64]; //CHECK: VarDecl{{.*}}bankbits //CHECK: IntelFPGANumBanksAttr{{.*}}Implicit{{$}} @@ -82,8 +80,7 @@ void check_ast() //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}5 //CHECK-NEXT: IntegerLiteral{{.*}}5{{$}} - [[intelfpga::bank_bits(2,3,4,5)]] - unsigned int bankbits[64]; + [[intel::bank_bits(2, 3, 4, 5)]] unsigned int bankbits[64]; //CHECK: VarDecl{{.*}}bank_bits_width //CHECK-NEXT: IntelFPGANumBanksAttr{{.*}}Implicit{{$}} @@ -100,29 +97,25 @@ void check_ast() //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}16 //CHECK-NEXT: IntegerLiteral{{.*}}16{{$}} - [[intelfpga::bank_bits(2,3), intelfpga::bankwidth(16)]] - unsigned int bank_bits_width[64]; + [[intel::bank_bits(2, 3), intel::bankwidth(16)]] unsigned int bank_bits_width[64]; //CHECK: VarDecl{{.*}}doublepump_mlab //CHECK: IntelFPGADoublePumpAttr //CHECK: IntelFPGAMemoryAttr{{.*}}MLAB{{$}} - [[intelfpga::doublepump]] - [[intelfpga::memory("MLAB")]] - unsigned int doublepump_mlab[64]; + [[intel::doublepump]] + [[intel::fpga_memory("MLAB")]] unsigned int doublepump_mlab[64]; //CHECK: VarDecl{{.*}}max_replicates //CHECK: IntelFPGAMaxReplicatesAttr //CHECK: ConstantExpr //CHECK-NEXT: value:{{.*}}2 //CHECK: IntegerLiteral{{.*}}2{{$}} - [[intelfpga::max_replicates(2)]] - unsigned int max_replicates[64]; + [[intel::max_replicates(2)]] unsigned int max_replicates[64]; //CHECK: VarDecl{{.*}}dual_port //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit //CHECK: IntelFPGASimpleDualPortAttr - [[intelfpga::simple_dual_port]] - unsigned int dual_port[64]; + [[intel::simple_dual_port]] unsigned int dual_port[64]; //CHECK: VarDecl{{.*}}arr_force_p2d_0 //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -130,7 +123,7 @@ void check_ast() //CHECK: ConstantExpr //CHECK-NEXT: value:{{.*}}0 //CHECK: IntegerLiteral{{.*}}0{{$}} - [[intelfpga::force_pow2_depth(0)]] unsigned int arr_force_p2d_0[64]; + [[intel::force_pow2_depth(0)]] unsigned int arr_force_p2d_0[64]; //CHECK: VarDecl{{.*}}arr_force_p2d_1 //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -138,169 +131,214 @@ void check_ast() //CHECK: ConstantExpr //CHECK-NEXT: value:{{.*}}1 //CHECK: IntegerLiteral{{.*}}1{{$}} - [[intelfpga::force_pow2_depth(1)]] unsigned int arr_force_p2d_1[64]; - - [[intelfpga::register]] int var_reg; - [[intelfpga::numbanks(4), intelfpga::bankwidth(16), intelfpga::singlepump]] int var_singlepump; - [[intelfpga::numbanks(4), intelfpga::bankwidth(16), intelfpga::doublepump]] int var_doublepump; - [[intelfpga::numbanks(4), intelfpga::bankwidth(16)]] int var_numbanks_bankwidth; - [[intelfpga::bank_bits(2,3), intelfpga::bankwidth(16)]] int var_bank_bits_width; - [[intelfpga::max_replicates(2)]] int var_max_repl; - [[intelfpga::simple_dual_port]] int var_dual_port; - [[intelfpga::force_pow2_depth(1)]] int var_force_p2d; - [[intelfpga::force_pow2_depth(1)]] const int const_force_p2d[64] = {0, 1}; + [[intel::force_pow2_depth(1)]] unsigned int arr_force_p2d_1[64]; + [[intel::fpga_register]] int var_reg; + [[intel::numbanks(4), intel::bankwidth(16), intel::singlepump]] int var_singlepump; + [[intel::numbanks(4), intel::bankwidth(16), intel::doublepump]] int var_doublepump; + [[intel::numbanks(4), intel::bankwidth(16)]] int var_numbanks_bankwidth; + [[intel::bank_bits(2, 3), intel::bankwidth(16)]] int var_bank_bits_width; + [[intel::max_replicates(2)]] int var_max_repl; + [[intel::simple_dual_port]] int var_dual_port; + [[intel::force_pow2_depth(1)]] int var_force_p2d; + [[intel::force_pow2_depth(1)]] const int const_force_p2d[64] = {0, 1}; } //CHECK: FunctionDecl{{.*}}diagnostics void diagnostics() { // **doublepump + //CHECK: VarDecl{{.*}}doublepump + //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit + //CHECK: IntelFPGADoublePumpAttr + //expected-warning@+2 {{attribute 'intelfpga::doublepump' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::doublepump' instead?}} + [[intelfpga::doublepump]] unsigned int doublepump[64]; + //expected-error@+2{{attributes are not compatible}} - [[intelfpga::doublepump]] - [[intelfpga::singlepump]] + [[intel::doublepump]] + [[intel::singlepump]] //expected-note@-2 {{conflicting attribute is here}} unsigned int dpump_spump[64]; //expected-warning@+2{{attribute 'doublepump' is already applied}} - [[intelfpga::doublepump]] - [[intelfpga::doublepump]] - unsigned int dpump[64]; + [[intel::doublepump]] + [[intel::doublepump]] unsigned int dpump[64]; //expected-error@+2{{attributes are not compatible}} - [[intelfpga::doublepump]] - [[intelfpga::register]] + [[intel::doublepump]] + [[intel::fpga_register]] //expected-note@-2 {{conflicting attribute is here}} unsigned int dpump_reg[64]; // **singlepump + //CHECK: VarDecl{{.*}}singlepump + //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit + //CHECK: IntelFPGASinglePumpAttr + //expected-warning@+2 {{attribute 'intelfpga::singlepump' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::singlepump' instead?}} + [[intelfpga::singlepump]] unsigned int singlepump[64]; + //expected-error@+1{{attributes are not compatible}} - [[intelfpga::singlepump, intelfpga::doublepump]] + [[intel::singlepump, intel::doublepump]] //expected-note@-1 {{conflicting attribute is here}} unsigned int spump_dpump[64]; //expected-warning@+2{{attribute 'singlepump' is already applied}} - [[intelfpga::singlepump]] - [[intelfpga::singlepump]] - unsigned int spump[64]; + [[intel::singlepump]] + [[intel::singlepump]] unsigned int spump[64]; //expected-error@+2{{attributes are not compatible}} - [[intelfpga::singlepump]] - [[intelfpga::register]] + [[intel::singlepump]] + [[intel::fpga_register]] //expected-note@-2 {{conflicting attribute is here}} unsigned int spump_reg[64]; - // **register - //expected-warning@+1{{attribute 'register' is already applied}} - [[intelfpga::register]] [[intelfpga::register]] - unsigned int reg_reg[64]; + // **fpga_register + //CHECK: VarDecl{{.*}}reg + //CHECK: IntelFPGARegisterAttr + //expected-warning@+2 {{attribute 'intelfpga::register' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::fpga_register' instead?}} + [[intelfpga::register]] unsigned int reg[64]; + + //expected-warning@+1{{attribute 'fpga_register' is already applied}} + [[intel::fpga_register]] [[intel::fpga_register]] unsigned int reg_reg[64]; //expected-error@+2{{attributes are not compatible}} - [[intelfpga::register]] - [[intelfpga::singlepump]] + [[intel::fpga_register]] + [[intel::singlepump]] //expected-note@-2 {{conflicting attribute is here}} unsigned int reg_spump[64]; //expected-error@+2{{attributes are not compatible}} - [[intelfpga::register]] - [[intelfpga::doublepump]] + [[intel::fpga_register]] + [[intel::doublepump]] //expected-note@-2 {{conflicting attribute is here}} unsigned int reg_dpump[64]; //expected-error@+2{{attributes are not compatible}} - [[intelfpga::register]] - [[intelfpga::memory]] + [[intel::fpga_register]] + [[intel::fpga_memory]] //expected-note@-2 {{conflicting attribute is here}} unsigned int reg_memory[64]; - //expected-error@+2{{'bank_bits' and 'register' attributes are not compatible}} - [[intelfpga::register]] - [[intelfpga::bank_bits(4,5)]] + //expected-error@+2{{'bank_bits' and 'fpga_register' attributes are not compatible}} + [[intel::fpga_register]] + [[intel::bank_bits(4, 5)]] //expected-note@-2 {{conflicting attribute is here}} unsigned int reg_bankbits[64]; - //expected-error@+2{{'bankwidth' and 'register' attributes are not compatible}} - [[intelfpga::register]] - [[intelfpga::bankwidth(16)]] + //expected-error@+2{{'bankwidth' and 'fpga_register' attributes are not compatible}} + [[intel::fpga_register]] + [[intel::bankwidth(16)]] //expected-note@-2 {{conflicting attribute is here}} unsigned int reg_bankwidth[64]; //expected-error@+2{{attributes are not compatible}} - [[intelfpga::register]] - [[intelfpga::private_copies(16)]] + [[intel::fpga_register]] + [[intel::private_copies(16)]] //expected-note@-2 {{conflicting attribute is here}} unsigned int reg_private_copies[64]; //expected-error@+2{{attributes are not compatible}} - [[intelfpga::register]] - [[intelfpga::numbanks(8)]] + [[intel::fpga_register]] + [[intel::numbanks(8)]] //expected-note@-2 {{conflicting attribute is here}} unsigned int reg_numbanks[64]; //expected-error@+2{{attributes are not compatible}} - [[intelfpga::register]] - [[intelfpga::merge("mrg1","depth")]] + [[intel::fpga_register]] + [[intel::merge("mrg1", "depth")]] //expected-note@-2 {{conflicting attribute is here}} unsigned int reg_merge[64]; - //expected-error@+3{{'max_replicates' and 'register' attributes are not compatible}} - [[intelfpga::register]] + //expected-error@+3{{'max_replicates' and 'fpga_register' attributes are not compatible}} + [[intel::fpga_register]] //expected-note@-1 {{conflicting attribute is here}} - [[intelfpga::max_replicates(2)]] unsigned int reg_maxrepl[64]; + [[intel::max_replicates(2)]] unsigned int reg_maxrepl[64]; - //expected-error@+3{{'simple_dual_port' and 'register' attributes are not compatible}} - [[intelfpga::register]] + //expected-error@+3{{'simple_dual_port' and 'fpga_register' attributes are not compatible}} + [[intel::fpga_register]] //expected-note@-1 {{conflicting attribute is here}} - [[intelfpga::simple_dual_port]] unsigned int reg_dualport[64]; + [[intel::simple_dual_port]] unsigned int reg_dualport[64]; - //expected-error@+3{{'force_pow2_depth' and 'register' attributes are not compatible}} - [[intelfpga::register]] + //expected-error@+3{{'force_pow2_depth' and 'fpga_register' attributes are not compatible}} + [[intel::fpga_register]] //expected-note@-1 {{conflicting attribute is here}} - [[intelfpga::force_pow2_depth(0)]] unsigned int reg_force_p2d[64]; + [[intel::force_pow2_depth(0)]] unsigned int reg_force_p2d[64]; - //expected-error@+3{{'register' and 'force_pow2_depth' attributes are not compatible}} - [[intelfpga::force_pow2_depth(1)]] + //expected-error@+3{{'fpga_register' and 'force_pow2_depth' attributes are not compatible}} + [[intel::force_pow2_depth(1)]] //expected-note@-1 {{conflicting attribute is here}} - [[intelfpga::register]] unsigned int force_p2d_reg[64]; + [[intel::fpga_register]] unsigned int force_p2d_reg[64]; // **memory + //CHECK: VarDecl{{.*}}memory + //CHECK: IntelFPGAMemoryAttr + //expected-warning@+2 {{attribute 'intelfpga::memory' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::fpga_memory' instead?}} + [[intelfpga::memory]] unsigned int memory[64]; + //expected-error@+2{{attributes are not compatible}} - [[intelfpga::memory]] - [[intelfpga::register]] + [[intel::fpga_memory]] + [[intel::fpga_register]] //expected-note@-2 {{conflicting attribute is here}} unsigned int mem_reg[64]; - //expected-warning@+1{{attribute 'memory' is already applied}} - [[intelfpga::memory]] [[intelfpga::memory]] - unsigned int mem_mem[64]; + //expected-warning@+1{{attribute 'fpga_memory' is already applied}} + [[intel::fpga_memory]] [[intel::fpga_memory]] unsigned int mem_mem[64]; // bankwidth + //CHECK: VarDecl{{.*}}bankwidth + //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit + //CHECK: IntelFPGABankWidthAttr + //CHECK-NEXT: ConstantExpr + //CHECK-NEXT: value:{{.*}}4 + //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}} + //expected-warning@+2 {{attribute 'intelfpga::bankwidth' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::bankwidth' instead?}} + [[intelfpga::bankwidth(4)]] unsigned int bankwidth[32]; + //expected-error@+2{{attributes are not compatible}} - [[intelfpga::bankwidth(16)]] - [[intelfpga::register]] + [[intel::bankwidth(16)]] + [[intel::fpga_register]] //expected-note@-2 {{conflicting attribute is here}} unsigned int bankwidth_reg[64]; // **max_replicates + //CHECK: VarDecl{{.*}}max_replicates + //CHECK: IntelFPGAMaxReplicatesAttr + //CHECK: ConstantExpr + //CHECK-NEXT: value:{{.*}}2 + //CHECK: IntegerLiteral{{.*}}2{{$}} + //expected-warning@+2 {{attribute 'intelfpga::max_replicates' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::max_replicates' instead?}} + [[intelfpga::max_replicates(2)]] unsigned int max_replicates[64]; + //expected-error@+1{{'max_replicates' attribute requires integer constant between 1 and 1048576 inclusive}} - [[intelfpga::max_replicates(0)]] unsigned int maxrepl_zero[64]; + [[intel::max_replicates(0)]] unsigned int maxrepl_zero[64]; //expected-error@+1{{'max_replicates' attribute requires integer constant between 1 and 1048576 inclusive}} - [[intelfpga::max_replicates(-1)]] unsigned int maxrepl_negative[64]; + [[intel::max_replicates(-1)]] unsigned int maxrepl_negative[64]; - //expected-error@+3{{'max_replicates' and 'register' attributes are not compatible}} - [[intelfpga::register]] + //expected-error@+3{{'max_replicates' and 'fpga_register' attributes are not compatible}} + [[intel::fpga_register]] //expected-note@-1 {{conflicting attribute is here}} - [[intelfpga::max_replicates(2)]] - unsigned int maxrepl_reg[64]; + [[intel::max_replicates(2)]] unsigned int maxrepl_reg[64]; // **simple_dual_port //expected-error@+1{{'simple_dual_port' attribute takes no arguments}} - [[intelfpga::simple_dual_port(0)]] unsigned int sdp[64]; + [[intel::simple_dual_port(0)]] unsigned int sdp[64]; + + //CHECK: VarDecl{{.*}}dual_port + //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit + //CHECK: IntelFPGASimpleDualPortAttr + //expected-warning@+2 {{attribute 'intelfpga::simple_dual_port' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::simple_dual_port' instead?}} + [[intelfpga::simple_dual_port]] unsigned int dual_port[64]; //expected-note@+1 {{conflicting attribute is here}} - [[intelfpga::register]] - //expected-error@+1{{'simple_dual_port' and 'register' attributes are not compatible}} - [[intelfpga::simple_dual_port]] - unsigned int sdp_reg[64]; + [[intel::fpga_register]] + //expected-error@+1{{'simple_dual_port' and 'fpga_register' attributes are not compatible}} + [[intel::simple_dual_port]] unsigned int sdp_reg[64]; //CHECK: VarDecl{{.*}}bw_bw //CHECK: IntelFPGABankWidthAttr @@ -312,37 +350,41 @@ void diagnostics() //CHECK-NEXT: value:{{.*}}16 //CHECK-NEXT: IntegerLiteral{{.*}}16{{$}} //expected-warning@+2{{attribute 'bankwidth' is already applied}} - [[intelfpga::bankwidth(8)]] - [[intelfpga::bankwidth(16)]] - unsigned int bw_bw[64]; + [[intel::bankwidth(8)]] + [[intel::bankwidth(16)]] unsigned int bw_bw[64]; //expected-error@+1{{must be a constant power of two greater than zero}} - [[intelfpga::bankwidth(3)]] - unsigned int bw_invalid_value[64]; + [[intel::bankwidth(3)]] unsigned int bw_invalid_value[64]; //expected-error@+1{{requires integer constant between 1 and 1048576}} - [[intelfpga::bankwidth(-4)]] - unsigned int bw_negative[64]; + [[intel::bankwidth(-4)]] unsigned int bw_negative[64]; int i_bankwidth = 32; // expected-note {{declared here}} //expected-error@+1{{is not an integral constant expression}} - [[intelfpga::bankwidth(i_bankwidth)]] + [[intel::bankwidth(i_bankwidth)]] //expected-note@-1{{read of non-const variable 'i_bankwidth' is not allowed in a constant expression}} unsigned int bw_non_const[64]; //expected-error@+1{{'bankwidth' attribute takes one argument}} - [[intelfpga::bankwidth(4,8)]] - unsigned int bw_two_args[64]; + [[intel::bankwidth(4, 8)]] unsigned int bw_two_args[64]; //expected-error@+1{{requires integer constant between 1 and 1048576}} - [[intelfpga::bankwidth(0)]] - unsigned int bw_zero[64]; - + [[intel::bankwidth(0)]] unsigned int bw_zero[64]; // private_copies_ + //CHECK: VarDecl{{.*}}private_copies + //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit + //CHECK: IntelFPGAPrivateCopiesAttr + //CHECK-NEXT: ConstantExpr + //CHECK-NEXT: value:{{.*}}8 + //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}} + //expected-warning@+2 {{attribute 'intelfpga::private_copies' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::private_copies' instead?}} + [[intelfpga::private_copies(8)]] unsigned int private_copies[64]; + //expected-error@+2{{attributes are not compatible}} - [[intelfpga::private_copies(16)]] - [[intelfpga::register]] + [[intel::private_copies(16)]] + [[intel::fpga_register]] //expected-note@-2 {{conflicting attribute is here}} unsigned int pc_reg[64]; @@ -356,28 +398,35 @@ void diagnostics() //CHECK-NEXT: value:{{.*}}16 //CHECK-NEXT: IntegerLiteral{{.*}}16{{$}} //expected-warning@+2{{is already applied}} - [[intelfpga::private_copies(8)]] - [[intelfpga::private_copies(16)]] - unsigned int pc_pc[64]; + [[intel::private_copies(8)]] + [[intel::private_copies(16)]] unsigned int pc_pc[64]; //expected-error@+1{{'private_copies' attribute requires integer constant between 0 and 1048576 inclusive}} - [[intelfpga::private_copies(-4)]] - unsigned int pc_negative[64]; + [[intel::private_copies(-4)]] unsigned int pc_negative[64]; int i_private_copies = 32; // expected-note {{declared here}} //expected-error@+1{{expression is not an integral constant expression}} - [[intelfpga::private_copies(i_private_copies)]] + [[intel::private_copies(i_private_copies)]] //expected-note@-1{{read of non-const variable 'i_private_copies' is not allowed in a constant expression}} unsigned int pc_nonconst[64]; //expected-error@+1{{'private_copies' attribute takes one argument}} - [[intelfpga::private_copies(4,8)]] - unsigned int pc_two_arg[64]; + [[intel::private_copies(4, 8)]] unsigned int pc_two_arg[64]; // numbanks + //CHECK: VarDecl{{.*}}numbanks + //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit + //CHECK: IntelFPGANumBanksAttr + //CHECK-NEXT: ConstantExpr + //CHECK-NEXT: value:{{.*}}8 + //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}} + //expected-warning@+2 {{attribute 'intelfpga::numbanks' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::numbanks' instead?}} + [[intelfpga::numbanks(8)]] unsigned int numbanks[32]; + //expected-error@+2{{attributes are not compatible}} - [[intelfpga::numbanks(16)]] - [[intelfpga::register]] + [[intel::numbanks(16)]] + [[intel::fpga_register]] //expected-note@-2 {{conflicting attribute is here}} unsigned int nb_reg[64]; @@ -391,68 +440,86 @@ void diagnostics() //CHECK-NEXT: value:{{.*}}16 //CHECK-NEXT: IntegerLiteral{{.*}}16{{$}} //expected-warning@+2{{attribute 'numbanks' is already applied}} - [[intelfpga::numbanks(8)]] - [[intelfpga::numbanks(16)]] - unsigned int nb_nb[64]; + [[intel::numbanks(8)]] + [[intel::numbanks(16)]] unsigned int nb_nb[64]; //expected-error@+1{{must be a constant power of two greater than zero}} - [[intelfpga::numbanks(15)]] - unsigned int nb_invalid_arg[64]; + [[intel::numbanks(15)]] unsigned int nb_invalid_arg[64]; //expected-error@+1{{requires integer constant between 1 and 1048576}} - [[intelfpga::numbanks(-4)]] - unsigned int nb_negative[64]; + [[intel::numbanks(-4)]] unsigned int nb_negative[64]; int i_numbanks = 32; // expected-note {{declared here}} //expected-error@+1{{is not an integral constant expression}} - [[intelfpga::numbanks(i_numbanks)]] + [[intel::numbanks(i_numbanks)]] //expected-note@-1{{read of non-const variable 'i_numbanks' is not allowed in a constant expression}} unsigned int nb_nonconst[64]; //expected-error@+1{{'numbanks' attribute takes one argument}} - [[intelfpga::numbanks(4,8)]] - unsigned int nb_two_args[64]; + [[intel::numbanks(4, 8)]] unsigned int nb_two_args[64]; //expected-error@+1{{requires integer constant between 1 and 1048576}} - [[intelfpga::numbanks(0)]] - unsigned int nb_zero[64]; + [[intel::numbanks(0)]] unsigned int nb_zero[64]; // merge + //CHECK: VarDecl{{.*}}merge_depth + //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit + //CHECK: IntelFPGAMergeAttr{{.*}}"mrg1" "depth"{{$}} + //expected-warning@+2 {{attribute 'intelfpga::merge' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::merge' instead?}} + [[intelfpga::merge("mrg1", "depth")]] unsigned int merge_depth[64]; + //expected-error@+2{{attributes are not compatible}} - [[intelfpga::merge("mrg1","depth")]] - [[intelfpga::register]] + [[intel::merge("mrg1", "depth")]] + [[intel::fpga_register]] //expected-note@-2 {{conflicting attribute is here}} unsigned int mrg_reg[4]; //expected-error@+1{{attribute requires a string}} - [[intelfpga::merge(3,9.0f)]] - unsigned int mrg_float[4]; + [[intel::merge(3, 9.0f)]] unsigned int mrg_float[4]; //expected-error@+1{{attribute requires exactly 2 arguments}} - [[intelfpga::merge("mrg2")]] - unsigned int mrg_one_arg[4]; + [[intel::merge("mrg2")]] unsigned int mrg_one_arg[4]; //expected-error@+1{{attribute requires exactly 2 arguments}} - [[intelfpga::merge("mrg3","depth","oops")]] - unsigned int mrg_three_arg[4]; + [[intel::merge("mrg3", "depth", "oops")]] unsigned int mrg_three_arg[4]; //expected-error@+1{{merge direction must be 'depth' or 'width'}} - [[intelfpga::merge("mrg4","depths")]] - unsigned int mrg_invalid_arg[4]; + [[intel::merge("mrg4", "depths")]] unsigned int mrg_invalid_arg[4]; //Last one is applied and others ignored. //CHECK: VarDecl{{.*}}mrg_mrg //CHECK: IntelFPGAMergeAttr{{.*}}"mrg4" "depth"{{$}} //CHECK: IntelFPGAMergeAttr{{.*}}"mrg5" "width"{{$}} //expected-warning@+2{{attribute 'merge' is already applied}} - [[intelfpga::merge("mrg4","depth")]] - [[intelfpga::merge("mrg5","width")]] - unsigned int mrg_mrg[4]; + [[intel::merge("mrg4", "depth")]] + [[intel::merge("mrg5", "width")]] unsigned int mrg_mrg[4]; // bank_bits - //expected-error@+2 1{{'register' and 'bank_bits' attributes are not compatible}} - [[intelfpga::bank_bits(2,3)]] - [[intelfpga::register]] + //CHECK: VarDecl{{.*}}bankbits + //CHECK: IntelFPGANumBanksAttr{{.*}}Implicit{{$}} + //CHECK-NEXT: IntegerLiteral{{.*}}16{{$}} + //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit + //CHECK: IntelFPGABankBitsAttr + //CHECK-NEXT: ConstantExpr + //CHECK-NEXT: value:{{.*}}2 + //CHECK-NEXT: IntegerLiteral{{.*}}2{{$}} + //CHECK-NEXT: ConstantExpr + //CHECK-NEXT: value:{{.*}}3 + //CHECK-NEXT: IntegerLiteral{{.*}}3{{$}} + //CHECK-NEXT: ConstantExpr + //CHECK-NEXT: value:{{.*}}4 + //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}} + //CHECK-NEXT: ConstantExpr + //CHECK-NEXT: value:{{.*}}5 + //CHECK-NEXT: IntegerLiteral{{.*}}5{{$}} + //expected-warning@+2 {{attribute 'intelfpga::bank_bits' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::bank_bits' instead?}} + [[intelfpga::bank_bits(2, 3, 4, 5)]] unsigned int bankbits[64]; + + //expected-error@+2 1{{'fpga_register' and 'bank_bits' attributes are not compatible}} + [[intel::bank_bits(2, 3)]] + [[intel::fpga_register]] //expected-note@-2 1{{conflicting attribute is here}} unsigned int bb_reg[4]; @@ -472,40 +539,44 @@ void diagnostics() //CHECK-NEXT: value:{{.*}}2 //CHECK-NEXT: IntegerLiteral{{.*}}2{{$}} //expected-warning@+2{{attribute 'bank_bits' is already applied}} - [[intelfpga::bank_bits(42,43)]] - [[intelfpga::bank_bits(1,2)]] - unsigned int bb_bb[4]; + [[intel::bank_bits(42, 43)]] + [[intel::bank_bits(1, 2)]] unsigned int bb_bb[4]; //expected-error@+1{{the number of bank_bits must be equal to ceil(log2(numbanks))}} - [[intelfpga::numbanks(8), intelfpga::bank_bits(3,4)]] - unsigned int bb_numbanks[4]; + [[intel::numbanks(8), intel::bank_bits(3, 4)]] unsigned int bb_numbanks[4]; //expected-error@+1{{bank_bits must be consecutive}} - [[intelfpga::bank_bits(3,3,4), intelfpga::bankwidth(4)]] - unsigned int bb_noncons[4]; + [[intel::bank_bits(3, 3, 4), intel::bankwidth(4)]] unsigned int bb_noncons[4]; //expected-error@+1{{bank_bits must be consecutive}} - [[intelfpga::bank_bits(1,3,4), intelfpga::bankwidth(4)]] - unsigned int bb_noncons1[4]; + [[intel::bank_bits(1, 3, 4), intel::bankwidth(4)]] unsigned int bb_noncons1[4]; //expected-error@+1{{attribute takes at least 1 argument}} - [[intelfpga::bank_bits]] - unsigned int bb_no_arg[4]; + [[intel::bank_bits]] unsigned int bb_no_arg[4]; //expected-error@+1{{requires integer constant between 0 and 1048576}} - [[intelfpga::bank_bits(-1)]] - unsigned int bb_negative_arg[4]; + [[intel::bank_bits(-1)]] unsigned int bb_negative_arg[4]; // force_pow2_depth + //CHECK: VarDecl{{.*}}arr_force_p2d_0 + //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit + //CHECK: IntelFPGAForcePow2DepthAttr + //CHECK: ConstantExpr + //CHECK-NEXT: value:{{.*}}0 + //CHECK: IntegerLiteral{{.*}}0{{$}} + //expected-warning@+2 {{attribute 'intelfpga::force_pow2_depth' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::force_pow2_depth' instead?}} + [[intelfpga::force_pow2_depth(0)]] unsigned int arr_force_p2d_0[64]; + //expected-error@+1{{'force_pow2_depth' attribute requires integer constant between 0 and 1 inclusive}} - [[intelfpga::force_pow2_depth(-1)]] unsigned int force_p2d_below_min[64]; + [[intel::force_pow2_depth(-1)]] unsigned int force_p2d_below_min[64]; //expected-error@+1{{'force_pow2_depth' attribute requires integer constant between 0 and 1 inclusive}} - [[intelfpga::force_pow2_depth(2)]] unsigned int force_p2d_above_max[64]; + [[intel::force_pow2_depth(2)]] unsigned int force_p2d_above_max[64]; //expected-error@+1{{'force_pow2_depth' attribute takes one argument}} - [[intelfpga::force_pow2_depth]] unsigned int force_p2d_no_args[64]; + [[intel::force_pow2_depth]] unsigned int force_p2d_no_args[64]; //expected-error@+1{{'force_pow2_depth' attribute takes one argument}} - [[intelfpga::force_pow2_depth(0, 1)]] unsigned int force_p2d_2_args[64]; + [[intel::force_pow2_depth(0, 1)]] unsigned int force_p2d_2_args[64]; //CHECK: VarDecl{{.*}}force_p2d_dup //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -518,7 +589,7 @@ void diagnostics() //CHECK-NEXT: value:{{.*}}0 //CHECK-NEXT: IntegerLiteral{{.*}}0{{$}} //expected-warning@+1{{attribute 'force_pow2_depth' is already applied}} - [[intelfpga::force_pow2_depth(1), intelfpga::force_pow2_depth(0)]] unsigned int force_p2d_dup[64]; + [[intel::force_pow2_depth(1), intel::force_pow2_depth(0)]] unsigned int force_p2d_dup[64]; } //CHECK: FunctionDecl{{.*}}check_gnu_style @@ -562,57 +633,57 @@ void check_gnu_style() { } //expected-error@+1{{attribute only applies to local non-const variables and non-static data members}} -[[intelfpga::private_copies(8)]] -__attribute__((opencl_constant)) unsigned int const_var[64] = { 1, 2, 3 }; +[[intel::private_copies(8)]] +__attribute__((opencl_constant)) unsigned int const_var[64] = {1, 2, 3}; void attr_on_const_error() { //expected-error@+1{{attribute only applies to local non-const variables and non-static data members}} - [[intelfpga::private_copies(8)]] const int const_var[64] = { 0, 1 }; + [[intel::private_copies(8)]] const int const_var[64] = {0, 1}; } //expected-error@+1{{attribute only applies to local non-const variables and non-static data members}} -void attr_on_func_arg([[intelfpga::private_copies(8)]] int pc) {} +void attr_on_func_arg([[intel::private_copies(8)]] int pc) {} //expected-error@+1{{attribute only applies to constant variables, local variables, static variables, slave memory arguments, and non-static data members}} -[[intelfpga::force_pow2_depth(0)]] +[[intel::force_pow2_depth(0)]] __attribute__((opencl_global)) unsigned int ocl_glob_force_p2d[64] = {1, 2, 3}; //expected-no-error@+1 -void force_p2d_attr_on_func_arg([[intelfpga::force_pow2_depth(0)]] int pc) {} +void force_p2d_attr_on_func_arg([[intel::force_pow2_depth(0)]] int pc) {} struct foo { //CHECK: FieldDecl{{.*}}doublepump //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit //CHECK: IntelFPGADoublePumpAttr - [[intelfpga::doublepump]] unsigned int doublepump[64]; + [[intel::doublepump]] unsigned int doublepump[64]; //CHECK: FieldDecl{{.*}}memory //CHECK: IntelFPGAMemoryAttr - [[intelfpga::memory]] unsigned int memory[64]; + [[intel::fpga_memory]] unsigned int memory[64]; //CHECK: FieldDecl{{.*}}memory_mlab //CHECK: IntelFPGAMemoryAttr{{.*}}MLAB{{$}} - [[intelfpga::memory("MLAB")]] unsigned int memory_mlab[64]; + [[intel::fpga_memory("MLAB")]] unsigned int memory_mlab[64]; //CHECK: FieldDecl{{.*}}mem_blockram //CHECK: IntelFPGAMemoryAttr{{.*}}BlockRAM{{$}} - [[intelfpga::memory("BLOCK_RAM")]] unsigned int mem_blockram[64]; + [[intel::fpga_memory("BLOCK_RAM")]] unsigned int mem_blockram[64]; //CHECK: FieldDecl{{.*}}mem_blockram_doublepump //CHECK: IntelFPGAMemoryAttr{{.*}}BlockRAM{{$}} //CHECK: IntelFPGADoublePumpAttr - [[intelfpga::memory("BLOCK_RAM")]] - [[intelfpga::doublepump]] unsigned int mem_blockram_doublepump[64]; + [[intel::fpga_memory("BLOCK_RAM")]] + [[intel::doublepump]] unsigned int mem_blockram_doublepump[64]; //CHECK: FieldDecl{{.*}}reg //CHECK: IntelFPGARegisterAttr - [[intelfpga::register]] unsigned int reg[64]; + [[intel::fpga_register]] unsigned int reg[64]; //CHECK: FieldDecl{{.*}}singlepump //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit //CHECK: IntelFPGASinglePumpAttr - [[intelfpga::singlepump]] unsigned int singlepump[64]; + [[intel::singlepump]] unsigned int singlepump[64]; //CHECK: FieldDecl{{.*}}bankwidth //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -620,7 +691,7 @@ struct foo { //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}4 //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}} - [[intelfpga::bankwidth(4)]] unsigned int bankwidth[64]; + [[intel::bankwidth(4)]] unsigned int bankwidth[64]; //CHECK: FieldDecl{{.*}}numbanks //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -628,7 +699,7 @@ struct foo { //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}8 //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}} - [[intelfpga::numbanks(8)]] unsigned int numbanks[64]; + [[intel::numbanks(8)]] unsigned int numbanks[64]; //CHECK: FieldDecl{{.*}}private_copies //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -636,17 +707,17 @@ struct foo { //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}4 //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}} - [[intelfpga::private_copies(4)]] unsigned int private_copies[64]; + [[intel::private_copies(4)]] unsigned int private_copies[64]; //CHECK: FieldDecl{{.*}}merge_depth //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit //CHECK: IntelFPGAMergeAttr{{.*}}"mrg1" "depth"{{$}} - [[intelfpga::merge("mrg1", "depth")]] unsigned int merge_depth[64]; + [[intel::merge("mrg1", "depth")]] unsigned int merge_depth[64]; //CHECK: FieldDecl{{.*}}merge_width //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit //CHECK: IntelFPGAMergeAttr{{.*}}"mrg2" "width"{{$}} - [[intelfpga::merge("mrg2", "width")]] unsigned int merge_width[64]; + [[intel::merge("mrg2", "width")]] unsigned int merge_width[64]; //CHECK: FieldDecl{{.*}}bankbits //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -657,7 +728,7 @@ struct foo { //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}3 //CHECK-NEXT: IntegerLiteral{{.*}}3{{$}} - [[intelfpga::bank_bits(2,3)]] unsigned int bankbits[64]; + [[intel::bank_bits(2, 3)]] unsigned int bankbits[64]; //CHECK: FieldDecl{{.*}}force_p2d_field //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -665,7 +736,7 @@ struct foo { //CHECK-NEXT: ConstantExpr //CHECK-NEXT: value:{{.*}}1 //CHECK-NEXT: IntegerLiteral{{.*}}1{{$}} - [[intelfpga::force_pow2_depth(1)]] unsigned int force_p2d_field[64]; + [[intel::force_pow2_depth(1)]] unsigned int force_p2d_field[64]; }; //CHECK: FunctionDecl{{.*}}used check_template_parameters @@ -679,7 +750,7 @@ void check_template_parameters() { //CHECK-NEXT: SubstNonTypeTemplateParmExpr //CHECK-NEXT: NonTypeTemplateParmDecl //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}} - [[intelfpga::numbanks(C)]] unsigned int numbanks; + [[intel::numbanks(C)]] unsigned int numbanks; //CHECK: VarDecl{{.*}}private_copies //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -689,7 +760,7 @@ void check_template_parameters() { //CHECK-NEXT: SubstNonTypeTemplateParmExpr //CHECK-NEXT: NonTypeTemplateParmDecl //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}} - [[intelfpga::private_copies(C)]] unsigned int private_copies; + [[intel::private_copies(C)]] unsigned int private_copies; //CHECK: VarDecl{{.*}}bank_bits_width //CHECK: IntelFPGANumBanksAttr{{.*}}Implicit{{$}} @@ -710,8 +781,7 @@ void check_template_parameters() { //CHECK-NEXT: SubstNonTypeTemplateParmExpr //CHECK-NEXT: NonTypeTemplateParmDecl //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}} - [[intelfpga::bank_bits(A,3), intelfpga::bankwidth(C)]] - unsigned int bank_bits_width; + [[intel::bank_bits(A, 3), intel::bankwidth(C)]] unsigned int bank_bits_width; //CHECK: VarDecl{{.*}}max_replicates //CHECK: IntelFPGAMaxReplicatesAttr @@ -719,37 +789,34 @@ void check_template_parameters() { //CHECK-NEXT: value:{{.*}}2 //CHECK-NEXT: SubstNonTypeTemplateParmExpr //CHECK: IntegerLiteral{{.*}}2{{$}} - [[intelfpga::max_replicates(A)]] - unsigned int max_replicates; + [[intel::max_replicates(A)]] unsigned int max_replicates; - [[intelfpga::force_pow2_depth(E)]] const int const_force_p2d_templ[64] = {0, 1}; + [[intel::force_pow2_depth(E)]] const int const_force_p2d_templ[64] = {0, 1}; //expected-error@+1{{'numbanks' attribute takes one argument}} - [[intelfpga::numbanks(A,B)]] - int numbanks_negative; + [[intel::numbanks(A, B)]] int numbanks_negative; //expected-error@+1{{'max_replicates' attribute requires integer constant between 1 and 1048576}} - [[intelfpga::max_replicates(D)]] - [[intelfpga::max_replicates(C)]] + [[intel::max_replicates(D)]] + [[intel::max_replicates(C)]] //expected-warning@-1{{attribute 'max_replicates' is already applied}} unsigned int max_replicates_duplicate; - //expected-error@+3{{'max_replicates' and 'register' attributes are not compatible}} - [[intelfpga::register]] + //expected-error@+3{{'max_replicates' and 'fpga_register' attributes are not compatible}} + [[intel::fpga_register]] //expected-note@-1 {{conflicting attribute is here}} - [[intelfpga::max_replicates(C)]] - unsigned int maxrepl_reg; + [[intel::max_replicates(C)]] unsigned int maxrepl_reg; //expected-error@+1{{'force_pow2_depth' attribute requires integer constant between 0 and 1 inclusive}} - [[intelfpga::force_pow2_depth(A)]] unsigned int force_p2d_below_min[64]; + [[intel::force_pow2_depth(A)]] unsigned int force_p2d_below_min[64]; //expected-error@+1{{'force_pow2_depth' attribute takes one argument}} - [[intelfpga::force_pow2_depth(E, E)]] unsigned int force_p2d_2_args[64]; + [[intel::force_pow2_depth(E, E)]] unsigned int force_p2d_2_args[64]; - //expected-error@+3{{'force_pow2_depth' and 'register' attributes are not compatible}} - [[intelfpga::register]] + //expected-error@+3{{'force_pow2_depth' and 'fpga_register' attributes are not compatible}} + [[intel::fpga_register]] //expected-note@-1{{conflicting attribute is here}} - [[intelfpga::force_pow2_depth(E)]] unsigned int reg_force_p2d[64]; + [[intel::force_pow2_depth(E)]] unsigned int reg_force_p2d[64]; //CHECK: VarDecl{{.*}}force_p2d_dup //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit @@ -764,7 +831,7 @@ void check_template_parameters() { //CHECK-NEXT: value:{{.*}}0 //CHECK-NEXT: IntegerLiteral{{.*}}0{{$}} //expected-warning@+1{{attribute 'force_pow2_depth' is already applied}} - [[intelfpga::force_pow2_depth(E), intelfpga::force_pow2_depth(0)]] unsigned int force_p2d_dup[64]; + [[intel::force_pow2_depth(E), intel::force_pow2_depth(0)]] unsigned int force_p2d_dup[64]; } template @@ -777,7 +844,7 @@ struct templ_st { //CHECK-NEXT: SubstNonTypeTemplateParmExpr //CHECK-NEXT: NonTypeTemplateParmDecl //CHECK-NEXT: IntegerLiteral{{.*}}0{{$}} - [[intelfpga::force_pow2_depth(A)]] unsigned int templ_force_p2d_field[64]; + [[intel::force_pow2_depth(A)]] unsigned int templ_force_p2d_field[64]; }; template diff --git a/clang/test/SemaSYCL/intel-fpga-loops.cpp b/clang/test/SemaSYCL/intel-fpga-loops.cpp index 164d720eb1560..92c5434464838 100644 --- a/clang/test/SemaSYCL/intel-fpga-loops.cpp +++ b/clang/test/SemaSYCL/intel-fpga-loops.cpp @@ -3,28 +3,67 @@ // Test for Intel FPGA loop attributes applied not to a loop void foo() { // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::ivdep]] int a[10]; + [[intel::ivdep]] int a[10]; + // expected-error@+1 {{ loop attributes must be applied to for, while, or do statements}} + [[intel::ivdep(2)]] int b[10]; // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::ivdep(2)]] int b[10]; + [[intel::ii(2)]] int c[10]; // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::ii(2)]] int c[10]; - // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::max_concurrency(2)]] int d[10]; + [[intel::max_concurrency(2)]] int d[10]; int arr[10]; // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::ivdep(arr)]] int e[10]; + [[intel::ivdep(arr)]] int e[10]; // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::ivdep(arr, 2)]] int f[10]; + [[intel::ivdep(arr, 2)]] int f[10]; // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::disable_loop_pipelining]] int g[10]; + [[intel::disable_loop_pipelining]] int g[10]; // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::loop_coalesce(2)]] int h[10]; + [[intel::loop_coalesce(2)]] int h[10]; // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::max_interleaving(4)]] int i[10]; + [[intel::max_interleaving(4)]] int i[10]; // expected-error@+1 {{intelfpga loop attributes must be applied to for, while, or do statements}} - [[intelfpga::speculated_iterations(6)]] int j[10]; + [[intel::speculated_iterations(6)]] int j[10]; +} + +// Test for deprecated spelling of Intel FPGA loop attributes +void foo_deprecated() { + int a[10]; + // expected-warning@+2 {{attribute 'intelfpga::ivdep' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::ivdep' instead?}} + [[intelfpga::ivdep(2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + + // expected-warning@+2 {{attribute 'intelfpga::ii' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::ii' instead?}} + [[intelfpga::ii(2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + + // expected-warning@+2 {{attribute 'intelfpga::max_concurrency' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::max_concurrency' instead?}} + [[intelfpga::max_concurrency(4)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + + // expected-warning@+2 {{attribute 'intelfpga::max_interleaving' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::max_interleaving' instead?}} + [[intelfpga::max_interleaving(2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + + // expected-warning@+2 {{attribute 'intelfpga::disable_loop_pipelining' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::disable_loop_pipelining' instead?}} + [[intelfpga::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) + a[i] = 0; + + // expected-warning@+2 {{attribute 'intelfpga::loop_coalesce' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::loop_coalesce' instead?}} + [[intelfpga::loop_coalesce(2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + + // expected-warning@+2 {{attribute 'intelfpga::speculated_iterations' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::speculated_iterations' instead?}} + [[intelfpga::speculated_iterations(6)]] for (int i = 0; i != 10; ++i) + a[i] = 0; } // Test for incorrect number of arguments for Intel FPGA loop attributes @@ -32,53 +71,48 @@ void boo() { int a[10]; int b[10]; // expected-error@+1 {{duplicate argument to 'ivdep'. attribute requires one or both of a safelen and array}} - [[intelfpga::ivdep(2,2)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ivdep(2, 2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-warning@+1 {{'ii' attribute takes at least 1 argument - attribute ignored}} - [[intelfpga::ii]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ii]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-warning@+1 {{'ii' attribute takes no more than 1 argument - attribute ignored}} - [[intelfpga::ii(2,2)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ii(2, 2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-warning@+1 {{'max_concurrency' attribute takes at least 1 argument - attribute ignored}} - [[intelfpga::max_concurrency]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::max_concurrency]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-warning@+1 {{'max_concurrency' attribute takes no more than 1 argument - attribute ignored}} - [[intelfpga::max_concurrency(2,2)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::max_concurrency(2, 2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-error@+1 {{duplicate argument to 'ivdep'. attribute requires one or both of a safelen and array}} - [[intelfpga::ivdep(2, 3)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(2, 3)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{duplicate argument to 'ivdep'. attribute requires one or both of a safelen and array}} - [[intelfpga::ivdep(a, b)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(a, b)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{unknown argument to 'ivdep'. Expected integer or array variable}} - [[intelfpga::ivdep(2, 3.0)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(2, 3.0)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-warning@+1 {{'disable_loop_pipelining' attribute takes no more than 0 arguments - attribute ignored}} - [[intelfpga::disable_loop_pipelining(0)]] for (int i = 0; i != 10; ++i) + [[intel::disable_loop_pipelining(0)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-warning@+1 {{'loop_coalesce' attribute takes no more than 1 argument - attribute ignored}} - [[intelfpga::loop_coalesce(2, 3)]] for (int i = 0; i != 10; ++i) + [[intel::loop_coalesce(2, 3)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-warning@+1 {{'max_interleaving' attribute takes at least 1 argument - attribute ignored}} - [[intelfpga::max_interleaving]] for (int i = 0; i != 10; ++i) + [[intel::max_interleaving]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-warning@+1 {{'max_interleaving' attribute takes no more than 1 argument - attribute ignored}} - [[intelfpga::max_interleaving(2, 4)]] for (int i = 0; i != 10; ++i) + [[intel::max_interleaving(2, 4)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-warning@+1 {{'speculated_iterations' attribute takes at least 1 argument - attribute ignored}} - [[intelfpga::speculated_iterations]] for (int i = 0; i != 10; ++i) + [[intel::speculated_iterations]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-warning@+1 {{'speculated_iterations' attribute takes no more than 1 argument - attribute ignored}} - [[intelfpga::speculated_iterations(1, 2)]] for (int i = 0; i != 10; ++i) + [[intel::speculated_iterations(1, 2)]] for (int i = 0; i != 10; ++i) a[i] = 0; } @@ -86,65 +120,60 @@ void boo() { void goo() { int a[10]; // no diagnostics are expected - [[intelfpga::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) + [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) a[i] = 0; // no diagnostics are expected - [[intelfpga::max_concurrency(0)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::max_concurrency(0)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-error@+1 {{'ivdep' attribute requires a positive integral compile time constant expression}} - [[intelfpga::ivdep(0)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ivdep(0)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-error@+1 {{'ii' attribute requires a positive integral compile time constant expression}} - [[intelfpga::ii(0)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ii(0)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-error@+1 {{'max_concurrency' attribute requires a non-negative integral compile time constant expression}} - [[intelfpga::max_concurrency(-1)]] for (int i = 0; i != 10; ++i) + [[intel::max_concurrency(-1)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{'loop_coalesce' attribute requires a positive integral compile time constant expression}} - [[intelfpga::loop_coalesce(0)]] for (int i = 0; i != 10; ++i) + [[intel::loop_coalesce(0)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{'max_interleaving' attribute requires a non-negative integral compile time constant expression}} - [[intelfpga::max_interleaving(-1)]] for (int i = 0; i != 10; ++i) + [[intel::max_interleaving(-1)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{'speculated_iterations' attribute requires a non-negative integral compile time constant expression}} - [[intelfpga::speculated_iterations(-1)]] for (int i = 0; i != 10; ++i) + [[intel::speculated_iterations(-1)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{unknown argument to 'ivdep'. Expected integer or array variable}} - [[intelfpga::ivdep("test123")]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ivdep("test123")]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-error@+1 {{'ii' attribute requires an integer constant}} - [[intelfpga::ii("test123")]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ii("test123")]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-error@+1 {{'max_concurrency' attribute requires an integer constant}} - [[intelfpga::max_concurrency("test123")]] for (int i = 0; i != 10; ++i) + [[intel::max_concurrency("test123")]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{'loop_coalesce' attribute requires an integer constant}} - [[intelfpga::loop_coalesce("test123")]] for (int i = 0; i != 10; ++i) + [[intel::loop_coalesce("test123")]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{'max_interleaving' attribute requires an integer constant}} - [[intelfpga::max_interleaving("test123")]] for (int i = 0; i != 10; ++i) + [[intel::max_interleaving("test123")]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{'speculated_iterations' attribute requires an integer constant}} - [[intelfpga::speculated_iterations("test123")]] for (int i = 0; i != 10; ++i) + [[intel::speculated_iterations("test123")]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{unknown argument to 'ivdep'. Expected integer or array variable}} - [[intelfpga::ivdep("test123")]] for (int i = 0; i != 10; ++i) + [[intel::ivdep("test123")]] for (int i = 0; i != 10; ++i) a[i] = 0; // no diagnostics are expected - [[intelfpga::ivdep(a, 2)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(a, 2)]] for (int i = 0; i != 10; ++i) a[i] = 0; // no diagnostics are expected - [[intelfpga::ivdep(2, a)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(2, a)]] for (int i = 0; i != 10; ++i) a[i] = 0; int *ptr; // no diagnostics are expected - [[intelfpga::ivdep(2, ptr)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(2, ptr)]] for (int i = 0; i != 10; ++i) ptr[i] = 0; struct S { @@ -153,10 +182,10 @@ void goo() { } s; // no diagnostics are expected - [[intelfpga::ivdep(2, s.arr)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(2, s.arr)]] for (int i = 0; i != 10; ++i) s.arr[i] = 0; // no diagnostics are expected - [[intelfpga::ivdep(2, s.ptr)]] for (int i = 0; i != 10; ++i) + [[intel::ivdep(2, s.ptr)]] for (int i = 0; i != 10; ++i) s.ptr[i] = 0; } @@ -164,145 +193,131 @@ void goo() { void zoo() { int a[10]; // no diagnostics are expected - [[intelfpga::ivdep]] - [[intelfpga::max_concurrency(2)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intelfpga::ivdep]] + [[intel::ivdep]] + [[intel::max_concurrency(2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::ivdep]] // expected-warning@+2 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen INF >= safelen INF}} // expected-note@-2 {{previous attribute is here}} - [[intelfpga::ivdep]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intelfpga::ivdep]] + [[intel::ivdep]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::ivdep]] // expected-warning@+2 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen INF >= safelen 2}} // expected-note@-2 {{previous attribute is here}} - [[intelfpga::ivdep(2)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intelfpga::ivdep(2)]] + [[intel::ivdep(2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::ivdep(2)]] // expected-warning@-1 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen 4 >= safelen 2}} // expected-note@+1 {{previous attribute is here}} - [[intelfpga::ivdep(4)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intelfpga::max_concurrency(2)]] + [[intel::ivdep(4)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::max_concurrency(2)]] // expected-error@-1 {{duplicate Intel FPGA loop attribute 'max_concurrency'}} - [[intelfpga::max_concurrency(2)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intelfpga::ii(2)]] + [[intel::max_concurrency(2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::ii(2)]] // expected-error@-1 {{duplicate Intel FPGA loop attribute 'ii'}} - [[intelfpga::ii(2)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intelfpga::ii(2)]] + [[intel::ii(2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::ii(2)]] // expected-error@-1 {{duplicate Intel FPGA loop attribute 'ii'}} - [[intelfpga::max_concurrency(2)]] - [[intelfpga::ii(2)]] for (int i = 0; i != 10; ++i) + [[intel::max_concurrency(2)]] + [[intel::ii(2)]] for (int i = 0; i != 10; ++i) a[i] = 0; - [[intelfpga::disable_loop_pipelining]] + [[intel::disable_loop_pipelining]] // expected-error@-1 {{duplicate Intel FPGA loop attribute 'disable_loop_pipelining'}} - [[intelfpga::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) + [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) a[i] = 0; - [[intelfpga::loop_coalesce(2)]] + [[intel::loop_coalesce(2)]] // expected-error@-1 {{duplicate Intel FPGA loop attribute 'loop_coalesce'}} - [[intelfpga::max_interleaving(1)]] - [[intelfpga::loop_coalesce]] for (int i = 0; i != 10; ++i) + [[intel::max_interleaving(1)]] + [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) a[i] = 0; - [[intelfpga::max_interleaving(1)]] + [[intel::max_interleaving(1)]] // expected-error@-1 {{duplicate Intel FPGA loop attribute 'max_interleaving'}} - [[intelfpga::speculated_iterations(1)]] - [[intelfpga::max_interleaving(4)]] for (int i = 0; i != 10; ++i) + [[intel::speculated_iterations(1)]] + [[intel::max_interleaving(4)]] for (int i = 0; i != 10; ++i) a[i] = 0; - [[intelfpga::speculated_iterations(1)]] + [[intel::speculated_iterations(1)]] // expected-error@-1 {{duplicate Intel FPGA loop attribute 'speculated_iterations'}} - [[intelfpga::loop_coalesce]] - [[intelfpga::speculated_iterations(2)]] for (int i = 0; i != 10; ++i) + [[intel::loop_coalesce]] + [[intel::speculated_iterations(2)]] for (int i = 0; i != 10; ++i) a[i] = 0; - [[intelfpga::ivdep]] + [[intel::ivdep]] // expected-warning@+2 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen INF >= safelen INF}} // expected-note@-2 {{previous attribute is here}} - [[intelfpga::ivdep]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intelfpga::ivdep(2)]] + [[intel::ivdep]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::ivdep(2)]] // expected-warning@-1 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen INF >= safelen 2}} // expected-note@+1 {{previous attribute is here}} - [[intelfpga::ivdep]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intelfpga::ivdep(a, 2)]] + [[intel::ivdep]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::ivdep(a, 2)]] // expected-warning@-1 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen INF >= safelen 2}} // expected-note@+1 {{previous attribute is here}} - [[intelfpga::ivdep(a)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intelfpga::ivdep(2)]] + [[intel::ivdep(a)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::ivdep(2)]] // expected-warning@-1 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen 4 >= safelen 2}} // expected-note@+1 {{previous attribute is here}} - [[intelfpga::ivdep(4)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ivdep(4)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // no diagnostics are expected - [[intelfpga::ivdep(a)]] - [[intelfpga::ivdep(2)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ivdep(a)]] + [[intel::ivdep(2)]] for (int i = 0; i != 10; ++i) + a[i] = 0; - [[intelfpga::ivdep(a, 2)]] + [[intel::ivdep(a, 2)]] // expected-warning@-1 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen INF >= safelen 2}} // expected-note@+1 {{previous attribute is here}} - [[intelfpga::ivdep]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ivdep]] for (int i = 0; i != 10; ++i) + a[i] = 0; // Ensure we only diagnose conflict with the 'worst', not all. // expected-warning@+1 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen 5 >= safelen 3}} - [[intelfpga::ivdep(3)]] + [[intel::ivdep(3)]] // expected-warning@+1 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen 5 >= safelen 4}} - [[intelfpga::ivdep(4)]] + [[intel::ivdep(4)]] // expected-note@+1 2 {{previous attribute is here}} - [[intelfpga::ivdep(5)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ivdep(5)]] for (int i = 0; i != 10; ++i) + a[i] = 0; - [[intelfpga::ivdep(a, 2)]] + [[intel::ivdep(a, 2)]] // expected-warning@-1 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen 3 >= safelen 2}} // expected-note@+1 {{previous attribute is here}} - [[intelfpga::ivdep(a, 3)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ivdep(a, 3)]] for (int i = 0; i != 10; ++i) + a[i] = 0; } // Test for Intel FPGA loop attributes compatibility void loop_attrs_compatibility() { int a[10]; // no diagnostics are expected - [[intelfpga::disable_loop_pipelining]] - [[intelfpga::loop_coalesce]] for (int i = 0; i != 10; ++i) + [[intel::disable_loop_pipelining]] + [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{disable_loop_pipelining and max_interleaving attributes are not compatible}} - [[intelfpga::disable_loop_pipelining]] - [[intelfpga::max_interleaving(0)]] for (int i = 0; i != 10; ++i) + [[intel::disable_loop_pipelining]] + [[intel::max_interleaving(0)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{disable_loop_pipelining and speculated_iterations attributes are not compatible}} - [[intelfpga::speculated_iterations(0)]] - [[intelfpga::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) + [[intel::speculated_iterations(0)]] + [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{disable_loop_pipelining and max_concurrency attributes are not compatible}} - [[intelfpga::disable_loop_pipelining]] - [[intelfpga::max_concurrency(0)]] for (int i = 0; i != 10; ++i) + [[intel::disable_loop_pipelining]] + [[intel::max_concurrency(0)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{disable_loop_pipelining and ii attributes are not compatible}} - [[intelfpga::ii(10)]] - [[intelfpga::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) + [[intel::ii(10)]] + [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-error@+1 {{disable_loop_pipelining and ivdep attributes are not compatible}} - [[intelfpga::disable_loop_pipelining]] - [[intelfpga::ivdep]] for (int i = 0; i != 10; ++i) + [[intel::disable_loop_pipelining]] + [[intel::ivdep]] for (int i = 0; i != 10; ++i) a[i] = 0; } @@ -310,33 +325,31 @@ template void ivdep_dependent() { int a[10]; // test this again to ensure we skip properly during instantiation. - [[intelfpga::ivdep(3)]] + [[intel::ivdep(3)]] // expected-warning@-1 2{{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen 5 >= safelen 3}} // expected-note@+1 2{{previous attribute is here}} - [[intelfpga::ivdep(5)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ivdep(5)]] for (int i = 0; i != 10; ++i) + a[i] = 0; - [[intelfpga::ivdep(C)]] + [[intel::ivdep(C)]] // expected-error@-1 {{'ivdep' attribute requires a positive integral compile time constant expression}} for (int i = 0; i != 10; ++i) - a[i] = 0; + a[i] = 0; // expected-warning@+3 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen 4 >= safelen 2}} // expected-note@+1 {{previous attribute is here}} - [[intelfpga::ivdep(A)]] - [[intelfpga::ivdep(B)]] + [[intel::ivdep(A)]] + [[intel::ivdep(B)]] // expected-warning@-2 {{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen 4 >= safelen 2}} // expected-note@-2 {{previous attribute is here}} for (int i = 0; i != 10; ++i) - a[i] = 0; + a[i] = 0; (void)[]() { // expected-warning@+3 2{{ignoring redundant Intel FPGA loop attribute 'ivdep': safelen INF >= safelen INF}} // expected-note@+1 2{{previous attribute is here}} - [[intelfpga::ivdep]] - [[intelfpga::ivdep]] - while(true); + [[intel::ivdep]] + [[intel::ivdep]] while (true); }; } @@ -344,30 +357,26 @@ template void ii_dependent() { int a[10]; // expected-error@+1 {{'ii' attribute requires a positive integral compile time constant expression}} - [[intelfpga::ii(C)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ii(C)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-error@+1 {{duplicate Intel FPGA loop attribute 'ii'}} - [[intelfpga::ii(A)]] - [[intelfpga::ii(B)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::ii(A)]] + [[intel::ii(B)]] for (int i = 0; i != 10; ++i) + a[i] = 0; } template void max_concurrency_dependent() { int a[10]; // expected-error@+1 {{'max_concurrency' attribute requires a non-negative integral compile time constant expression}} - [[intelfpga::max_concurrency(C)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::max_concurrency(C)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-error@+1 {{duplicate Intel FPGA loop attribute 'max_concurrency'}} - [[intelfpga::max_concurrency(A)]] - [[intelfpga::max_concurrency(B)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::max_concurrency(A)]] + [[intel::max_concurrency(B)]] for (int i = 0; i != 10; ++i) + a[i] = 0; } template @@ -378,6 +387,7 @@ __attribute__((sycl_kernel)) void kernel_single_task(const Func &kernelFunc) { int main() { kernel_single_task([]() { foo(); + foo_deprecated(); boo(); goo(); zoo(); diff --git a/clang/test/SemaSYCL/intel-fpga-no-global-work-offset.cpp b/clang/test/SemaSYCL/intel-fpga-no-global-work-offset.cpp index 808eaf8c3e9e8..ff816237d6fb1 100644 --- a/clang/test/SemaSYCL/intel-fpga-no-global-work-offset.cpp +++ b/clang/test/SemaSYCL/intel-fpga-no-global-work-offset.cpp @@ -1,6 +1,8 @@ // RUN: %clang_cc1 -fsycl -fsycl-is-device -Wno-return-type -fcxx-exceptions -fsyntax-only -ast-dump -verify -pedantic %s | FileCheck %s struct FuncObj { + //expected-warning@+2 {{attribute 'intelfpga::no_global_work_offset' is deprecated}} + //expected-note@+1 {{did you mean to use 'intel::no_global_work_offset' instead?}} [[intelfpga::no_global_work_offset]] void operator()() {} }; @@ -18,24 +20,24 @@ int main() { // CHECK: SYCLIntelNoGlobalWorkOffsetAttr // CHECK-NOT: Enabled kernel( - []() [[intelfpga::no_global_work_offset(0)]]{}); + []() [[intel::no_global_work_offset(0)]]{}); // CHECK: SYCLIntelNoGlobalWorkOffsetAttr{{.*}}Enabled // expected-warning@+2{{'no_global_work_offset' attribute should be 0 or 1. Adjusted to 1}} kernel( - []() [[intelfpga::no_global_work_offset(42)]]{}); + []() [[intel::no_global_work_offset(42)]]{}); // expected-error@+2{{'no_global_work_offset' attribute requires a non-negative integral compile time constant expression}} kernel( - []() [[intelfpga::no_global_work_offset(-1)]]{}); + []() [[intel::no_global_work_offset(-1)]]{}); // expected-error@+2{{'no_global_work_offset' attribute requires parameter 0 to be an integer constant}} kernel( - []() [[intelfpga::no_global_work_offset("foo")]]{}); + []() [[intel::no_global_work_offset("foo")]]{}); kernel([]() { // expected-error@+1{{'no_global_work_offset' attribute only applies to functions}} - [[intelfpga::no_global_work_offset(1)]] int a; + [[intel::no_global_work_offset(1)]] int a; }); // CHECK: SYCLIntelNoGlobalWorkOffsetAttr{{.*}} @@ -43,7 +45,7 @@ int main() { // CHECK: SYCLIntelNoGlobalWorkOffsetAttr{{.*}}Enabled // expected-warning@+2{{attribute 'no_global_work_offset' is already applied}} kernel( - []() [[intelfpga::no_global_work_offset(0), intelfpga::no_global_work_offset(1)]]{}); + []() [[intel::no_global_work_offset(0), intel::no_global_work_offset(1)]]{}); return 0; } diff --git a/clang/test/SemaSYCL/intel-max-global-work-dim.cpp b/clang/test/SemaSYCL/intel-max-global-work-dim.cpp index c039787b6d8cf..b55994082342f 100644 --- a/clang/test/SemaSYCL/intel-max-global-work-dim.cpp +++ b/clang/test/SemaSYCL/intel-max-global-work-dim.cpp @@ -4,7 +4,7 @@ #ifndef __SYCL_DEVICE_ONLY__ struct FuncObj { - [[intelfpga::max_global_work_dim(1)]] // expected-no-diagnostics + [[intel::max_global_work_dim(1)]] // expected-no-diagnostics void operator()() const {} }; @@ -21,31 +21,37 @@ void foo() { #else // __SYCL_DEVICE_ONLY__ -[[intelfpga::max_global_work_dim(2)]] void func_do_not_ignore() {} +[[intel::max_global_work_dim(2)]] void func_do_not_ignore() {} struct FuncObj { - [[intelfpga::max_global_work_dim(1)]] void operator()() const {} + [[intel::max_global_work_dim(1)]] void operator()() const {} +}; + +struct Func { + // expected-warning@+2 {{attribute 'intelfpga::max_global_work_dim' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::max_global_work_dim' instead?}} + [[intelfpga::max_global_work_dim(2)]] void operator()() const {} }; struct TRIFuncObjGood1 { - [[intelfpga::max_global_work_dim(0)]] - [[intelfpga::max_work_group_size(1, 1, 1)]] + [[intel::max_global_work_dim(0)]] + [[intel::max_work_group_size(1, 1, 1)]] [[cl::reqd_work_group_size(1, 1, 1)]] void operator()() const {} }; struct TRIFuncObjGood2 { - [[intelfpga::max_global_work_dim(3)]] - [[intelfpga::max_work_group_size(8, 1, 1)]] + [[intel::max_global_work_dim(3)]] + [[intel::max_work_group_size(8, 1, 1)]] [[cl::reqd_work_group_size(4, 1, 1)]] void operator()() const {} }; #ifdef TRIGGER_ERROR struct TRIFuncObjBad { - [[intelfpga::max_global_work_dim(0)]] - [[intelfpga::max_work_group_size(8, 8, 8)]] // expected-error{{'max_work_group_size' X-, Y- and Z- sizes must be 1 when 'max_global_work_dim' attribute is used with value 0}} - [[cl::reqd_work_group_size(4, 4, 4)]] // expected-error{{'reqd_work_group_size' X-, Y- and Z- sizes must be 1 when 'max_global_work_dim' attribute is used with value 0}} + [[intel::max_global_work_dim(0)]] + [[intel::max_work_group_size(8, 8, 8)]] // expected-error{{'max_work_group_size' X-, Y- and Z- sizes must be 1 when 'max_global_work_dim' attribute is used with value 0}} + [[cl::reqd_work_group_size(4, 4, 4)]] // expected-error{{'reqd_work_group_size' X-, Y- and Z- sizes must be 1 when 'max_global_work_dim' attribute is used with value 0}} void operator()() const {} }; @@ -64,8 +70,10 @@ int main() { // CHECK-LABEL: FunctionDecl {{.*}}test_kernel2 // CHECK: SYCLIntelMaxGlobalWorkDimAttr {{.*}} 2 + // expected-warning@+3 {{attribute 'intelfpga::max_global_work_dim' is deprecated}} + // expected-note@+2 {{did you mean to use 'intel::max_global_work_dim' instead?}} kernel( - []() [[intelfpga::max_global_work_dim(2)]] {}); + []() [[intelfpga::max_global_work_dim(2)]]{}); // CHECK-LABEL: FunctionDecl {{.*}}test_kernel3 // CHECK: SYCLIntelMaxGlobalWorkDimAttr {{.*}} @@ -87,20 +95,20 @@ int main() { // CHECK: SYCLIntelMaxGlobalWorkDimAttr {{.*}} 3 #ifdef TRIGGER_ERROR - [[intelfpga::max_global_work_dim(1)]] int Var = 0; // expected-error{{'max_global_work_dim' attribute only applies to functions}} + [[intel::max_global_work_dim(1)]] int Var = 0; // expected-error{{'max_global_work_dim' attribute only applies to functions}} kernel( - []() [[intelfpga::max_global_work_dim(-8)]] {}); // expected-error{{'max_global_work_dim' attribute requires a non-negative integral compile time constant expression}} + []() [[intel::max_global_work_dim(-8)]]{}); // expected-error{{'max_global_work_dim' attribute requires a non-negative integral compile time constant expression}} kernel( - []() [[intelfpga::max_global_work_dim(3), - intelfpga::max_global_work_dim(2)]] {}); // expected-warning{{attribute 'max_global_work_dim' is already applied with different parameters}} + []() [[intel::max_global_work_dim(3), + intel::max_global_work_dim(2)]]{}); // expected-warning{{attribute 'max_global_work_dim' is already applied with different parameters}} kernel( TRIFuncObjBad()); kernel( - []() [[intelfpga::max_global_work_dim(4)]] {}); // expected-error{{The value of 'max_global_work_dim' attribute must be in range from 0 to 3}} + []() [[intel::max_global_work_dim(4)]]{}); // expected-error{{The value of 'max_global_work_dim' attribute must be in range from 0 to 3}} #endif // TRIGGER_ERROR } diff --git a/clang/test/SemaSYCL/intel-max-work-group-size.cpp b/clang/test/SemaSYCL/intel-max-work-group-size.cpp index 210944f6b2fdd..6a05833815835 100644 --- a/clang/test/SemaSYCL/intel-max-work-group-size.cpp +++ b/clang/test/SemaSYCL/intel-max-work-group-size.cpp @@ -4,7 +4,7 @@ #ifndef __SYCL_DEVICE_ONLY__ struct FuncObj { - [[intelfpga::max_work_group_size(1, 1, 1)]] // expected-no-diagnostics + [[intel::max_work_group_size(1, 1, 1)]] // expected-no-diagnostics void operator()() const {} }; @@ -21,15 +21,21 @@ void foo() { #else // __SYCL_DEVICE_ONLY__ -[[intelfpga::max_work_group_size(2, 2, 2)]] void func_do_not_ignore() {} +[[intel::max_work_group_size(2, 2, 2)]] void func_do_not_ignore() {} struct FuncObj { - [[intelfpga::max_work_group_size(4, 4, 4)]] void operator()() const {} + [[intel::max_work_group_size(4, 4, 4)]] void operator()() const {} +}; + +struct Func { + // expected-warning@+2 {{attribute 'intelfpga::max_work_group_size' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::max_work_group_size' instead?}} + [[intelfpga::max_work_group_size(1, 1, 1)]] void operator()() const {} }; #ifdef TRIGGER_ERROR struct DAFuncObj { - [[intelfpga::max_work_group_size(4, 4, 4)]] + [[intel::max_work_group_size(4, 4, 4)]] [[cl::reqd_work_group_size(8, 8, 4)]] // expected-error{{'reqd_work_group_size' attribute conflicts with 'max_work_group_size' attribute}} void operator()() const {} @@ -49,8 +55,10 @@ int main() { // CHECK-LABEL: FunctionDecl {{.*}}test_kernel2 // CHECK: SYCLIntelMaxWorkGroupSizeAttr {{.*}} 8 8 8 + // expected-warning@+3 {{attribute 'intelfpga::max_work_group_size' is deprecated}} + // expected-note@+2 {{did you mean to use 'intel::max_work_group_size' instead?}} kernel( - []() [[intelfpga::max_work_group_size(8, 8, 8)]] {}); + []() [[intelfpga::max_work_group_size(8, 8, 8)]]{}); // CHECK-LABEL: FunctionDecl {{.*}}test_kernel3 // CHECK: SYCLIntelMaxWorkGroupSizeAttr {{.*}} @@ -58,17 +66,17 @@ int main() { []() { func_do_not_ignore(); }); #ifdef TRIGGER_ERROR - [[intelfpga::max_work_group_size(1, 1, 1)]] int Var = 0; // expected-error{{'max_work_group_size' attribute only applies to functions}} + [[intel::max_work_group_size(1, 1, 1)]] int Var = 0; // expected-error{{'max_work_group_size' attribute only applies to functions}} kernel( - []() [[intelfpga::max_work_group_size(0, 1, 3)]] {}); // expected-error{{'max_work_group_size' attribute must be greater than 0}} + []() [[intel::max_work_group_size(0, 1, 3)]]{}); // expected-error{{'max_work_group_size' attribute must be greater than 0}} kernel( - []() [[intelfpga::max_work_group_size(-8, 8, 1)]] {}); // expected-error{{'max_work_group_size' attribute requires a non-negative integral compile time constant expression}} + []() [[intel::max_work_group_size(-8, 8, 1)]]{}); // expected-error{{'max_work_group_size' attribute requires a non-negative integral compile time constant expression}} kernel( - []() [[intelfpga::max_work_group_size(16, 16, 16), - intelfpga::max_work_group_size(2, 2, 2)]] {}); // expected-warning{{attribute 'max_work_group_size' is already applied with different parameters}} + []() [[intel::max_work_group_size(16, 16, 16), + intel::max_work_group_size(2, 2, 2)]]{}); // expected-warning{{attribute 'max_work_group_size' is already applied with different parameters}} kernel( DAFuncObj()); diff --git a/clang/test/SemaSYCL/loop_unroll.cpp b/clang/test/SemaSYCL/loop_unroll.cpp index 13ecae08d7430..be6e3554c1ab6 100644 --- a/clang/test/SemaSYCL/loop_unroll.cpp +++ b/clang/test/SemaSYCL/loop_unroll.cpp @@ -39,8 +39,7 @@ void foo() { // no error expected [[clang::loop_unroll(4)]] - [[intelfpga::ii(2)]] - for (int i = 0; i < 10; ++i); + [[intel::ii(2)]] for (int i = 0; i < 10; ++i); // expected-error@+2 {{'loop_unroll' attribute requires an integer constant}} int b = 4; diff --git a/clang/test/SemaSYCL/num_simd_work_items_device.cpp b/clang/test/SemaSYCL/num_simd_work_items_device.cpp index 4659183cb73e7..b48d6b8d322bc 100644 --- a/clang/test/SemaSYCL/num_simd_work_items_device.cpp +++ b/clang/test/SemaSYCL/num_simd_work_items_device.cpp @@ -3,11 +3,18 @@ #ifndef __SYCL_DEVICE_ONLY__ struct FuncObj { - [[intelfpga::num_simd_work_items(42)]] // expected-no-diagnostics + [[intel::num_simd_work_items(42)]] // expected-no-diagnostics void operator()() const {} }; +struct FuncObj { + // expected-warning@+2 {{attribute 'intelfpga::num_simd_work_items' is deprecated}} + // expected-note@+1 {{did you mean to use 'intel::num_simd_work_items' instead?}} + [[intelfpga::num_simd_work_items(42)]] void + operator()() const {} +}; + template void kernel(const Func &kernelFunc) { kernelFunc(); @@ -19,10 +26,10 @@ void foo() { } #else // __SYCL_DEVICE_ONLY__ -[[intelfpga::num_simd_work_items(2)]] void func_do_not_ignore() {} +[[intel::num_simd_work_items(2)]] void func_do_not_ignore() {} struct FuncObj { - [[intelfpga::num_simd_work_items(42)]] void operator()() const {} + [[intel::num_simd_work_items(42)]] void operator()() const {} }; template @@ -40,8 +47,10 @@ int main() { // CHECK-LABEL: FunctionDecl {{.*}}test_kernel2 // CHECK: SYCLIntelNumSimdWorkItemsAttr {{.*}} // CHECK-NEXT: IntegerLiteral{{.*}}8{{$}} + // expected-warning@+3 {{attribute 'intelfpga::num_simd_work_items' is deprecated}} + // expected-note@+2 {{did you mean to use 'intel::num_simd_work_items' instead?}} kernel( - []() [[intelfpga::num_simd_work_items(8)]] {}); + []() [[intelfpga::num_simd_work_items(8)]]{}); // CHECK-LABEL: FunctionDecl {{.*}}test_kernel3 // CHECK: SYCLIntelNumSimdWorkItemsAttr {{.*}} @@ -50,16 +59,16 @@ int main() { []() { func_do_not_ignore(); }); #ifdef TRIGGER_ERROR - [[intelfpga::num_simd_work_items(0)]] int Var = 0; // expected-error{{'num_simd_work_items' attribute only applies to functions}} + [[intel::num_simd_work_items(0)]] int Var = 0; // expected-error{{'num_simd_work_items' attribute only applies to functions}} kernel( - []() [[intelfpga::num_simd_work_items(0)]]{}); // expected-error{{'num_simd_work_items' attribute requires a positive integral compile time constant expression}} + []() [[intel::num_simd_work_items(0)]]{}); // expected-error{{'num_simd_work_items' attribute requires a positive integral compile time constant expression}} kernel( - []() [[intelfpga::num_simd_work_items(-42)]]{}); // expected-error{{'num_simd_work_items' attribute requires a positive integral compile time constant expression}} + []() [[intel::num_simd_work_items(-42)]]{}); // expected-error{{'num_simd_work_items' attribute requires a positive integral compile time constant expression}} kernel( - []() [[intelfpga::num_simd_work_items(1), intelfpga::num_simd_work_items(2)]] {}); // expected-warning{{attribute 'num_simd_work_items' is already applied with different parameters}} + []() [[intel::num_simd_work_items(1), intel::num_simd_work_items(2)]]{}); // expected-warning{{attribute 'num_simd_work_items' is already applied with different parameters}} #endif // TRIGGER_ERROR } #endif // __SYCL_DEVICE_ONLY__ diff --git a/clang/test/SemaSYCL/num_simd_work_items_host.cpp b/clang/test/SemaSYCL/num_simd_work_items_host.cpp index c447cc1d6a0c4..07027c12a538b 100644 --- a/clang/test/SemaSYCL/num_simd_work_items_host.cpp +++ b/clang/test/SemaSYCL/num_simd_work_items_host.cpp @@ -1,8 +1,8 @@ // RUN: %clang_cc1 -fsycl -fsycl-is-host -fsyntax-only -Wno-sycl-2017-compat -verify %s // expected-no-diagnostics -[[intelfpga::num_simd_work_items(2)]] void func_do_not_ignore() {} +[[intel::num_simd_work_items(2)]] void func_do_not_ignore() {} struct FuncObj { - [[intelfpga::num_simd_work_items(42)]] void operator()() const {} + [[intel::num_simd_work_items(42)]] void operator()() const {} }; diff --git a/clang/test/SemaSYCL/redeclaration-attribute-propagation.cpp b/clang/test/SemaSYCL/redeclaration-attribute-propagation.cpp index 00d6311449e83..4b2777c1bb9dd 100644 --- a/clang/test/SemaSYCL/redeclaration-attribute-propagation.cpp +++ b/clang/test/SemaSYCL/redeclaration-attribute-propagation.cpp @@ -6,17 +6,17 @@ #ifndef TRIGGER_ERROR //first case - good case -[[intelfpga::no_global_work_offset]] // expected-no-diagnostics +[[intel::no_global_work_offset]] // expected-no-diagnostics void func1(); -[[intelfpga::max_work_group_size(4, 4, 4)]] void func1(); +[[intel::max_work_group_size(4, 4, 4)]] void func1(); [[cl::reqd_work_group_size(2, 2, 2)]] void func1() {} #else //second case - expect error -[[intelfpga::max_work_group_size(4, 4, 4)]] // expected-note {{conflicting attribute is here}} +[[intel::max_work_group_size(4, 4, 4)]] // expected-note {{conflicting attribute is here}} void func2(); @@ -35,11 +35,11 @@ void func3() {} // expected-error {{'reqd_work_group_size' attribute conflicts with ''reqd_work_group_size'' attribute}} //fourth case - expect error -[[intelfpga::max_work_group_size(4, 4, 4)]] // expected-note {{conflicting attribute is here}} +[[intel::max_work_group_size(4, 4, 4)]] // expected-note {{conflicting attribute is here}} void func4(); -[[intelfpga::max_work_group_size(8, 8, 8)]] // expected-note {{conflicting attribute is here}} +[[intel::max_work_group_size(8, 8, 8)]] // expected-note {{conflicting attribute is here}} void // expected-warning@+1 {{attribute 'max_work_group_size' is already applied with different parameters}} func4() {} // expected-error {{'max_work_group_size' attribute conflicts with ''max_work_group_size'' attribute}} diff --git a/clang/test/SemaSYCL/spurious-host-warning.cpp b/clang/test/SemaSYCL/spurious-host-warning.cpp index dd2c94b5df6f0..fc5aacdf95917 100644 --- a/clang/test/SemaSYCL/spurious-host-warning.cpp +++ b/clang/test/SemaSYCL/spurious-host-warning.cpp @@ -7,56 +7,54 @@ void foo() { - #ifndef SYCLHOST - // expected-warning@+2 {{'doublepump' attribute ignored}} - #endif - [[intelfpga::doublepump]] unsigned int v_one[64]; - - #ifndef SYCLHOST - // expected-warning@+2 {{'memory' attribute ignored}} - #endif - [[intelfpga::memory]] unsigned int v_two[64]; - - #ifndef SYCLHOST - // expected-warning@+2 {{'register' attribute ignored}} - #endif - [[intelfpga::register]] unsigned int v_three[64]; - - #ifndef SYCLHOST - // expected-warning@+2 {{'singlepump' attribute ignored}} - #endif - [[intelfpga::singlepump]] unsigned int v_four[64]; - - #ifndef SYCLHOST - // expected-warning@+2 {{'bankwidth' attribute ignored}} - #endif - [[intelfpga::bankwidth(4)]] unsigned int v_five[32]; - - #ifndef SYCLHOST - // expected-warning@+2 {{'numbanks' attribute ignored}} - #endif - [[intelfpga::numbanks(8)]] unsigned int v_six[32]; - - #ifndef SYCLHOST - // expected-warning@+2 {{'private_copies' attribute ignored}} - #endif - [[intelfpga::private_copies(8)]] unsigned int v_seven[64]; - - #ifndef SYCLHOST - // expected-warning@+2 {{'merge' attribute ignored}} - #endif - [[intelfpga::merge("mrg1","depth")]] unsigned int v_eight[64]; - - #ifndef SYCLHOST - // expected-warning@+2 {{'max_replicates' attribute ignored}} - #endif - [[intelfpga::max_replicates(2)]] - unsigned int v_nine[64]; - - #ifndef SYCLHOST - // expected-warning@+2 {{'simple_dual_port' attribute ignored}} - #endif - [[intelfpga::simple_dual_port]] - unsigned int v_ten[64]; +#ifndef SYCLHOST +// expected-warning@+2 {{'doublepump' attribute ignored}} +#endif + [[intel::doublepump]] unsigned int v_one[64]; + +#ifndef SYCLHOST +// expected-warning@+2 {{'fpga_memory' attribute ignored}} +#endif + [[intel::fpga_memory]] unsigned int v_two[64]; + +#ifndef SYCLHOST +// expected-warning@+2 {{'fpga_register' attribute ignored}} +#endif + [[intel::fpga_register]] unsigned int v_three[64]; + +#ifndef SYCLHOST +// expected-warning@+2 {{'singlepump' attribute ignored}} +#endif + [[intel::singlepump]] unsigned int v_four[64]; + +#ifndef SYCLHOST +// expected-warning@+2 {{'bankwidth' attribute ignored}} +#endif + [[intel::bankwidth(4)]] unsigned int v_five[32]; + +#ifndef SYCLHOST +// expected-warning@+2 {{'numbanks' attribute ignored}} +#endif + [[intel::numbanks(8)]] unsigned int v_six[32]; + +#ifndef SYCLHOST +// expected-warning@+2 {{'private_copies' attribute ignored}} +#endif + [[intel::private_copies(8)]] unsigned int v_seven[64]; + +#ifndef SYCLHOST +// expected-warning@+2 {{'merge' attribute ignored}} +#endif + [[intel::merge("mrg1", "depth")]] unsigned int v_eight[64]; + +#ifndef SYCLHOST +// expected-warning@+2 {{'max_replicates' attribute ignored}} +#endif + [[intel::max_replicates(2)]] unsigned int v_nine[64]; + +#ifndef SYCLHOST +// expected-warning@+2 {{'simple_dual_port' attribute ignored}} +#endif + [[intel::simple_dual_port]] unsigned int v_ten[64]; } diff --git a/clang/test/SemaSYCL/sycl-device-num_simd_work_items-template.cpp b/clang/test/SemaSYCL/sycl-device-num_simd_work_items-template.cpp index 6e100636cbcb2..4f4f9286b5d72 100644 --- a/clang/test/SemaSYCL/sycl-device-num_simd_work_items-template.cpp +++ b/clang/test/SemaSYCL/sycl-device-num_simd_work_items-template.cpp @@ -6,7 +6,7 @@ template class KernelFunctor { public: // expected-error@+1{{'num_simd_work_items' attribute requires a positive integral compile time constant expression}} - [[intelfpga::num_simd_work_items(SIZE)]] void operator()() {} + [[intel::num_simd_work_items(SIZE)]] void operator()() {} }; int main() {