diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 579171129567..8a4cc2d88ce5 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -317,10 +317,14 @@ class SubjectList subjects, SubjectDiag diag = WarnDiag, string CustomDiag = customDiag; } -class LangOpt { +class LangOpt { // The language option to test; ignored when custom code is supplied. string Name = name; + // If set to 1, the attribute is accepted but is silently ignored. This is + // useful in multi-compilation situations like SYCL. + bit SilentlyIgnore = silentlyIgnore; + // A custom predicate, written as an expression evaluated in a context with // "LangOpts" bound. code CustomCode = customCode; @@ -329,9 +333,10 @@ def MicrosoftExt : LangOpt<"MicrosoftExt">; def Borland : LangOpt<"Borland">; def CUDA : LangOpt<"CUDA">; def HIP : LangOpt<"HIP">; +def SYCL : LangOpt<"SYCL">; def SYCLIsDevice : LangOpt<"SYCLIsDevice">; -def SYCL : LangOpt<"SYCLIsDevice">; def SYCLIsHost : LangOpt<"SYCLIsHost">; +def SilentlyIgnoreSYCLIsHost : LangOpt<"SYCLIsHost", "", 1>; def SYCLExplicitSIMD : LangOpt<"SYCLExplicitSIMD">; def COnly : LangOpt<"", "!LangOpts.CPlusPlus">; def CPlusPlus : LangOpt<"CPlusPlus">; @@ -1322,7 +1327,7 @@ def SYCLIntelNoGlobalWorkOffset : InheritableAttr { let Spellings = [CXX11<"intelfpga","no_global_work_offset">, CXX11<"intel","no_global_work_offset">]; let Args = [ExprArgument<"Value", /*optional*/1>]; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Subjects = SubjectList<[Function], ErrorDiag>; let Documentation = [SYCLIntelNoGlobalWorkOffsetAttrDocs]; } @@ -1331,7 +1336,7 @@ def SYCLIntelLoopFuse : InheritableAttr { let Spellings = [CXX11<"intel", "loop_fuse">, CXX11<"intel", "loop_fuse_independent">]; let Args = [ExprArgument<"Value", /*optional=*/ 1>]; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Subjects = SubjectList<[Function], ErrorDiag>; let Accessors = [Accessor<"isIndependent", [CXX11<"intel", "loop_fuse_independent">]>]; @@ -1395,7 +1400,7 @@ def IntelReqdSubGroupSize: InheritableAttr { let Args = [ExprArgument<"Value">]; let Subjects = SubjectList<[Function], ErrorDiag>; let Documentation = [IntelReqdSubGroupSizeDocs]; - let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost]; + let LangOpts = [OpenCL, SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; } // This attribute is both a type attribute, and a declaration attribute (for @@ -1841,7 +1846,7 @@ def SYCLIntelFPGAInitiationInterval : StmtAttr { let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], ErrorDiag, "'for', 'while', and 'do' statements">; let Args = [ExprArgument<"IntervalExpr">]; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let HasCustomTypeTransform = 1; let Documentation = [SYCLIntelFPGAInitiationIntervalAttrDocs]; } @@ -1852,7 +1857,7 @@ def SYCLIntelFPGAMaxConcurrency : StmtAttr { let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], ErrorDiag, "'for', 'while', and 'do' statements">; let Args = [ExprArgument<"NThreadsExpr">]; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let HasCustomTypeTransform = 1; let Documentation = [SYCLIntelFPGAMaxConcurrencyAttrDocs]; } @@ -1863,7 +1868,7 @@ def SYCLIntelFPGALoopCoalesce : StmtAttr { let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], ErrorDiag, "'for', 'while', and 'do' statements">; let Args = [ExprArgument<"NExpr">]; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let HasCustomTypeTransform = 1; let Documentation = [SYCLIntelFPGALoopCoalesceAttrDocs]; } @@ -1873,7 +1878,7 @@ def SYCLIntelFPGADisableLoopPipelining : StmtAttr { CXX11<"intel","disable_loop_pipelining">]; let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], ErrorDiag, "'for', 'while', and 'do' statements">; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let HasCustomTypeTransform = 1; let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs]; } @@ -1884,7 +1889,7 @@ def SYCLIntelFPGAMaxInterleaving : StmtAttr { let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], ErrorDiag, "'for', 'while', and 'do' statements">; let Args = [ExprArgument<"NExpr">]; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let HasCustomTypeTransform = 1; let Documentation = [SYCLIntelFPGAMaxInterleavingAttrDocs]; } @@ -1895,7 +1900,7 @@ def SYCLIntelFPGASpeculatedIterations : StmtAttr { let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], ErrorDiag, "'for', 'while', and 'do' statements">; let Args = [ExprArgument<"NExpr">]; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let HasCustomTypeTransform = 1; let Documentation = [SYCLIntelFPGASpeculatedIterationsAttrDocs]; } @@ -1904,7 +1909,7 @@ def SYCLIntelFPGANofusion : StmtAttr { let Spellings = [CXX11<"intel","nofusion">]; let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], ErrorDiag, "'for', 'while', and 'do' statements">; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let HasCustomTypeTransform = 1; let Documentation = [SYCLIntelFPGANofusionAttrDocs]; } @@ -1946,7 +1951,7 @@ def IntelFPGADoublePump : Attr { CXX11<"intel", "doublepump">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGADoublePumpAttrDocs]; } @@ -1955,7 +1960,7 @@ def IntelFPGASinglePump : Attr { CXX11<"intel", "singlepump">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGASinglePumpAttrDocs]; } @@ -1976,7 +1981,7 @@ def IntelFPGAMemory : Attr { }]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGAMemoryAttrDocs]; } @@ -1985,7 +1990,7 @@ def IntelFPGARegister : Attr { CXX11<"intel", "fpga_register">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGARegisterAttrDocs]; } @@ -1996,7 +2001,7 @@ def IntelFPGABankWidth : Attr { let Args = [ExprArgument<"Value">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGABankWidthAttrDocs]; } @@ -2006,7 +2011,7 @@ def IntelFPGANumBanks : Attr { let Args = [ExprArgument<"Value">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGANumBanksAttrDocs]; } @@ -2014,7 +2019,7 @@ def IntelFPGAPrivateCopies : InheritableAttr { let Spellings = [CXX11<"intelfpga","private_copies">, CXX11<"intel","private_copies">]; let Args = [ExprArgument<"Value">]; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>; let Documentation = [IntelFPGAPrivateCopiesAttrDocs]; } @@ -2026,7 +2031,7 @@ def IntelFPGAMerge : Attr { let Args = [StringArgument<"Name">, StringArgument<"Direction">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGAMergeAttrDocs]; } @@ -2036,7 +2041,7 @@ def IntelFPGAMaxReplicates : Attr { let Args = [ExprArgument<"Value">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGAMaxReplicatesAttrDocs]; } @@ -2045,7 +2050,7 @@ def IntelFPGASimpleDualPort : Attr { CXX11<"intel","simple_dual_port">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGASimpleDualPortAttrDocs]; } @@ -2081,7 +2086,7 @@ def IntelFPGAForcePow2Depth : Attr { let Args = [ExprArgument<"Value">]; let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar, Field], ErrorDiag>; - let LangOpts = [SYCLIsDevice, SYCLIsHost]; + let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; let Documentation = [IntelFPGAForcePow2DepthAttrDocs]; let AdditionalMembers = [{ static unsigned getMinValue() { diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 1b3028b5a9c3..13f9c9661d5d 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -3211,9 +3211,6 @@ static void handleWorkGroupSizeHint(Sema &S, Decl *D, const ParsedAttr &AL) { void Sema::AddIntelReqdSubGroupSize(Decl *D, const AttributeCommonInfo &CI, Expr *E) { - if (LangOpts.SYCLIsHost) - return; - if (!E->isValueDependent()) { // Validate that we have an integer constant expression and then store the // converted constant expression into the semantic attribute so that we @@ -3470,10 +3467,6 @@ void Sema::addSYCLIntelLoopFuseAttr(Decl *D, const AttributeCommonInfo &CI, if (checkSYCLIntelLoopFuseArgument(*this, CI, E)) return; - // Attribute should not be added during host compilation. - if (getLangOpts().SYCLIsHost) - return; - SYCLIntelLoopFuseAttr *NewAttr = mergeSYCLIntelLoopFuseAttr(D, CI, E); if (NewAttr) @@ -5717,9 +5710,6 @@ static bool checkForDuplicateAttribute(Sema &S, Decl *D, static void handleNoGlobalWorkOffsetAttr(Sema &S, Decl *D, const ParsedAttr &A) { - if (S.LangOpts.SYCLIsHost) - return; - checkForDuplicateAttribute(S, D, A); S.CheckDeprecatedSYCLAttributeSpelling(A); @@ -5736,9 +5726,6 @@ static void handleNoGlobalWorkOffsetAttr(Sema &S, Decl *D, /// Both are incompatible with the __register__ attribute. template static void handleIntelFPGAPumpAttr(Sema &S, Decl *D, const ParsedAttr &A) { - if (S.LangOpts.SYCLIsHost) - return; - checkForDuplicateAttribute(S, D, A); if (checkAttrMutualExclusion(S, D, A)) return; @@ -5759,10 +5746,6 @@ static void handleIntelFPGAPumpAttr(Sema &S, Decl *D, const ParsedAttr &A) { /// This is incompatible with the [[intelfpga::register]] attribute. static void handleIntelFPGAMemoryAttr(Sema &S, Decl *D, const ParsedAttr &AL) { - - if (S.LangOpts.SYCLIsHost) - return; - checkForDuplicateAttribute(S, D, AL); if (checkAttrMutualExclusion(S, D, AL)) return; @@ -5832,10 +5815,6 @@ static bool checkIntelFPGARegisterAttrCompatibility(Sema &S, Decl *D, /// Handle the [[intelfpga::register]] attribute. /// This is incompatible with most of the other memory attributes. static void handleIntelFPGARegisterAttr(Sema &S, Decl *D, const ParsedAttr &A) { - - if (S.LangOpts.SYCLIsHost) - return; - checkForDuplicateAttribute(S, D, A); if (checkIntelFPGARegisterAttrCompatibility(S, D, A)) return; @@ -5853,10 +5832,6 @@ static void handleIntelFPGARegisterAttr(Sema &S, Decl *D, const ParsedAttr &A) { template static void handleOneConstantPowerTwoValueAttr(Sema &S, Decl *D, const ParsedAttr &A) { - - if (S.LangOpts.SYCLIsHost) - return; - checkForDuplicateAttribute(S, D, A); if (checkAttrMutualExclusion(S, D, A)) return; @@ -5868,9 +5843,6 @@ static void handleOneConstantPowerTwoValueAttr(Sema &S, Decl *D, static void handleIntelFPGASimpleDualPortAttr(Sema &S, Decl *D, const ParsedAttr &AL) { - if (S.LangOpts.SYCLIsHost) - return; - checkForDuplicateAttribute(S, D, AL); if (checkAttrMutualExclusion(S, D, AL)) @@ -5888,9 +5860,6 @@ static void handleIntelFPGASimpleDualPortAttr(Sema &S, Decl *D, static void handleIntelFPGAMaxReplicatesAttr(Sema &S, Decl *D, const ParsedAttr &A) { - if (S.LangOpts.SYCLIsHost) - return; - checkForDuplicateAttribute(S, D, A); if (checkAttrMutualExclusion(S, D, A)) @@ -5908,9 +5877,6 @@ static void handleIntelFPGAMaxReplicatesAttr(Sema &S, Decl *D, static void handleIntelFPGAMergeAttr(Sema &S, Decl *D, const ParsedAttr &AL) { checkForDuplicateAttribute(S, D, AL); - if (S.LangOpts.SYCLIsHost) - return; - if (checkAttrMutualExclusion(S, D, AL)) return; @@ -6029,9 +5995,6 @@ void Sema::AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI, static void handleIntelFPGAPrivateCopiesAttr(Sema &S, Decl *D, const ParsedAttr &A) { - if (S.LangOpts.SYCLIsHost) - return; - checkForDuplicateAttribute(S, D, A); if (checkAttrMutualExclusion(S, D, A)) return; @@ -6043,9 +6006,6 @@ static void handleIntelFPGAPrivateCopiesAttr(Sema &S, Decl *D, static void handleIntelFPGAForcePow2DepthAttr(Sema &S, Decl *D, const ParsedAttr &A) { - if (S.LangOpts.SYCLIsHost) - return; - checkForDuplicateAttribute(S, D, A); if (checkAttrMutualExclusion(S, D, A)) diff --git a/clang/test/CodeGenSYCL/loop_fusion_host.cpp b/clang/test/CodeGenSYCL/loop_fusion_host.cpp index 5245855ebd62..98237d61a6db 100644 --- a/clang/test/CodeGenSYCL/loop_fusion_host.cpp +++ b/clang/test/CodeGenSYCL/loop_fusion_host.cpp @@ -1,5 +1,4 @@ // RUN: %clang_cc1 -fsycl -fsycl-is-host -triple -x86_64-unknown-linux-gnu -disable-llvm-passes -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -fsycl -fsycl-is-host -triple -x86_64-unknown-linux-gnu -disable-llvm-passes -verify -Wno-sycl-2017-compat -DDIAG %s template __attribute__((sycl_kernel)) void kernel(const Func &kernelFunc) { @@ -30,8 +29,3 @@ void foo() { kernel(f5); } // CHECK-NOT: !loop_fuse - -#if defined(DIAG) -int baz(); -[[intel::loop_fuse(baz())]] void func3(); // expected-error{{'loop_fuse' attribute requires an integer constant}} -#endif diff --git a/clang/utils/TableGen/ClangAttrEmitter.cpp b/clang/utils/TableGen/ClangAttrEmitter.cpp index da3f0db3c018..1fefd3c1a6c0 100644 --- a/clang/utils/TableGen/ClangAttrEmitter.cpp +++ b/clang/utils/TableGen/ClangAttrEmitter.cpp @@ -1992,10 +1992,15 @@ bool PragmaClangAttributeSupport::isAttributedSupported( return true; } -static std::string GenerateTestExpression(ArrayRef LangOpts) { +static std::string GenerateTestExpression(ArrayRef LangOpts, + bool IsAttrAccepted) { std::string Test; for (auto *E : LangOpts) { + bool SilentlyIgnore = E->getValueAsBit("SilentlyIgnore"); + if (SilentlyIgnore == IsAttrAccepted) + continue; + if (!Test.empty()) Test += " || "; @@ -2010,6 +2015,8 @@ static std::string GenerateTestExpression(ArrayRef LangOpts) { "non-empty 'Name' field ignored because 'CustomCode' was supplied"); } } else { + if (!IsAttrAccepted && SilentlyIgnore) + Test += "!"; Test += "LangOpts."; Test += E->getValueAsString("Name"); } @@ -2043,7 +2050,7 @@ PragmaClangAttributeSupport::generateStrictConformsTo(const Record &Attr, // rules if the specific language options are specified. std::vector LangOpts = Rule.getLangOpts(); OS << " MatchRules.push_back(std::make_pair(" << Rule.getEnumValue() - << ", /*IsSupported=*/" << GenerateTestExpression(LangOpts) + << ", /*IsSupported=*/" << GenerateTestExpression(LangOpts, true) << "));\n"; } } @@ -3635,13 +3642,13 @@ static void GenerateLangOptRequirements(const Record &R, if (LangOpts.empty()) return; - OS << "bool diagLangOpts(Sema &S, const ParsedAttr &Attr) "; + OS << "bool diagLangOpts(Sema &S, const ParsedAttr &PA) "; OS << "const override {\n"; - OS << " auto &LangOpts = S.LangOpts;\n"; - OS << " if (" << GenerateTestExpression(LangOpts) << ")\n"; + OS << " const auto &LangOpts = S.LangOpts;\n"; + OS << " if (" << GenerateTestExpression(LangOpts, true) << ")\n"; OS << " return true;\n\n"; - OS << " S.Diag(Attr.getLoc(), diag::warn_attribute_ignored) "; - OS << "<< Attr;\n"; + OS << " if (" << GenerateTestExpression(LangOpts, false) << ")\n"; + OS << " S.Diag(PA.getLoc(), diag::warn_attribute_ignored) << PA;\n"; OS << " return false;\n"; OS << "}\n\n"; }