diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index df7a7e6124f48..dabc6069ac33f 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -3785,9 +3785,6 @@ class OffloadingActionBuilder final { /// Flag to signal if the user requested device code split. bool DeviceCodeSplit = false; - /// Flag to signal if DAE optimization is turned on. - bool EnableDAE = false; - /// The SYCL actions for the current input. ActionList SYCLDeviceActions; @@ -4278,33 +4275,33 @@ class OffloadingActionBuilder final { // .--------------------------------------. // | PostLink | // .--------------------------------------. - // [.n] [.!na!s] [+*] [+*] - // | | | | - // | | .----------------. | - // | | |FileTableTform | | - // | | |(extract "Code")| | - // | | .----------------. | - // | | [-] | - // | | | | - // | [.a!s] [-*] | - // .-------------. .---------------------. | - // |finalizeNVPTX| | SPIRVTranslator | | - // .-------------. .---------------------. | - // | [.a!s] [-as] [-!a] | - // | | | | | - // | [.!s] [-s] | | - // | .----------------. | | - // | | BackendCompile | | | - // | .----------------. | | - // | [.!s] [-s] | | - // | | | | | - // | | [-a] [-!a] [+] - // | | .----------------. - // | | |FileTableTform | - // | | |(replace "Code")| - // | | .----------------. - // | | | - // [.n] [.!na!s] [+*] + // [.n] [+*] [+*] + // | | | + // | .-----------------. | + // | | FileTableTform | | + // | | (extract "Code")| | + // | .-----------------. | + // | [-] | + // | | | + // | [-*] | + // .-------------. .-------------------. | + // |finalizeNVPTX| | SPIRVTranslator | | + // .-------------. .-------------------. | + // | [-as] [-!a] | + // | | | | + // | [-s] | | + // | .----------------. | | + // | | BackendCompile | | | + // | .----------------. | | + // | [-s] | | + // | | | | + // | [-a] [-!a] [+] + // | .--------------------. + // | | FileTableTform | + // | | (replace "Code") | + // | .--------------------. + // | | + // [.n] [+*] // .--------------------------------------. // | OffloadWrapper | // .--------------------------------------. @@ -4351,10 +4348,8 @@ class OffloadingActionBuilder final { ActionList WrapperInputs; // post link is not optional - even if not splitting, always need to // process specialization constants - bool MultiFileActionDeps = !isSpirvAOT || DeviceCodeSplit || EnableDAE; - types::ID PostLinkOutType = isNVPTX || !MultiFileActionDeps - ? types::TY_LLVM_BC - : types::TY_Tempfiletable; + types::ID PostLinkOutType = + isNVPTX ? types::TY_LLVM_BC : types::TY_Tempfiletable; auto *PostLinkAction = C.MakeAction( FullDeviceLinkAction, PostLinkOutType); PostLinkAction->setRTSetsSpecConstants(!isAOT); @@ -4366,21 +4361,14 @@ class OffloadingActionBuilder final { } else { // For SPIRV-based targets - translate to SPIRV then optionally // compile ahead-of-time to native architecture - Action *SPIRVInput = PostLinkAction; constexpr char COL_CODE[] = "Code"; - - if (MultiFileActionDeps) { - auto *ExtractIRFilesAction = C.MakeAction( - PostLinkAction, types::TY_Tempfilelist); - // single column w/o title fits TY_Tempfilelist format - ExtractIRFilesAction->addExtractColumnTform(COL_CODE, - false /*drop titles*/); - SPIRVInput = ExtractIRFilesAction; - } - types::ID SPIRVOutType = - MultiFileActionDeps ? types::TY_Tempfilelist : types::TY_SPIRV; - Action *BuildCodeAction = - C.MakeAction(SPIRVInput, SPIRVOutType); + auto *ExtractIRFilesAction = C.MakeAction( + PostLinkAction, types::TY_Tempfilelist); + // single column w/o title fits TY_Tempfilelist format + ExtractIRFilesAction->addExtractColumnTform(COL_CODE, + false /*drop titles*/); + Action *BuildCodeAction = C.MakeAction( + ExtractIRFilesAction, types::TY_Tempfilelist); // After the Link, wrap the files before the final host link if (isSpirvAOT) { @@ -4412,14 +4400,11 @@ class OffloadingActionBuilder final { BuildCodeAction = C.MakeAction(BEInputs, OutType); } - if (MultiFileActionDeps) { - ActionList TformInputs{PostLinkAction, BuildCodeAction}; - auto *ReplaceFilesAction = C.MakeAction( - TformInputs, types::TY_Tempfiletable); - ReplaceFilesAction->addReplaceColumnTform(COL_CODE, COL_CODE); - BuildCodeAction = ReplaceFilesAction; - } - WrapperInputs.push_back(BuildCodeAction); + ActionList TformInputs{PostLinkAction, BuildCodeAction}; + auto *ReplaceFilesAction = C.MakeAction( + TformInputs, types::TY_Tempfiletable); + ReplaceFilesAction->addReplaceColumnTform(COL_CODE, COL_CODE); + WrapperInputs.push_back(ReplaceFilesAction); } // After the Link, wrap the files before the final host link auto *DeviceWrappingAction = C.MakeAction( @@ -4523,9 +4508,6 @@ class OffloadingActionBuilder final { WrapDeviceOnlyBinary = Args.hasArg(options::OPT_fsycl_link_EQ); auto *DeviceCodeSplitArg = Args.getLastArg(options::OPT_fsycl_device_code_split_EQ); - EnableDAE = - Args.hasFlag(options::OPT_fsycl_dead_args_optimization, - options::OPT_fno_sycl_dead_args_optimization, false); // -fsycl-device-code-split is an alias to // -fsycl-device-code-split=per_source DeviceCodeSplit = DeviceCodeSplitArg && diff --git a/clang/test/Driver/sycl-intelfpga-aoco-win.cpp b/clang/test/Driver/sycl-intelfpga-aoco-win.cpp index 143dc4a70a197..7ce88b485f2e9 100755 --- a/clang/test/Driver/sycl-intelfpga-aoco-win.cpp +++ b/clang/test/Driver/sycl-intelfpga-aoco-win.cpp @@ -27,15 +27,17 @@ // CHK-FPGA-AOCO-PHASES-WIN: 13: input, "[[INPUTA]]", archive // CHK-FPGA-AOCO-PHASES-WIN: 14: clang-offload-unbundler, {13}, archive // CHK-FPGA-AOCO-PHASES-WIN: 15: linker, {5, 12, 14}, ir, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 16: sycl-post-link, {15}, ir, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 17: llvm-spirv, {16}, spirv, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 18: input, "[[INPUTA]]", archive -// CHK-FPGA-AOCO-PHASES-WIN: 19: clang-offload-unbundler, {18}, fpga_dep_list -// CHK-FPGA-AOCO-PHASES-WIN: 20: input, "[[INPUTA]]", fpga_aoco -// CHK-FPGA-AOCO-PHASES-WIN: 21: clang-offload-unbundler, {20}, fpga_aoco -// CHK-FPGA-AOCO-PHASES-WIN: 22: backend-compiler, {17, 19, 21}, fpga_aocx, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 23: clang-offload-wrapper, {22}, object, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 24: offload, "host-sycl (x86_64-pc-windows-msvc)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {23}, image +// CHK-FPGA-AOCO-PHASES-WIN: 16: sycl-post-link, {15}, tempfiletable, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 17: file-table-tform, {16}, tempfilelist, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 18: llvm-spirv, {17}, tempfilelist, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 19: input, "[[INPUTA]]", archive +// CHK-FPGA-AOCO-PHASES-WIN: 20: clang-offload-unbundler, {19}, fpga_dep_list +// CHK-FPGA-AOCO-PHASES-WIN: 21: input, "[[INPUTA]]", fpga_aoco +// CHK-FPGA-AOCO-PHASES-WIN: 22: clang-offload-unbundler, {21}, fpga_aoco +// CHK-FPGA-AOCO-PHASES-WIN: 23: backend-compiler, {18, 20, 22}, fpga_aocx, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 24: file-table-tform, {16, 23}, tempfiletable, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 25: clang-offload-wrapper, {24}, object, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 26: offload, "host-sycl (x86_64-pc-windows-msvc)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {25}, image /// aoco test, checking tools // RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga -foffload-static-lib=%t_aoco.a -Xshardware -### %s 2>&1 \ @@ -44,12 +46,12 @@ // RUN: | FileCheck -check-prefix=CHK-FPGA-AOCO %s // CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=a" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUTLIB:.+\.a]]" "-outputs=[[OUTLIB:.+\.a]]" "-unbundle" // CHK-FPGA-AOCO: llvm-link{{.*}} "[[OUTLIB]]" "-o" "[[LINKEDBC:.+\.bc]]" -// CHK-FPGA-AOCO: sycl-post-link -// CHK-FPGA-AOCO-NOT: -split-esimd -// CHK-FPGA-AOCO: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]" -// CHK-FPGA-AOCO: llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.spv]]" {{.*}} "[[PLINKEDBC]]" +// CHK-FPGA-AOCO: sycl-post-link{{.*}} "-split-esimd"{{.*}} "-O2" "-spec-const=default" "-o" "[[SPLTABLE:.+\.table]]" "[[LINKEDBC]]" +// CHK-FPGA-AOCO: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[SPLTABLE]]" +// CHK-FPGA-AOCO: llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.txt]]" {{.*}} "[[TABLEOUT]]" // CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=aoo" "-targets=sycl-fpga_aoco-intel-unknown-sycldevice" "-inputs=[[INPUTLIB]]" "-outputs=[[AOCOLIST:.+\.txt]]" "-unbundle" // CHK-FPGA-AOCO: aoc{{.*}} "-o" "[[AOCXOUT:.+\.aocx]]" "[[TARGSPV]]" "-library-list=[[AOCOLIST]]" "-sycl" -// CHK-FPGA-AOCO: clang-offload-wrapper{{.*}} "-o=[[FINALBC:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCXOUT]]" +// CHK-FPGA-AOCO: file-table-tform{{.*}} "-o" "[[TABLEOUT2:.+\.table]]" "[[SPLTABLE]]" "[[AOCXOUT]]" +// CHK-FPGA-AOCO: clang-offload-wrapper{{.*}} "-o=[[FINALBC:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT2]]" // CHK-FPGA-AOCO: llc{{.*}} "-filetype=obj" "-o" "[[FINALOBJW:.+\.obj]]" "[[FINALBC]]" // CHK-FPGA-AOCO: link.exe{{.*}} "{{.*}}[[INPUTLIB]]" {{.*}} "[[FINALOBJW]]" diff --git a/clang/test/Driver/sycl-intelfpga-aoco.cpp b/clang/test/Driver/sycl-intelfpga-aoco.cpp index c83194f90694e..f28a0aad971fe 100755 --- a/clang/test/Driver/sycl-intelfpga-aoco.cpp +++ b/clang/test/Driver/sycl-intelfpga-aoco.cpp @@ -31,15 +31,17 @@ // CHK-FPGA-AOCO-PHASES: 13: input, "[[INPUTA]]", archive // CHK-FPGA-AOCO-PHASES: 14: clang-offload-unbundler, {13}, archive // CHK-FPGA-AOCO-PHASES: 15: linker, {5, 12, 14}, ir, (device-sycl) -// CHK-FPGA-AOCO-PHASES: 16: sycl-post-link, {15}, ir, (device-sycl) -// CHK-FPGA-AOCO-PHASES: 17: llvm-spirv, {16}, spirv, (device-sycl) -// CHK-FPGA-AOCO-PHASES: 18: input, "[[INPUTA]]", archive -// CHK-FPGA-AOCO-PHASES: 19: clang-offload-unbundler, {18}, fpga_dep_list -// CHK-FPGA-AOCO-PHASES: 20: input, "[[INPUTA]]", fpga_aoco -// CHK-FPGA-AOCO-PHASES: 21: clang-offload-unbundler, {20}, fpga_aoco -// CHK-FPGA-AOCO-PHASES: 22: backend-compiler, {17, 19, 21}, fpga_aocx, (device-sycl) -// CHK-FPGA-AOCO-PHASES: 23: clang-offload-wrapper, {22}, object, (device-sycl) -// CHK-FPGA-AOCO-PHASES: 24: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {23}, image +// CHK-FPGA-AOCO-PHASES: 16: sycl-post-link, {15}, tempfiletable, (device-sycl) +// CHK-FPGA-AOCO-PHASES: 17: file-table-tform, {16}, tempfilelist, (device-sycl) +// CHK-FPGA-AOCO-PHASES: 18: llvm-spirv, {17}, tempfilelist, (device-sycl) +// CHK-FPGA-AOCO-PHASES: 19: input, "[[INPUTA]]", archive +// CHK-FPGA-AOCO-PHASES: 20: clang-offload-unbundler, {19}, fpga_dep_list +// CHK-FPGA-AOCO-PHASES: 21: input, "[[INPUTA]]", fpga_aoco +// CHK-FPGA-AOCO-PHASES: 22: clang-offload-unbundler, {21}, fpga_aoco +// CHK-FPGA-AOCO-PHASES: 23: backend-compiler, {18, 20, 22}, fpga_aocx, (device-sycl) +// CHK-FPGA-AOCO-PHASES: 24: file-table-tform, {16, 23}, tempfiletable, (device-sycl) +// CHK-FPGA-AOCO-PHASES: 25: clang-offload-wrapper, {24}, object, (device-sycl) +// CHK-FPGA-AOCO-PHASES: 26: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {25}, image /// FPGA AOCO Windows phases check // RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga -foffload-static-lib=%t_aoco_cl.a %s -ccc-print-phases 2>&1 \ @@ -60,15 +62,17 @@ // CHK-FPGA-AOCO-PHASES-WIN: 13: input, "[[INPUTA]]", archive // CHK-FPGA-AOCO-PHASES-WIN: 14: clang-offload-unbundler, {13}, archive // CHK-FPGA-AOCO-PHASES-WIN: 15: linker, {5, 12, 14}, ir, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 16: sycl-post-link, {15}, ir, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 17: llvm-spirv, {16}, spirv, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 18: input, "[[INPUTA]]", archive -// CHK-FPGA-AOCO-PHASES-WIN: 19: clang-offload-unbundler, {18}, fpga_dep_list -// CHK-FPGA-AOCO-PHASES-WIN: 20: input, "[[INPUTA]]", fpga_aoco -// CHK-FPGA-AOCO-PHASES-WIN: 21: clang-offload-unbundler, {20}, fpga_aoco -// CHK-FPGA-AOCO-PHASES-WIN: 22: backend-compiler, {17, 19, 21}, fpga_aocx, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 23: clang-offload-wrapper, {22}, object, (device-sycl) -// CHK-FPGA-AOCO-PHASES-WIN: 24: offload, "host-sycl (x86_64-pc-windows-msvc)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {23}, image +// CHK-FPGA-AOCO-PHASES-WIN: 16: sycl-post-link, {15}, tempfiletable, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 17: file-table-tform, {16}, tempfilelist, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 18: llvm-spirv, {17}, tempfilelist, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 19: input, "[[INPUTA]]", archive +// CHK-FPGA-AOCO-PHASES-WIN: 20: clang-offload-unbundler, {19}, fpga_dep_list +// CHK-FPGA-AOCO-PHASES-WIN: 21: input, "[[INPUTA]]", fpga_aoco +// CHK-FPGA-AOCO-PHASES-WIN: 22: clang-offload-unbundler, {21}, fpga_aoco +// CHK-FPGA-AOCO-PHASES-WIN: 23: backend-compiler, {18, 20, 22}, fpga_aocx, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 24: file-table-tform, {16, 23}, tempfiletable, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 25: clang-offload-wrapper, {24}, object, (device-sycl) +// CHK-FPGA-AOCO-PHASES-WIN: 26: offload, "host-sycl (x86_64-pc-windows-msvc)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {25}, image /// aoco test, checking tools // RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware -foffload-static-lib=%t_aoco.a -### %s 2>&1 \ @@ -81,13 +85,13 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO,CHK-FPGA-AOCO-WIN %s // CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=a" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUTLIB:.+\.a]]" "-outputs=[[OUTLIB:.+\.a]]" "-unbundle" // CHK-FPGA-AOCO: llvm-link{{.*}} "[[OUTLIB]]" "-o" "[[LINKEDBC:.+\.bc]]" -// CHK-FPGA-AOCO: sycl-post-link -// CHK-FPGA-AOCO-NOT: "-split-esimd" -// CHK-FPGA-AOCO: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[PLINKEDBC:.+\.bc]]" "[[LINKEDBC]]" -// CHK-FPGA-AOCO: llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.spv]]" {{.*}} "[[PLINKEDBC]]" +// CHK-FPGA-AOCO: sycl-post-link{{.*}} "-split-esimd"{{.*}} "-O2" "-spec-const=default" "-o" "[[SPLTABLE:.+\.table]]" "[[LINKEDBC]]" +// CHK-FPGA-AOCO: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[SPLTABLE]]" +// CHK-FPGA-AOCO: llvm-spirv{{.*}} "-o" "[[TARGSPV:.+\.txt]]" {{.*}} "[[TABLEOUT]]" // CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=aoo" "-targets=sycl-fpga_aoco-intel-unknown-sycldevice" "-inputs=[[INPUTLIB]]" "-outputs=[[AOCOLIST:.+\.txt]]" "-unbundle" // CHK-FPGA-AOCO: aoc{{.*}} "-o" "[[AOCXOUT:.+\.aocx]]" "[[TARGSPV]]" "-library-list=[[AOCOLIST]]" "-sycl" -// CHK-FPGA-AOCO: clang-offload-wrapper{{.*}} "-o=[[FINALBC:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCXOUT]]" +// CHK-FPGA-AOCO: file-table-tform{{.*}} "-o" "[[TABLEOUT2:.+\.table]]" "[[SPLTABLE]]" "[[AOCXOUT]]" +// CHK-FPGA-AOCO: clang-offload-wrapper{{.*}} "-o=[[FINALBC:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT2]]" // CHK-FPGA-AOCO-LIN: llc{{.*}} "-filetype=obj" "-o" "[[FINALOBJL:.+\.o]]" "[[FINALBC]]" // CHK-FPGA-AOCO-WIN: llc{{.*}} "-filetype=obj" "-o" "[[FINALOBJW:.+\.obj]]" "[[FINALBC]]" // CHK-FPGA-AOCO-LIN: ld{{.*}} "[[INPUTLIB]]" {{.*}} "[[FINALOBJL]]" diff --git a/clang/test/Driver/sycl-intelfpga-static-lib-win.cpp b/clang/test/Driver/sycl-intelfpga-static-lib-win.cpp index 1ab60d6f40074..b26c806af366c 100644 --- a/clang/test/Driver/sycl-intelfpga-static-lib-win.cpp +++ b/clang/test/Driver/sycl-intelfpga-static-lib-win.cpp @@ -20,13 +20,15 @@ // CHECK_PHASES: 4: input, "[[INPUT]]", archive // CHECK_PHASES: 5: clang-offload-unbundler, {4}, archive // CHECK_PHASES: 6: linker, {3, 5}, ir, (device-sycl) -// CHECK_PHASES: 7: sycl-post-link, {6}, ir, (device-sycl) -// CHECK_PHASES: 8: llvm-spirv, {7}, spirv, (device-sycl) -// CHECK_PHASES: 9: input, "[[INPUT]]", archive -// CHECK_PHASES: 10: clang-offload-unbundler, {9}, fpga_dep_list -// CHECK_PHASES: 11: backend-compiler, {8, 10}, fpga_aocx, (device-sycl) -// CHECK_PHASES: 12: clang-offload-wrapper, {11}, object, (device-sycl) -// CHECK_PHASES: 13: offload, "host-sycl (x86_64-pc-windows-msvc)" {1}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {12}, image +// CHECK_PHASES: 7: sycl-post-link, {6}, tempfiletable, (device-sycl) +// CHECK_PHASES: 8: file-table-tform, {7}, tempfilelist, (device-sycl) +// CHECK_PHASES: 9: llvm-spirv, {8}, tempfilelist, (device-sycl) +// CHECK_PHASES: 10: input, "[[INPUT]]", archive +// CHECK_PHASES: 11: clang-offload-unbundler, {10}, fpga_dep_list +// CHECK_PHASES: 12: backend-compiler, {9, 11}, fpga_aocx, (device-sycl) +// CHECK_PHASES: 13: file-table-tform, {7, 12}, tempfiletable, (device-sycl) +// CHECK_PHASES: 14: clang-offload-wrapper, {13}, object, (device-sycl) +// CHECK_PHASES: 15: offload, "host-sycl (x86_64-pc-windows-msvc)" {1}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {14}, image /// Check for unbundle and use of deps in static lib // RUN: %clang_cl --target=x86_64-pc-windows-msvc -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware %t.lib -### 2>&1 \ diff --git a/clang/test/Driver/sycl-intelfpga-static-lib.cpp b/clang/test/Driver/sycl-intelfpga-static-lib.cpp index 22baf5675b3e5..b45215b985466 100644 --- a/clang/test/Driver/sycl-intelfpga-static-lib.cpp +++ b/clang/test/Driver/sycl-intelfpga-static-lib.cpp @@ -19,13 +19,15 @@ // CHECK_PHASES: 4: input, "[[INPUT]]", archive // CHECK_PHASES: 5: clang-offload-unbundler, {4}, archive // CHECK_PHASES: 6: linker, {3, 5}, ir, (device-sycl) -// CHECK_PHASES: 7: sycl-post-link, {6}, ir, (device-sycl) -// CHECK_PHASES: 8: llvm-spirv, {7}, spirv, (device-sycl) -// CHECK_PHASES: 9: input, "[[INPUT]]", archive -// CHECK_PHASES: 10: clang-offload-unbundler, {9}, fpga_dep_list -// CHECK_PHASES: 11: backend-compiler, {8, 10}, fpga_aocx, (device-sycl) -// CHECK_PHASES: 12: clang-offload-wrapper, {11}, object, (device-sycl) -// CHECK_PHASES: 13: offload, "host-sycl (x86_64-unknown-linux-gnu)" {1}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {12}, image +// CHECK_PHASES: 7: sycl-post-link, {6}, tempfiletable, (device-sycl) +// CHECK_PHASES: 8: file-table-tform, {7}, tempfilelist, (device-sycl) +// CHECK_PHASES: 9: llvm-spirv, {8}, tempfilelist, (device-sycl) +// CHECK_PHASES: 10: input, "[[INPUT]]", archive +// CHECK_PHASES: 11: clang-offload-unbundler, {10}, fpga_dep_list +// CHECK_PHASES: 12: backend-compiler, {9, 11}, fpga_aocx, (device-sycl) +// CHECK_PHASES: 13: file-table-tform, {7, 12}, tempfiletable, (device-sycl) +// CHECK_PHASES: 14: clang-offload-wrapper, {13}, object, (device-sycl) +// CHECK_PHASES: 15: offload, "host-sycl (x86_64-unknown-linux-gnu)" {1}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {14}, image /// Check for unbundle and use of deps in static lib // RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware %t.a -### 2>&1 \ diff --git a/clang/test/Driver/sycl-offload-intelfpga-emu.cpp b/clang/test/Driver/sycl-offload-intelfpga-emu.cpp index 93c3e5055179a..6c55f3b8a99af 100644 --- a/clang/test/Driver/sycl-offload-intelfpga-emu.cpp +++ b/clang/test/Driver/sycl-offload-intelfpga-emu.cpp @@ -13,11 +13,13 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK,CHK-FPGA-IMAGE %s // CHK-FPGA-LINK: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUT:.+\.o]]" "-outputs=[[OUTPUT1:.+\.o]]" "-unbundle" // CHK-FPGA-LINK: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" -// CHK-FPGA-LINK: sycl-post-link{{.*}} "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]" -// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version={{.*}}"{{.*}} "[[OUTPUT2]]" +// CHK-FPGA-LINK: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]" +// CHK-FPGA-LINK: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" +// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" // CHK-FPGA-EARLY: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocr]]" "--bo=-g" // CHK-FPGA-IMAGE: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]" "--bo=-g" -// CHK-FPGA-LINK: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" {{.*}} "-kind=sycl" +// CHK-FPGA-LINK: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]" +// CHK-FPGA-LINK: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]" // CHK-FPGA-LINK: llc{{.*}} "-o" "[[OBJOUTDEV:.+\.o]]" "[[WRAPOUT]]" // CHK-FPGA-EARLY: clang-offload-wrapper{{.*}} "-host" "x86_64-unknown-linux-gnu" "-o" "[[WRAPOUTHOST:.+\.bc]]" "-kind=host" // CHK-FPGA-EARLY-NOT: clang{{.*}} "-triple" "x86_64-unknown-linux-gnu" {{.*}} "-O2" @@ -33,10 +35,12 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-WIN %s // CHK-FPGA-LINK-WIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.obj]]" "-outputs=[[OUTPUT1:.+\.obj]]" "-unbundle" // CHK-FPGA-LINK-WIN: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" -// CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]" -// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version={{.*}}"{{.*}} "[[OUTPUT2]]" -// CHK-FPGA-LINK-WIN: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT5:.+\.aocr]]" "--bo=-g" -// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" +// CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]" +// CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" +// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" +// CHK-FPGA-LINK-WIN: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocr]]" "--bo=-g" +// CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]" +// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]" // CHK-FPGA-LINK-WIN: llc{{.*}} "-o" "[[OBJOUTDEV:.+\.obj]]" "[[WRAPOUT]]" // CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o" "[[WRAPOUTHOST:.+\.bc]]" "-kind=host" // CHK-FPGA-LINK-WIN: clang{{.*}} "-o" "[[OBJOUT:.+\.obj]]" {{.*}} "[[WRAPOUTHOST]]" @@ -85,12 +89,14 @@ // CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK:.+\.o]]" "[[OUTPUT_AOCX_BC]]" // CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=host-x86_64-unknown-linux-gnu,sycl-spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-outputs=[[FINALLINK2:.+\.o]],[[OUTPUT1:.+\.o]]" "-unbundle" // CHK-FPGA: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_BC:.+\.bc]]" -// CHK-FPGA: sycl-post-link{{.*}} "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT3_BC:.+\.bc]]" "[[OUTPUT2_BC]]" -// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.spv]]" "-spirv-max-version={{.*}}"{{.*}} "[[OUTPUT3_BC]]" +// CHK-FPGA: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_BC]]" +// CHK-FPGA: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" +// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" // CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-fpga_dep" {{.*}} "-outputs=[[DEPFILE:.+\.d]]" "-unbundle" -// CHK-FPGA: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT5]]" "-ir=[[OUTPUT6:.+\.aocx]]" "--bo=-g" -// CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT7:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga" "-kind=sycl" "[[OUTPUT6]]" -// CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK3:.+\.o]]" "[[OUTPUT7]]" +// CHK-FPGA: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]" "--bo=-g" +// CHK-FPGA: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]" +// CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]" +// CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK3:.+\.o]]" "[[WRAPOUT]]" // CHK-FPGA: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" {{.*}} "-outputs=[[FINALLINK4:.+\.txt]]" "-unbundle" // CHK-FPGA: {{link|ld}}{{.*}} "@[[FINALLINK4]]" "[[FINALLINK2]]" "[[FINALLINK]]" "[[FINALLINK3]]" @@ -137,11 +143,13 @@ // CHK-FPGA-AOCX-SRC: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.(o|obj)]]" "[[WRAPOUT]]" // CHK-FPGA-AOCX-SRC: clang{{.*}} "-cc1" {{.*}} "-fsycl-is-device" {{.*}} "-o" "[[DEVICEBC:.+\.bc]]" // CHK-FPGA-AOCX-SRC: llvm-link{{.*}} "[[DEVICEBC]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings" -// CHK-FPGA-AOCX-SRC: sycl-post-link{{.*}} "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]] -// CHK-FPGA-AOCX-SRC: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.spv]]" {{.*}} "[[POSTLINKOUT]]" -// CHK-FPGA-AOCX-SRC: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[LLVMSPVOUT]]" "-ir=[[AOCOUT:.+\.aocx]]" "--bo=-g" -// CHK-FPGA-AOCX-SRC: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCOUT]]" -// CHK-FPGA-AOCX-SRC: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUTSRC:.+\.(o|obj)]]" "[[WRAPOUTSRC]]" +// CHK-FPGA-AOCX-SRC: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[LLVMLINKOUT]]" +// CHK-FPGA-AOCX-SRC: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" +// CHK-FPGA-AOCX-SRC: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" +// CHK-FPGA-AOCX-SRC: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]" "--bo=-g" +// CHK-FPGA-AOCX-SRC: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]" +// CHK-FPGA-AOCX-SRC: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]" +// CHK-FPGA-AOCX-SRC: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUTSRC:.+\.(o|obj)]]" "[[WRAPOUT]]" // CHK-FPGA-AOCX-SRC: clang{{.*}} "-fsycl-is-host" {{.*}} "-o" "[[HOSTOBJ:.+\.(o|obj)]]" // CHK-FPGA-AOCX-SRC-LIN: ld{{.*}} "[[HOSTOBJ]]" "[[LIBINPUT]]" "[[LLCOUT]]" "[[LLCOUTSRC]]" // CHK-FPGA-AOCX-SRC-WIN: link{{.*}} "[[HOSTOBJ]]" "[[LIBINPUT]]" "[[LLCOUT]]" "[[LLCOUTSRC]]" @@ -158,10 +166,12 @@ // CHK-FPGA-AOCX-OBJ: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.(o|obj)]]" "[[WRAPOUT]]" // CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=o" {{.*}} "-outputs=[[HOSTOBJ:.+\.(o|obj)]],[[DEVICEOBJ:.+\.(o|obj)]]" "-unbundle" // CHK-FPGA-AOCX-OBJ: llvm-link{{.*}} "[[DEVICEOBJ]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings" -// CHK-FPGA-AOCX-OBJ: sycl-post-link{{.*}} "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]] -// CHK-FPGA-AOCX-OBJ: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.spv]]" {{.*}} "[[POSTLINKOUT]]" -// CHK-FPGA-AOCX-OBJ: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[LLVMSPVOUT]]" "-ir=[[AOCOUT:.+\.aocx]]" "--bo=-g" -// CHK-FPGA-AOCX-OBJ: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCOUT]]" +// CHK-FPGA-AOCX-OBJ: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[LLVMLINKOUT]]" +// CHK-FPGA-AOCX-OBJ: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" +// CHK-FPGA-AOCX-OBJ: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" +// CHK-FPGA-AOCX-OBJ: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]" "--bo=-g" +// CHK-FPGA-AOCX-OBJ: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]" +// CHK-FPGA-AOCX-OBJ: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+\.bc]]" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]" // CHK-FPGA-AOCX-OBJ: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUTSRC:.+\.(o|obj)]]" "[[WRAPOUTSRC]]" // CHK-FPGA-AOCX-OBJ-LIN: ld{{.*}} "[[HOSTOBJ]]" "[[LIBINPUT]]" "[[LLCOUT]]" "[[LLCOUTSRC]]" // CHK-FPGA-AOCX-OBJ-WIN: link{{.*}} "[[HOSTOBJ]]" "[[LIBINPUT]]" "[[LLCOUT]]" "[[LLCOUTSRC]]" @@ -186,11 +196,13 @@ // CHK-FPGA-LINK-SRC: 11: assembler, {10}, object, (host-sycl) // CHK-FPGA-LINK-SRC: 12: linker, {11}, archive, (host-sycl) // CHK-FPGA-LINK-SRC: 13: linker, {4}, ir, (device-sycl) -// CHK-FPGA-LINK-SRC: 14: sycl-post-link, {13}, ir, (device-sycl) -// CHK-FPGA-LINK-SRC: 15: llvm-spirv, {14}, spirv, (device-sycl) -// CHK-FPGA-LINK-SRC: 16: backend-compiler, {15}, fpga_aocr_emu, (device-sycl) -// CHK-FPGA-LINK-SRC: 17: clang-offload-wrapper, {16}, object, (device-sycl) -// CHK-FPGA-LINK-SRC: 18: offload, "host-sycl (x86_64-unknown-linux-gnu)" {12}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {17}, archive +// CHK-FPGA-LINK-SRC: 14: sycl-post-link, {13}, tempfiletable, (device-sycl) +// CHK-FPGA-LINK-SRC: 15: file-table-tform, {14}, tempfilelist, (device-sycl) +// CHK-FPGA-LINK-SRC: 16: llvm-spirv, {15}, tempfilelist, (device-sycl) +// CHK-FPGA-LINK-SRC: 17: backend-compiler, {16}, fpga_aocr_emu, (device-sycl) +// CHK-FPGA-LINK-SRC: 18: file-table-tform, {14, 17}, tempfiletable, (device-sycl) +// CHK-FPGA-LINK-SRC: 19: clang-offload-wrapper, {18}, object, (device-sycl) +// CHK-FPGA-LINK-SRC: 20: offload, "host-sycl (x86_64-unknown-linux-gnu)" {12}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {19}, archive /// Check the warning's emission for conflicting emulation/hardware (AOCX) // RUN: touch %t_aocx.a diff --git a/clang/test/Driver/sycl-offload-intelfpga.cpp b/clang/test/Driver/sycl-offload-intelfpga.cpp index 6c06cef7f064c..36db2ae4c94e9 100644 --- a/clang/test/Driver/sycl-offload-intelfpga.cpp +++ b/clang/test/Driver/sycl-offload-intelfpga.cpp @@ -32,10 +32,9 @@ // CHK-FPGA-LINK: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUT:.+\.o]]" "-outputs=[[OUTPUT1:.+\.o]]" "-unbundle" // CHK-FPGA-LINK-NOT: clang-offload-bundler{{.*}} // CHK-FPGA-LINK: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" -// CHK-FPGA-LINK: sycl-post-link -// CHK-FPGA-LINK-NOT: -split-esimd -// CHK-FPGA-LINK: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]" -// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version={{.*}}"{{.*}} "[[OUTPUT2]]" +// CHK-FPGA-LINK: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]" +// CHK-FPGA-LINK: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" +// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" // CHK-FPGA-EARLY: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl" // CHK-FPGA-IMAGE: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocx]]" "[[OUTPUT3]]" "-sycl" // CHK-FPGA-LINK: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" {{.*}} "-kind=sycl" @@ -66,10 +65,9 @@ // CHK-FPGA-LINK-WIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.obj]]" "-outputs=[[OUTPUT1:.+\.obj]]" "-unbundle" // CHK-FPGA-LINK-WIN-NOT: clang-offload-bundler{{.*}} // CHK-FPGA-LINK-WIN: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" -// CHK-FPGA-LINK-WIN: sycl-post-link -// CHK-FPGA-LINK-WIN-NOT: -split-esimd -// CHK-FPGA-LINK-WIN: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.bc]]" "[[OUTPUT2_1]]" -// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version={{.*}}"{{.*}} "[[OUTPUT2]]" +// CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]" +// CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" +// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" // CHK-FPGA-LINK-WIN: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl" // CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" // CHK-FPGA-LINK-WIN: llc{{.*}} "-o" "[[OBJOUTDEV:.+\.obj]]" "[[WRAPOUT]]" @@ -131,13 +129,13 @@ // CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK:.+\.o]]" "[[OUTPUT_AOCX_BC]]" // CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=host-x86_64-unknown-linux-gnu,sycl-spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-outputs=[[FINALLINK2:.+\.o]],[[OUTPUT1:.+\.o]]" "-unbundle" // CHK-FPGA: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_BC:.+\.bc]]" -// CHK-FPGA: sycl-post-link -// CHK-FPGA-NOT: -split-esimd -// CHK-FPGA: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[OUTPUT3_BC:.+\.bc]]" "[[OUTPUT2_BC]]" -// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.spv]]" "-spirv-max-version={{.*}}"{{.*}} "[[OUTPUT3_BC]]" +// CHK-FPGA: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT3_TABLE:.+\.table]]" "[[OUTPUT2_BC]]" +// CHK-FPGA: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT3_TABLE]]" +// CHK-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT5:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" // CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-fpga_dep" {{.*}} "-outputs=[[DEPFILE:.+\.d]]" "-unbundle" // CHK-FPGA: aoc{{.*}} "-o" "[[OUTPUT6:.+\.aocx]]" "[[OUTPUT5]]" "-sycl" "-dep-files=[[DEPFILE]]" -// CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT7:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga" "-kind=sycl" "[[OUTPUT6]]" +// CHK-FPGA: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT3_TABLE]]" "[[OUTPUT6]]" +// CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT7:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT2]]" // CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK3:.+\.o]]" "[[OUTPUT7]]" // CHK-FPGA: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" {{.*}} "-outputs=[[FINALLINK4:.+\.txt]]" "-unbundle" // CHK-FPGA: {{link|ld}}{{.*}} "@[[FINALLINK4]]" "[[FINALLINK2]]" "[[FINALLINK]]" "[[FINALLINK3]]" @@ -191,12 +189,12 @@ // CHK-FPGA-AOCX-SRC: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.(o|obj)]]" "[[WRAPOUT]]" // CHK-FPGA-AOCX-SRC: clang{{.*}} "-cc1" {{.*}} "-fsycl-is-device" {{.*}} "-o" "[[DEVICEBC:.+\.bc]]" // CHK-FPGA-AOCX-SRC: llvm-link{{.*}} "[[DEVICEBC]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings" -// CHK-FPGA-AOCX-SRC: sycl-post-link -// CHK-FPGA-AOCX-SRC-NOT: -split-esimd -// CHK-FPGA-AOCX-SRC: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]] -// CHK-FPGA-AOCX-SRC: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.spv]]" {{.*}} "[[POSTLINKOUT]]" +// CHK-FPGA-AOCX-SRC: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.table]]" "[[LLVMLINKOUT]] +// CHK-FPGA-AOCX-SRC: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[POSTLINKOUT]]" +// CHK-FPGA-AOCX-SRC: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.txt]]" {{.*}} "[[TABLEOUT]]" // CHK-FPGA-AOCX-SRC: aoc{{.*}} "-o" "[[AOCOUT:.+\.aocx]]" "[[LLVMSPVOUT]]" "-sycl" -// CHK-FPGA-AOCX-SRC: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCOUT]]" +// CHK-FPGA-AOCX-SRC: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[POSTLINKOUT]]" "[[AOCOUT]]" +// CHK-FPGA-AOCX-SRC: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT2]]" // CHK-FPGA-AOCX-SRC: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUTSRC:.+\.(o|obj)]]" "[[WRAPOUTSRC]]" // CHK-FPGA-AOCX-SRC: clang{{.*}} "-fsycl-is-host" {{.*}} "-o" "[[HOSTOBJ:.+\.(o|obj)]]" // CHK-FPGA-AOCX-SRC-LIN: ld{{.*}} "[[HOSTOBJ]]" "[[LIBINPUT]]" "[[LLCOUT]]" "[[LLCOUTSRC]]" @@ -214,12 +212,12 @@ // CHK-FPGA-AOCX-OBJ: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.(o|obj)]]" "[[WRAPOUT]]" // CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=o" {{.*}} "-outputs=[[HOSTOBJ:.+\.(o|obj)]],[[DEVICEOBJ:.+\.(o|obj)]]" "-unbundle" // CHK-FPGA-AOCX-OBJ: llvm-link{{.*}} "[[DEVICEOBJ]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings" -// CHK-FPGA-AOCX-OBJ: sycl-post-link -// CHK-FPGA-AOCX-OBJ-NOT: -split-esimd -// CHK-FPGA-AOCX-OBJ: "-ir-output-only" "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.bc]]" "[[LLVMLINKOUT]] -// CHK-FPGA-AOCX-OBJ: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.spv]]" {{.*}} "[[POSTLINKOUT]]" +// CHK-FPGA-AOCX-OBJ: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.table]]" "[[LLVMLINKOUT]] +// CHK-FPGA-AOCX-OBJ: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[POSTLINKOUT]]" +// CHK-FPGA-AOCX-OBJ: llvm-spirv{{.*}} "-o" "[[LLVMSPVOUT:.+\.txt]]" {{.*}} "[[TABLEOUT]]" // CHK-FPGA-AOCX-OBJ: aoc{{.*}} "-o" "[[AOCOUT:.+\.aocx]]" "[[LLVMSPVOUT]]" "-sycl" -// CHK-FPGA-AOCX-OBJ: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "[[AOCOUT]]" +// CHK-FPGA-AOCX-OBJ: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[POSTLINKOUT]]" "[[AOCOUT]]" +// CHK-FPGA-AOCX-OBJ: clang-offload-wrapper{{.*}} "-o=[[WRAPOUTSRC:.+.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT2]]" // CHK-FPGA-AOCX-OBJ: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUTSRC:.+\.(o|obj)]]" "[[WRAPOUTSRC]]" // CHK-FPGA-AOCX-OBJ-LIN: ld{{.*}} "[[HOSTOBJ]]" "[[LIBINPUT]]" "[[LLCOUT]]" "[[LLCOUTSRC]]" // CHK-FPGA-AOCX-OBJ-WIN: link{{.*}} "[[HOSTOBJ]]" "[[LIBINPUT]]" "[[LLCOUT]]" "[[LLCOUTSRC]]" @@ -244,11 +242,14 @@ // CHK-FPGA-LINK-SRC: 11: assembler, {10}, object, (host-sycl) // CHK-FPGA-LINK-SRC: 12: linker, {11}, archive, (host-sycl) // CHK-FPGA-LINK-SRC: 13: linker, {4}, ir, (device-sycl) -// CHK-FPGA-LINK-SRC: 14: sycl-post-link, {13}, ir, (device-sycl) -// CHK-FPGA-LINK-SRC: 15: llvm-spirv, {14}, spirv, (device-sycl) -// CHK-FPGA-LINK-SRC: 16: backend-compiler, {15}, fpga_aocr_emu, (device-sycl) -// CHK-FPGA-LINK-SRC: 17: clang-offload-wrapper, {16}, object, (device-sycl) -// CHK-FPGA-LINK-SRC: 18: offload, "host-sycl (x86_64-unknown-linux-gnu)" {12}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {17}, archive +// CHK-FPGA-LINK-SRC: 14: sycl-post-link, {13}, tempfiletable, (device-sycl) +// CHK-FPGA-LINK-SRC: 15: file-table-tform, {14}, tempfilelist, (device-sycl) +// CHK-FPGA-LINK-SRC: 16: llvm-spirv, {15}, tempfilelist, (device-sycl) +// CHK-FPGA-LINK-SRC: 17: backend-compiler, {16}, fpga_aocr_emu, (device-sycl) +// CHK-FPGA-LINK-SRC: 18: file-table-tform, {14, 17}, tempfiletable, (device-sycl) +// CHK-FPGA-LINK-SRC: 19: clang-offload-wrapper, {18}, object, (device-sycl) +// CHK-FPGA-LINK-SRC: 20: offload, "host-sycl (x86_64-unknown-linux-gnu)" {12}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {19}, archive + /// -fintelfpga with -reuse-exe= // RUN: touch %t.cpp @@ -320,20 +321,23 @@ /// -fintelfpga dependency file use from object phases test // RUN: touch %t-1.o -// RUN: %clangxx -fsycl -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases -### %t-1.o 2>&1 \ +// RUN: %clangxx -fsycl -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases %t-1.o 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FPGA-DEP-FILES-OBJ-PHASES %s -// RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases -### %t-1.o 2>&1 \ +// RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases %t-1.o 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FPGA-DEP-FILES-OBJ-PHASES %s // CHK-FPGA-DEP-FILES-OBJ-PHASES: 0: input, "{{.*}}-1.o", object, (host-sycl) // CHK-FPGA-DEP-FILES-OBJ-PHASES: 1: clang-offload-unbundler, {0}, object, (host-sycl) // CHK-FPGA-DEP-FILES-OBJ-PHASES: 2: linker, {1}, image, (host-sycl) // CHK-FPGA-DEP-FILES-OBJ-PHASES: 3: linker, {1}, ir, (device-sycl) -// CHK-FPGA-DEP-FILES-OBJ-PHASES: 4: sycl-post-link, {3}, ir, (device-sycl) -// CHK-FPGA-DEP-FILES-OBJ-PHASES: 5: llvm-spirv, {4}, spirv, (device-sycl) -// CHK-FPGA-DEP-FILES-OBJ-PHASES: 6: clang-offload-unbundler, {0}, fpga_dep -// CHK-FPGA-DEP-FILES-OBJ-PHASES: 7: backend-compiler, {5, 6}, fpga_aocx, (device-sycl) -// CHK-FPGA-DEP-FILES-OBJ-PHASES: 8: clang-offload-wrapper, {7}, object, (device-sycl) -// CHK-FPGA-DEP-FILES-OBJ-PHASES: 9: offload, "host-sycl (x86_64-{{unknown-linux-gnu|pc-windows-msvc}})" {2}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {8}, image +// CHK-FPGA-DEP-FILES-OBJ-PHASES: 4: sycl-post-link, {3}, tempfiletable, (device-sycl) +// CHK-FPGA-DEP-FILES-OBJ-PHASES: 5: file-table-tform, {4}, tempfilelist, (device-sycl) +// CHK-FPGA-DEP-FILES-OBJ-PHASES: 6: llvm-spirv, {5}, tempfilelist, (device-sycl) +// CHK-FPGA-DEP-FILES-OBJ-PHASES: 7: clang-offload-unbundler, {0}, fpga_dep +// CHK-FPGA-DEP-FILES-OBJ-PHASES: 8: backend-compiler, {6, 7}, fpga_aocx, (device-sycl) +// CHK-FPGA-DEP-FILES-OBJ-PHASES: 9: file-table-tform, {4, 8}, tempfiletable, (device-sycl) +// CHK-FPGA-DEP-FILES-OBJ-PHASES: 10: clang-offload-wrapper, {9}, object, (device-sycl) +// CHK-FPGA-DEP-FILES-OBJ-PHASES: 11: offload, "host-sycl ({{.*}})" {2}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {10}, image + /// -fintelfpga output report file test // RUN: mkdir -p %t_dir diff --git a/clang/test/Driver/sycl-offload-static-lib.cpp b/clang/test/Driver/sycl-offload-static-lib.cpp index bde5145f49153..7e76c3c3def33 100644 --- a/clang/test/Driver/sycl-offload-static-lib.cpp +++ b/clang/test/Driver/sycl-offload-static-lib.cpp @@ -161,14 +161,3 @@ // RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %t.a -### 2>&1 \ // RUN: | FileCheck %s -check-prefixes=STATIC_ARCHIVE_UNBUNDLE // STATIC_ARCHIVE_UNBUNDLE: clang-offload-bundler{{.*}} - -/// Use of static archives with AOT should not split or use llvm-foreach -// RUN: touch %t.a -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %t.a -### 2>&1 \ -// RUN: | FileCheck %s -check-prefixes=STATIC_ARCHIVE_SPLIT_CHECK -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %t.a -### 2>&1 \ -// RUN: | FileCheck %s -check-prefixes=STATIC_ARCHIVE_SPLIT_CHECK -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %t.a -### 2>&1 \ -// RUN: | FileCheck %s -check-prefixes=STATIC_ARCHIVE_SPLIT_CHECK -// STATIC_ARCHIVE_SPLIT_CHECK-NOT: file-table-tform{{.*}} -// STATIC_ARCHIVE_SPLIT_CHECK-NOT: llvm-foreach{{.*}} diff --git a/clang/test/Driver/sycl-offload-with-split.c b/clang/test/Driver/sycl-offload-with-split.c index f2cd867daee6b..0ca1ef2574b4b 100644 --- a/clang/test/Driver/sycl-offload-with-split.c +++ b/clang/test/Driver/sycl-offload-with-split.c @@ -297,9 +297,9 @@ // RUN: %clang_cl -### -fsycl -fsycl-device-code-split-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT // RUN: %clang -### -fsycl -fno-sycl-device-code-split-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-SPLIT // RUN: %clang_cl -### -fsycl -fno-sycl-device-code-split-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-SPLIT -// RUN: %clang -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-SPLIT -// RUN: %clang -### -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-SPLIT -// RUN: %clang_cl -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-SPLIT +// RUN: %clang -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT +// RUN: %clang -### -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT +// RUN: %clang_cl -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-SPLIT // CHK-ESIMD-SPLIT: sycl-post-link{{.*}} "-split-esimd" // CHK-NO-ESIMD-SPLIT-NOT: sycl-post-link{{.*}} "-split-esimd" @@ -310,8 +310,8 @@ // RUN: %clang_cl -### -fsycl -fsycl-device-code-lower-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER // RUN: %clang -### -fsycl -fno-sycl-device-code-lower-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-LOWER // RUN: %clang_cl -### -fsycl -fno-sycl-device-code-lower-esimd %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-LOWER -// RUN: %clang -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-LOWER -// RUN: %clang -### -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-LOWER -// RUN: %clang_cl -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-NO-ESIMD-LOWER +// RUN: %clang -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER +// RUN: %clang -### -fsycl -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER +// RUN: %clang_cl -### -fsycl -fintelfpga %s 2>&1 | FileCheck %s -check-prefixes=CHK-ESIMD-LOWER // CHK-ESIMD-LOWER: sycl-post-link{{.*}} "-lower-esimd" // CHK-NO-ESIMD-LOWER-NOT: sycl-post-link{{.*}} "-lower-esimd" diff --git a/clang/test/Driver/sycl-offload.c b/clang/test/Driver/sycl-offload.c index 399c50a8b31d1..705517c525ae2 100644 --- a/clang/test/Driver/sycl-offload.c +++ b/clang/test/Driver/sycl-offload.c @@ -622,15 +622,17 @@ // CHK-PHASES-AOT: 8: assembler, {7}, object, (host-sycl) // CHK-PHASES-AOT: 9: linker, {8}, image, (host-sycl) // CHK-PHASES-AOT: 10: linker, {4}, ir, (device-sycl) -// CHK-PHASES-AOT: 11: sycl-post-link, {10}, ir, (device-sycl) -// CHK-PHASES-AOT: 12: llvm-spirv, {11}, spirv, (device-sycl) -// CHK-PHASES-FPGA: 13: backend-compiler, {12}, fpga_aocx, (device-sycl) -// CHK-PHASES-CPU: 13: backend-compiler, {12}, image, (device-sycl) -// CHK-PHASES-GEN: 13: backend-compiler, {12}, image, (device-sycl) -// CHK-PHASES-AOT: 14: clang-offload-wrapper, {13}, object, (device-sycl) -// CHK-PHASES-FPGA: 15: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {14}, image -// CHK-PHASES-GEN: 15: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64_gen-unknown-unknown-sycldevice)" {14}, image -// CHK-PHASES-CPU: 15: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64_x86_64-unknown-unknown-sycldevice)" {14}, image +// CHK-PHASES-AOT: 11: sycl-post-link, {10}, tempfiletable, (device-sycl) +// CHK-PHASES-AOT: 12: file-table-tform, {11}, tempfilelist, (device-sycl) +// CHK-PHASES-AOT: 13: llvm-spirv, {12}, tempfilelist, (device-sycl) +// CHK-PHASES-FPGA: 14: backend-compiler, {13}, fpga_aocx, (device-sycl) +// CHK-PHASES-GEN: 14: backend-compiler, {13}, image, (device-sycl) +// CHK-PHASES-CPU: 14: backend-compiler, {13}, image, (device-sycl) +// CHK-PHASES-AOT: 15: file-table-tform, {11, 14}, tempfiletable, (device-sycl) +// CHK-PHASES-AOT: 16: clang-offload-wrapper, {15}, object, (device-sycl) +// CHK-PHASES-FPGA: 17: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {16}, image +// CHK-PHASES-GEN: 17: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64_gen-unknown-unknown-sycldevice)" {16}, image +// CHK-PHASES-CPU: 17: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64_x86_64-unknown-unknown-sycldevice)" {16}, image /// ########################################################################### @@ -665,17 +667,19 @@ // CHK-TOOLS-AOT: "-fsycl-is-device"{{.*}} "-fsycl-int-header=[[INPUT1:.+\-header.+\.h]]"{{.*}} "-o" "[[OUTPUT1:.+\.bc]]" // CHK-TOOLS-AOTx: "-o" "[[OUTPUT1:.+\.bc]]" // CHK-TOOLS-AOT: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2:.+\.bc]]" -// CHK-TOOLS-AOT: sycl-post-link{{.*}} "-o" "[[OUTPUT2_1:.+\.bc]]" "[[OUTPUT2]]" -// CHK-TOOLS-CPU: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]" -// CHK-TOOLS-GEN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]" -// CHK-TOOLS-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.spv]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]" -// CHK-TOOLS-FPGA-HW: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocx]]" "[[OUTPUT3]]" -// CHK-TOOLS-FPGA-EMU: opencl-aot{{.*}} "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]" -// CHK-TOOLS-GEN: ocloc{{.*}} "-output" "[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]" -// CHK-TOOLS-CPU: opencl-aot{{.*}} "-o=[[OUTPUT4:.+\.out]]" {{.*}} "[[OUTPUT3]]" -// CHK-TOOLS-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga{{.*}}" "-kind=sycl" "[[OUTPUT4]]" -// CHK-TOOLS-GEN: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_gen{{.*}}" "-kind=sycl" "[[OUTPUT4]]" -// CHK-TOOLS-CPU: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_x86_64{{.*}}" "-kind=sycl" "[[OUTPUT4]]" +// CHK-TOOLS-AOT: sycl-post-link{{.*}} "-o" "[[OUTPUT2_T:.+\.table]]" "[[OUTPUT2]]" +// CHK-TOOLS-AOT: file-table-tform{{.*}} "-extract=Code" "-drop_titles" "-o" "[[OUTPUT2_1:.+\.txt]]" "[[OUTPUT2_T]]" +// CHK-TOOLS-CPU: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]" +// CHK-TOOLS-GEN: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]" +// CHK-TOOLS-FPGA: llvm-spirv{{.*}} "-o" "[[OUTPUT3_T:.+\.txt]]" "-spirv-max-version=1.3" "-spirv-debug-info-version=ocl-100" "-spirv-allow-extra-diexpressions" "-spirv-allow-unknown-intrinsics=llvm.genx." {{.*}} "[[OUTPUT2_1]]" +// CHK-TOOLS-FPGA-HW: aoc{{.*}} "-o" "[[OUTPUT4_T:.+\.aocx]]" "[[OUTPUT3_T]]" +// CHK-TOOLS-FPGA-EMU: opencl-aot{{.*}} "-spv=[[OUTPUT3_T]]" "-ir=[[OUTPUT4_T:.+\.aocx]]" +// CHK-TOOLS-GEN: ocloc{{.*}} "-output" "[[OUTPUT4_T:.+\.out]]" {{.*}} "[[OUTPUT3_T]]" +// CHK-TOOLS-CPU: opencl-aot{{.*}} "-o=[[OUTPUT4_T:.+\.out]]" {{.*}} "[[OUTPUT3_T]]" +// CHK-TOOLS-AOT: file-table-tform{{.*}} "-o" "[[OUTPUT4:.+\.table]]" "{{.*}}.table"{{.*}} "[[OUTPUT4_T]]" +// CHK-TOOLS-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga{{.*}}" "-kind=sycl" "-batch" "[[OUTPUT4]]" +// CHK-TOOLS-GEN: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_gen{{.*}}" "-kind=sycl" "-batch" "[[OUTPUT4]]" +// CHK-TOOLS-CPU: clang-offload-wrapper{{.*}} "-o=[[OUTPUT5:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_x86_64{{.*}}" "-kind=sycl" "-batch" "[[OUTPUT4]]" // CHK-TOOLS-AOT: llc{{.*}} "-filetype=obj" "-o" "[[OUTPUT6:.+\.o]]" "[[OUTPUT5]]" // CHK-TOOLS-AOT: clang{{.*}} "-triple" "x86_64-unknown-linux-gnu" {{.*}} "-include" "[[INPUT1]]" {{.*}} "-o" "[[OUTPUT7:.+\.o]]" // CHK-TOOLS-AOT: ld{{.*}} "[[OUTPUT7]]" "[[OUTPUT6]]" {{.*}} "-lsycl" @@ -810,16 +814,20 @@ // CHK-PHASE-MULTI-TARG: 20: preprocessor, {19}, c++-cpp-output, (device-sycl) // CHK-PHASE-MULTI-TARG: 21: compiler, {20}, ir, (device-sycl) // CHK-PHASE-MULTI-TARG: 22: linker, {21}, ir, (device-sycl) -// CHK-PHASE-MULTI-TARG: 23: sycl-post-link, {22}, ir, (device-sycl) -// CHK-PHASE-MULTI-TARG: 24: llvm-spirv, {23}, spirv, (device-sycl) -// CHK-PHASE-MULTI-TARG: 25: backend-compiler, {24}, fpga_aocx, (device-sycl) -// CHK-PHASE-MULTI-TARG: 26: clang-offload-wrapper, {25}, object, (device-sycl) -// CHK-PHASE-MULTI-TARG: 27: linker, {4}, ir, (device-sycl) -// CHK-PHASE-MULTI-TARG: 28: sycl-post-link, {27}, ir, (device-sycl) -// CHK-PHASE-MULTI-TARG: 29: llvm-spirv, {28}, spirv, (device-sycl) -// CHK-PHASE-MULTI-TARG: 30: backend-compiler, {29}, image, (device-sycl) -// CHK-PHASE-MULTI-TARG: 31: clang-offload-wrapper, {30}, object, (device-sycl) -// CHK-PHASE-MULTI-TARG: 32: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64-unknown-unknown-sycldevice)" {18}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {26}, "device-sycl (spir64_gen-unknown-unknown-sycldevice)" {31}, image +// CHK-PHASE-MULTI-TARG: 23: sycl-post-link, {22}, tempfiletable, (device-sycl) +// CHK-PHASE-MULTI-TARG: 24: file-table-tform, {23}, tempfilelist, (device-sycl) +// CHK-PHASE-MULTI-TARG: 25: llvm-spirv, {24}, tempfilelist, (device-sycl) +// CHK-PHASE-MULTI-TARG: 26: backend-compiler, {25}, fpga_aocx, (device-sycl) +// CHK-PHASE-MULTI-TARG: 27: file-table-tform, {23, 26}, tempfiletable, (device-sycl) +// CHK-PHASE-MULTI-TARG: 28: clang-offload-wrapper, {27}, object, (device-sycl) +// CHK-PHASE-MULTI-TARG: 29: linker, {4}, ir, (device-sycl) +// CHK-PHASE-MULTI-TARG: 30: sycl-post-link, {29}, tempfiletable, (device-sycl) +// CHK-PHASE-MULTI-TARG: 31: file-table-tform, {30}, tempfilelist, (device-sycl) +// CHK-PHASE-MULTI-TARG: 32: llvm-spirv, {31}, tempfilelist, (device-sycl) +// CHK-PHASE-MULTI-TARG: 33: backend-compiler, {32}, image, (device-sycl) +// CHK-PHASE-MULTI-TARG: 34: file-table-tform, {30, 33}, tempfiletable, (device-sycl) +// CHK-PHASE-MULTI-TARG: 35: clang-offload-wrapper, {34}, object, (device-sycl) +// CHK-PHASE-MULTI-TARG: 36: offload, "host-sycl (x86_64-unknown-linux-gnu)" {9}, "device-sycl (spir64-unknown-unknown-sycldevice)" {18}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {28}, "device-sycl (spir64_gen-unknown-unknown-sycldevice)" {35}, image /// ########################################################################### /// Verify that -save-temps does not crash diff --git a/sycl/doc/images/DeviceLinkAndWrap.svg b/sycl/doc/images/DeviceLinkAndWrap.svg index df385f2171308..99ffe673132b5 100644 --- a/sycl/doc/images/DeviceLinkAndWrap.svg +++ b/sycl/doc/images/DeviceLinkAndWrap.svg @@ -9,7 +9,7 @@ xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" sodipodi:docname="DeviceLinkAndWrap.svg" - inkscape:version="1.0rc1 (09960d6f05, 2020-04-09)" + inkscape:version="1.0.2 (e86c870879, 2021-01-15, custom)" id="svg8" version="1.1" viewBox="0 0 205.79753 221.03191" @@ -1501,17 +1501,17 @@ fit-margin-left="0" fit-margin-top="0" inkscape:window-maximized="1" - inkscape:window-y="-9" - inkscape:window-x="79" - inkscape:window-height="1411" - inkscape:window-width="2472" + inkscape:window-y="12" + inkscape:window-x="-11" + inkscape:window-height="2066" + inkscape:window-width="3840" showgrid="false" inkscape:document-rotation="0" - inkscape:current-layer="layer1" + inkscape:current-layer="g841" inkscape:document-units="mm" - inkscape:cy="530.2935" + inkscape:cy="301.56522" inkscape:cx="721.53556" - inkscape:zoom="0.98994949" + inkscape:zoom="2.6044095" inkscape:pageshadow="2" inkscape:pageopacity="0.0" borderopacity="1.0" @@ -1526,7 +1526,7 @@ image/svg+xml - + @@ -1841,21 +1841,6 @@ style="fill:#538f7b;fill-opacity:1;fill-rule:nonzero;stroke:none" id="path1031" inkscape:connector-curvature="0" /> - - - - - - - - - No code split - - -