Skip to content

[SYCL][NVPTX] Removes unsupported memory orders for atomic load/store #4106

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged

Conversation

steffenlarsen
Copy link
Contributor

NVPTX currently only supports atomic loads and stores with at most monotonic ordering. Newer PTX versions have support for acquire and release, but NVPTX does not currently support this.

These changes removes the current faulty implementation of atomic loads and stores for acquire, release, and seq_cst in libclc for PTX. These are replaced by trap instructions, causing runtime errors, which is to be preferred due to memory-order selection being determined by a function parameter in libclc.

NVPTX currently only supports atomic loads and stores with at most
monotonic ordering. Newer PTX versions have support for acquire and
release, but NVPTX does not currently support this.

These changes removes the current faulty implementation of atomic loads
and stores for acquire, release, and seq_cst in libclc for PTX. These
are replaced by trap instructions, causing runtime errors, which is to
be preferred due to memory-order selection being determined by a
function parameter in libclc.

Signed-off-by: Steffen Larsen <[email protected]>
@bader bader added the cuda CUDA back-end label Jul 16, 2021
@bader bader merged commit 4876443 into intel:sycl Jul 16, 2021
@steffenlarsen steffenlarsen deleted the steffen/remove_unsupported_mem_order branch December 6, 2023 11:37
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
cuda CUDA back-end
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants