From b2891191e869f9242d71672a1e6a2e407ea538b6 Mon Sep 17 00:00:00 2001 From: Soumi Manna Date: Wed, 6 Jul 2022 04:34:04 -0700 Subject: [PATCH 1/3] [SYCL][FPGA] Remove deprecation message for intel::disable_loop_pipelining attribute https://github.com/intel/llvm/pull/6254 added the fpga_pipeline attribute and deprecated the intel::disable_loop_pipelining attribute. While this was in the pipeline, the internal decision was made to switch to properties rather than attributes for this type of thing. At this point, internal request is that (at a minimum) the deprecation message for intel::disable_loop_pipelining be removed, as we no longer plan to deprecate it. Signed-off-by: Soumi Manna --- clang/include/clang/Basic/AttrDocs.td | 3 -- clang/lib/Sema/SemaDeclAttr.cpp | 8 ---- clang/test/SemaSYCL/intel-fpga-loops.cpp | 48 +++++++++++++++++++++--- 3 files changed, 43 insertions(+), 16 deletions(-) diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 0bc553e3a1acf..3b4ec8453edcc 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -3294,9 +3294,6 @@ function, or in conjunction with ``max_interleaving``, ``speculated_iterations``, ``max_concurrency``, ``initiation_interval``, or ``ivdep``. -The ``[[intel::disable_loop_pipelining]]`` attribute spelling is a deprecated -synonym for ``[[[intel::fpga_pipeline]]`` and will be removed in the future. - .. code-block:: c++ void foo() { diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index fe312cf91082c..03b144d5f33f9 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -364,14 +364,6 @@ void Sema::CheckDeprecatedSYCLAttributeSpelling(const ParsedAttr &A, Diag(A.getLoc(), diag::ext_sycl_2020_attr_spelling) << A; return; } - - // Deprecate [[intel::disable_loop_pipelining]] attribute spelling in favor - // of the SYCL FPGA attribute spelling [[intel::fpga_pipeline]]. - if (A.hasScope() && A.getScopeName()->isStr("intel") && - A.getAttrName()->isStr("disable_loop_pipelining")) { - DiagnoseDeprecatedAttribute(A, "intel", "fpga_pipeline"); - return; - } } /// Check if IdxExpr is a valid parameter index for a function or diff --git a/clang/test/SemaSYCL/intel-fpga-loops.cpp b/clang/test/SemaSYCL/intel-fpga-loops.cpp index d093a0ed5f176..f8d0b646d8772 100644 --- a/clang/test/SemaSYCL/intel-fpga-loops.cpp +++ b/clang/test/SemaSYCL/intel-fpga-loops.cpp @@ -134,6 +134,9 @@ void boo() { void goo() { int a[10]; // no diagnostics are expected + [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) + a[i] = 0; + // no diagnostics are expected [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) a[i] = 0; // no diagnostics are expected @@ -269,6 +272,10 @@ void zoo() { [[intel::max_concurrency(2)]] [[intel::initiation_interval(2)]] for (int i = 0; i != 10; ++i) a[i] = 0; + [[intel::disable_loop_pipelining]] + // expected-error@+1 {{duplicate Intel FPGA loop attribute 'disable_loop_pipelining'}} + [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) + a[i] = 0; [[intel::fpga_pipeline]] // expected-error@+1 {{duplicate Intel FPGA loop attribute 'fpga_pipeline'}} [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) @@ -355,23 +362,54 @@ void zoo() { // Test for Intel FPGA loop attributes compatibility void loop_attrs_compatibility() { int a[10]; + // no diagnostics are expected + [[intel::disable_loop_pipelining]] [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) + a[i] = 0; + // no diagnostics are expected [[intel::fpga_pipeline]] [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) a[i] = 0; - // expected-error@+4 {{'max_interleaving' and 'disable_loop_pipelining' attributes are not compatible}} + // expected-error@+2 {{'max_interleaving' and 'disable_loop_pipelining' attributes are not compatible}} // expected-note@+1 {{conflicting attribute is here}} - [[intel::disable_loop_pipelining]] // expected-warning {{attribute 'intel::disable_loop_pipelining' is deprecated}} \ - // expected-note {{did you mean to use 'intel::fpga_pipeline' instead?}} - [[intel::max_interleaving(0)]] for (int i = 0; i != 10; ++i) + [[intel::disable_loop_pipelining]] [[intel::max_interleaving(0)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + // expected-error@+2 {{'max_concurrency' and 'disable_loop_pipelining' attributes are not compatible}} + // expected-note@+1 {{conflicting attribute is here}} + [[intel::disable_loop_pipelining]] [[intel::max_concurrency(0)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + // expected-error@+2 {{'disable_loop_pipelining' and 'speculated_iterations' attributes are not compatible}} + // expected-note@+1 {{conflicting attribute is here}} + [[intel::speculated_iterations(0)]] [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) a[i] = 0; - // expected-error@+2 {{'fpga_pipeline' and 'speculated_iterations' attributes are not compatible}} // expected-note@+1 {{conflicting attribute is here}} [[intel::speculated_iterations(0)]] [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) a[i] = 0; + // expected-error@+2 {{'disable_loop_pipelining' and 'initiation_interval' attributes are not compatible}} + // expected-note@+1 {{conflicting attribute is here}} + [[intel::initiation_interval(10)]] [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) + a[i] = 0; + // expected-error@+2 {{'ivdep' and 'disable_loop_pipelining' attributes are not compatible}} + // expected-note@+1 {{conflicting attribute is here}} + [[intel::disable_loop_pipelining]] [[intel::ivdep]] for (int i = 0; i != 10; ++i) + a[i] = 0; // expected-error@+2 {{'fpga_pipeline' and 'initiation_interval' attributes are not compatible}} // expected-note@+1 {{conflicting attribute is here}} [[intel::initiation_interval(10)]] [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) a[i] = 0; + // no diagnostics are expected + [[intel::disable_loop_pipelining]] [[intel::nofusion]] for (int i = 0; i != 10; ++i) + a[i] = 0; + // no diagnostics are expected + [[intel::disable_loop_pipelining]] [[intel::loop_count_avg(8)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::loop_count_min(8)]] + for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::loop_count_max(8)]] + for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::loop_count(8)]] for (int i = 0; i != 10; ++i) + a[i] = 0; // no diagnostics are expected [[intel::fpga_pipeline]] [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) From c26e0174256a0c7d6d926cde658459486341399f Mon Sep 17 00:00:00 2001 From: Soumi Manna Date: Wed, 6 Jul 2022 04:42:51 -0700 Subject: [PATCH 2/3] Fix clang format errors Signed-off-by: Soumi Manna --- clang/test/SemaSYCL/intel-fpga-loops.cpp | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/clang/test/SemaSYCL/intel-fpga-loops.cpp b/clang/test/SemaSYCL/intel-fpga-loops.cpp index f8d0b646d8772..87b615ec6a33d 100644 --- a/clang/test/SemaSYCL/intel-fpga-loops.cpp +++ b/clang/test/SemaSYCL/intel-fpga-loops.cpp @@ -402,14 +402,12 @@ void loop_attrs_compatibility() { // no diagnostics are expected [[intel::disable_loop_pipelining]] [[intel::loop_count_avg(8)]] for (int i = 0; i != 10; ++i) a[i] = 0; - [[intel::loop_count_min(8)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intel::loop_count_max(8)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; + [[intel::loop_count_min(8)]] for (int i = 0; i != 10; ++i) + a[i] = 0; + [[intel::loop_count_max(8)]] for (int i = 0; i != 10; ++i) + a[i] = 0; [[intel::loop_count(8)]] for (int i = 0; i != 10; ++i) - a[i] = 0; + a[i] = 0; // no diagnostics are expected [[intel::fpga_pipeline]] [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) From c0444e9e291876b4be421b1a7144db6a8fc21747 Mon Sep 17 00:00:00 2001 From: Soumi Manna Date: Wed, 6 Jul 2022 12:13:28 -0700 Subject: [PATCH 3/3] address review comment Signed-off-by: Soumi Manna --- clang/test/SemaSYCL/intel-fpga-loops.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/clang/test/SemaSYCL/intel-fpga-loops.cpp b/clang/test/SemaSYCL/intel-fpga-loops.cpp index 87b615ec6a33d..4a14afbcc0697 100644 --- a/clang/test/SemaSYCL/intel-fpga-loops.cpp +++ b/clang/test/SemaSYCL/intel-fpga-loops.cpp @@ -442,6 +442,10 @@ void loop_attrs_compatibility() { // expected-note@+1 {{conflicting attribute is here}} [[intel::ivdep]] [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) a[i] = 0; + + // no diagnostics are expected + [[intel::disable_loop_pipelining]] [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) + a[i] = 0; } template