diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index 643f2bd74b314..379ecd18ab3a2 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -2320,7 +2320,7 @@ def Mode : Attr {
   let PragmaAttributeSupport = 0;
 }
 
-def SYCLIntelFPGAIVDep : StmtAttr {
+def SYCLIntelIVDep : StmtAttr {
   let Spellings = [CXX11<"intel", "ivdep">];
   let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
                              ErrorDiag, "'for', 'while', and 'do' statements">;
@@ -2352,8 +2352,8 @@ def SYCLIntelFPGAIVDep : StmtAttr {
       return !getSafelenExpr();
     }
 
-    static bool SafelenCompare(const SYCLIntelFPGAIVDepAttr *LHS,
-                               const SYCLIntelFPGAIVDepAttr *RHS) {
+    static bool SafelenCompare(const SYCLIntelIVDepAttr *LHS,
+                               const SYCLIntelIVDepAttr *RHS) {
       // INF < INF is false, !INF < INF is true.
       if (!RHS->getSafelenExpr())
         return false;
@@ -2362,10 +2362,10 @@ def SYCLIntelFPGAIVDep : StmtAttr {
       return LHS->getSafelenValue() > RHS->getSafelenValue();
     }
   }];
-  let Documentation = [SYCLIntelFPGAIVDepAttrDocs];
+  let Documentation = [SYCLIntelIVDepAttrDocs];
 }
 
-def SYCLIntelFPGAInitiationInterval : DeclOrStmtAttr {
+def SYCLIntelInitiationInterval : DeclOrStmtAttr {
   let Spellings = [CXX11<"intel", "ii">,
                    CXX11<"intel", "initiation_interval">];
   let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function],
@@ -2374,11 +2374,11 @@ def SYCLIntelFPGAInitiationInterval : DeclOrStmtAttr {
   let Args = [ExprArgument<"IntervalExpr">];
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
   let IsStmtDependent = 1;
-  let Documentation = [SYCLIntelFPGAInitiationIntervalAttrDocs];
+  let Documentation = [SYCLIntelInitiationIntervalAttrDocs];
   let SupportsNonconformingLambdaSyntax = 1;
 }
 
-def SYCLIntelFPGAMaxConcurrency : DeclOrStmtAttr {
+def SYCLIntelMaxConcurrency : DeclOrStmtAttr {
   let Spellings = [CXX11<"intel", "max_concurrency">];
   let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function],
                              ErrorDiag,
@@ -2386,39 +2386,39 @@ def SYCLIntelFPGAMaxConcurrency : DeclOrStmtAttr {
   let Args = [ExprArgument<"NThreadsExpr">];
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
   let IsStmtDependent = 1;
-  let Documentation = [SYCLIntelFPGAMaxConcurrencyAttrDocs];
+  let Documentation = [SYCLIntelMaxConcurrencyAttrDocs];
   let SupportsNonconformingLambdaSyntax = 1;
 }
 
-def SYCLIntelFPGALoopCoalesce : StmtAttr {
+def SYCLIntelLoopCoalesce : StmtAttr {
   let Spellings = [CXX11<"intel", "loop_coalesce">];
   let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
                              ErrorDiag, "'for', 'while', and 'do' statements">;
   let Args = [ExprArgument<"NExpr", /*opt*/1>];
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
   let IsStmtDependent = 1;
-  let Documentation = [SYCLIntelFPGALoopCoalesceAttrDocs];
+  let Documentation = [SYCLIntelLoopCoalesceAttrDocs];
 }
 
-def SYCLIntelFPGADisableLoopPipelining : DeclOrStmtAttr {
+def SYCLIntelDisableLoopPipelining : DeclOrStmtAttr {
   let Spellings = [CXX11<"intel", "disable_loop_pipelining">];
   let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function],
                               ErrorDiag,
                               "'for', 'while', 'do' statements, and functions">;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
   let IsStmtDependent = 1;
-  let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs];
+  let Documentation = [SYCLIntelDisableLoopPipeliningAttrDocs];
   let SupportsNonconformingLambdaSyntax = 1;
   let SimpleHandler = 1;
 }
-def : MutualExclusions<[SYCLIntelFPGAInitiationInterval,
-                        SYCLIntelFPGADisableLoopPipelining]>;
-def : MutualExclusions<[SYCLIntelFPGAIVDep,
-                        SYCLIntelFPGADisableLoopPipelining]>;
-def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency,
-                        SYCLIntelFPGADisableLoopPipelining]>;
+def : MutualExclusions<[SYCLIntelInitiationInterval,
+                        SYCLIntelDisableLoopPipelining]>;
+def : MutualExclusions<[SYCLIntelIVDep,
+                        SYCLIntelDisableLoopPipelining]>;
+def : MutualExclusions<[SYCLIntelMaxConcurrency,
+                        SYCLIntelDisableLoopPipelining]>;
 
-def SYCLIntelFPGALoopCount : StmtAttr {
+def SYCLIntelLoopCount : StmtAttr {
   let Spellings = [CXX11<"intel", "loop_count_min">,
                    CXX11<"intel", "loop_count_max">,
                    CXX11<"intel", "loop_count_avg">,
@@ -2432,58 +2432,58 @@ def SYCLIntelFPGALoopCount : StmtAttr {
   let Args = [ExprArgument<"NTripCount">];
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
   let IsStmtDependent = 1;
-  let Documentation = [SYCLIntelFPGALoopCountAttrDocs];
+  let Documentation = [SYCLIntelLoopCountAttrDocs];
 }
 
-def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency,
-                        SYCLIntelFPGADisableLoopPipelining]>;
+def : MutualExclusions<[SYCLIntelMaxConcurrency,
+                        SYCLIntelDisableLoopPipelining]>;
 
-def SYCLIntelFPGAMaxInterleaving : StmtAttr {
+def SYCLIntelMaxInterleaving : StmtAttr {
   let Spellings = [CXX11<"intel", "max_interleaving">];
   let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
                              ErrorDiag, "'for', 'while', and 'do' statements">;
   let Args = [ExprArgument<"NExpr">];
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
   let IsStmtDependent = 1;
-  let Documentation = [SYCLIntelFPGAMaxInterleavingAttrDocs];
+  let Documentation = [SYCLIntelMaxInterleavingAttrDocs];
 }
-def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining,
-                        SYCLIntelFPGAMaxInterleaving]>;
+def : MutualExclusions<[SYCLIntelDisableLoopPipelining,
+                        SYCLIntelMaxInterleaving]>;
 
-def SYCLIntelFPGASpeculatedIterations : StmtAttr {
+def SYCLIntelSpeculatedIterations : StmtAttr {
   let Spellings = [CXX11<"intel", "speculated_iterations">];
   let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
                              ErrorDiag, "'for', 'while', and 'do' statements">;
   let Args = [ExprArgument<"NExpr">];
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
   let IsStmtDependent = 1;
-  let Documentation = [SYCLIntelFPGASpeculatedIterationsAttrDocs];
+  let Documentation = [SYCLIntelSpeculatedIterationsAttrDocs];
 }
-def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining,
-                        SYCLIntelFPGASpeculatedIterations]>;
+def : MutualExclusions<[SYCLIntelDisableLoopPipelining,
+                        SYCLIntelSpeculatedIterations]>;
 
-def SYCLIntelFPGANofusion : StmtAttr {
+def SYCLIntelNofusion : StmtAttr {
   let Spellings = [CXX11<"intel","nofusion">];
   let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
                              ErrorDiag, "'for', 'while', and 'do' statements">;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
   let IsStmtDependent = 1;
-  let Documentation = [SYCLIntelFPGANofusionAttrDocs];
+  let Documentation = [SYCLIntelNofusionAttrDocs];
 }
 
-def SYCLIntelFPGAMaxReinvocationDelay : StmtAttr {
+def SYCLIntelMaxReinvocationDelay : StmtAttr {
   let Spellings = [CXX11<"intel", "max_reinvocation_delay">];
   let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
                              ErrorDiag, "'for', 'while', and 'do' statements">;
   let Args = [ExprArgument<"NExpr">];
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
   let IsStmtDependent = 1;
-  let Documentation = [SYCLIntelFPGAMaxReinvocationDelayAttrDocs];
+  let Documentation = [SYCLIntelMaxReinvocationDelayAttrDocs];
 }
-def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining,
-                        SYCLIntelFPGAMaxReinvocationDelay]>;
+def : MutualExclusions<[SYCLIntelDisableLoopPipelining,
+                        SYCLIntelMaxReinvocationDelay]>;
 
-def IntelFPGALocalNonConstVar : SubsetSubject<Var,
+def SYCLIntelLocalNonConstVar : SubsetSubject<Var,
                               [{S->hasLocalStorage() &&
                                 S->getKind() != Decl::ImplicitParam &&
                                 S->getKind() != Decl::ParmVar &&
@@ -2491,7 +2491,7 @@ def IntelFPGALocalNonConstVar : SubsetSubject<Var,
                                 !S->getType().isConstQualified()}],
                               "local non-const variables">;
 
-def IntelFPGAConstVar : SubsetSubject<Var,
+def SYCLIntelConstVar : SubsetSubject<Var,
                       [{S->getKind() != Decl::ImplicitParam &&
                         S->getKind() != Decl::ParmVar &&
                         S->getKind() != Decl::NonTypeTemplateParm &&
@@ -2500,14 +2500,14 @@ def IntelFPGAConstVar : SubsetSubject<Var,
                             LangAS::opencl_constant)}],
                       "constant variables">;
 
-def IntelFPGALocalStaticAgentMemVar : SubsetSubject<Var,
+def SYCLIntelLocalStaticAgentMemVar : SubsetSubject<Var,
       [{S->getKind() != Decl::ImplicitParam &&
         S->getKind() != Decl::NonTypeTemplateParm &&
        (S->getStorageClass() == SC_Static ||
         S->hasLocalStorage())}],
         "local variables, static variables, agent memory arguments">;
 
-def IntelFPGALocalOrStaticVar : SubsetSubject<Var,
+def SYCLIntelLocalOrStaticVar : SubsetSubject<Var,
                               [{S->getKind() != Decl::ImplicitParam &&
                                 S->getKind() != Decl::ParmVar &&
                                 S->getKind() != Decl::NonTypeTemplateParm &&
@@ -2515,23 +2515,23 @@ def IntelFPGALocalOrStaticVar : SubsetSubject<Var,
                                  S->hasLocalStorage())}],
                               "local variables, static variables">;
 
-def IntelFPGADoublePump : Attr {
+def SYCLIntelDoublePump : Attr {
   let Spellings = [CXX11<"intel", "doublepump">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar, SYCLIntelLocalOrStaticVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGADoublePumpAttrDocs];
+  let Documentation = [SYCLIntelDoublePumpAttrDocs];
 }
 
-def IntelFPGASinglePump : Attr {
+def SYCLIntelSinglePump : Attr {
   let Spellings = [CXX11<"intel", "singlepump">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar, SYCLIntelLocalOrStaticVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGASinglePumpAttrDocs];
+  let Documentation = [SYCLIntelSinglePumpAttrDocs];
 }
 
-def IntelFPGAMemory : Attr {
+def SYCLIntelMemory : Attr {
   let Spellings = [CXX11<"intel", "fpga_memory">];
   let Args = [EnumArgument<"Kind", "MemoryKind",
                            ["MLAB", "BLOCK_RAM", ""],
@@ -2545,86 +2545,91 @@ def IntelFPGAMemory : Attr {
       }
     }
   }];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar,
+                              SYCLIntelLocalStaticAgentMemVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGAMemoryAttrDocs];
+  let Documentation = [SYCLIntelMemoryAttrDocs];
 }
 
-def IntelFPGARegister : Attr {
+def SYCLIntelRegister : Attr {
   let Spellings = [CXX11<"intel", "fpga_register">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar, SYCLIntelLocalOrStaticVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGARegisterAttrDocs];
+  let Documentation = [SYCLIntelRegisterAttrDocs];
 }
-def : MutualExclusions<[IntelFPGADoublePump, IntelFPGASinglePump,
-                        IntelFPGARegister]>;
+def : MutualExclusions<[SYCLIntelDoublePump, SYCLIntelSinglePump,
+                        SYCLIntelRegister]>;
 
 // One integral argument.
-def IntelFPGABankWidth : InheritableAttr {
+def SYCLIntelBankWidth : InheritableAttr {
   let Spellings = [CXX11<"intel", "bankwidth">];
   let Args = [ExprArgument<"Value">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar,
+                              SYCLIntelLocalStaticAgentMemVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGABankWidthAttrDocs];
+  let Documentation = [SYCLIntelBankWidthAttrDocs];
 }
-def : MutualExclusions<[IntelFPGARegister, IntelFPGABankWidth]>;
+def : MutualExclusions<[SYCLIntelRegister, SYCLIntelBankWidth]>;
 
-def IntelFPGANumBanks : InheritableAttr {
+def SYCLIntelNumBanks : InheritableAttr {
   let Spellings = [CXX11<"intel", "numbanks">];
   let Args = [ExprArgument<"Value">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar,
+                              SYCLIntelLocalStaticAgentMemVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGANumBanksAttrDocs];
+  let Documentation = [SYCLIntelNumBanksAttrDocs];
 }
 
-def IntelFPGAPrivateCopies : InheritableAttr {
+def SYCLIntelPrivateCopies : InheritableAttr {
   let Spellings = [CXX11<"intel", "private_copies">];
   let Args = [ExprArgument<"Value">];
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
-  let Documentation = [IntelFPGAPrivateCopiesAttrDocs];
+  let Subjects = SubjectList<[SYCLIntelLocalNonConstVar, Field], ErrorDiag>;
+  let Documentation = [SYCLIntelPrivateCopiesAttrDocs];
 }
-def : MutualExclusions<[IntelFPGARegister, IntelFPGAPrivateCopies]>;
+def : MutualExclusions<[SYCLIntelRegister, SYCLIntelPrivateCopies]>;
 
 // Two string arguments.
-def IntelFPGAMerge : Attr {
+def SYCLIntelMerge : Attr {
   let Spellings = [CXX11<"intel", "merge">];
   let Args = [StringArgument<"Name">, StringArgument<"Direction">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar, SYCLIntelLocalOrStaticVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGAMergeAttrDocs];
+  let Documentation = [SYCLIntelMergeAttrDocs];
 }
-def : MutualExclusions<[IntelFPGARegister, IntelFPGAMerge]>;
+def : MutualExclusions<[SYCLIntelRegister, SYCLIntelMerge]>;
 
-def IntelFPGAMaxReplicates : InheritableAttr {
+def SYCLIntelMaxReplicates : InheritableAttr {
   let Spellings = [CXX11<"intel", "max_replicates">];
   let Args = [ExprArgument<"Value">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar,
+                              SYCLIntelLocalStaticAgentMemVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGAMaxReplicatesAttrDocs];
+  let Documentation = [SYCLIntelMaxReplicatesAttrDocs];
 }
-def : MutualExclusions<[IntelFPGARegister, IntelFPGAMaxReplicates]>;
+def : MutualExclusions<[SYCLIntelRegister, SYCLIntelMaxReplicates]>;
 
-def IntelFPGASimpleDualPort : Attr {
+def SYCLIntelSimpleDualPort : Attr {
   let Spellings = [CXX11<"intel", "simple_dual_port">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar,
+                              SYCLIntelLocalStaticAgentMemVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGASimpleDualPortAttrDocs];
+  let Documentation = [SYCLIntelSimpleDualPortAttrDocs];
 }
-def : MutualExclusions<[IntelFPGARegister, IntelFPGASimpleDualPort]>;
+def : MutualExclusions<[SYCLIntelRegister, SYCLIntelSimpleDualPort]>;
 
-def SYCLFPGAPipe : TypeAttr {
+def SYCLIntelPipe : TypeAttr {
   let Spellings = [GNU<"pipe">];
   let Args = [StringArgument<"Mode">];
   let LangOpts = [SYCLIsDevice];
-  let Documentation = [SYCLFPGAPipeDocs];
+  let Documentation = [SYCLIntelPipeDocs];
 }
 
 def SYCLIntelPipeIO : InheritableAttr {
@@ -2636,26 +2641,28 @@ def SYCLIntelPipeIO : InheritableAttr {
 }
 
 // Variadic integral arguments.
-def IntelFPGABankBits : Attr {
+def SYCLIntelBankBits : Attr {
   let Spellings = [CXX11<"intel", "bank_bits">];
   let Args = [VariadicExprArgument<"Args">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar,
+                              SYCLIntelLocalStaticAgentMemVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGABankBitsDocs];
+  let Documentation = [SYCLIntelBankBitsDocs];
 }
-def : MutualExclusions<[IntelFPGARegister, IntelFPGABankBits]>;
-def : MutualExclusions<[IntelFPGARegister, IntelFPGANumBanks]>;
+def : MutualExclusions<[SYCLIntelRegister, SYCLIntelBankBits]>;
+def : MutualExclusions<[SYCLIntelRegister, SYCLIntelNumBanks]>;
 
-def IntelFPGAForcePow2Depth : InheritableAttr {
+def SYCLIntelForcePow2Depth : InheritableAttr {
   let Spellings = [CXX11<"intel", "force_pow2_depth">];
   let Args = [ExprArgument<"Value">];
-  let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
+  let Subjects = SubjectList<[SYCLIntelConstVar,
+                              SYCLIntelLocalStaticAgentMemVar,
                               Field], ErrorDiag>;
   let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
-  let Documentation = [IntelFPGAForcePow2DepthAttrDocs];
+  let Documentation = [SYCLIntelForcePow2DepthAttrDocs];
 }
-def : MutualExclusions<[IntelFPGARegister, IntelFPGAForcePow2Depth]>;
+def : MutualExclusions<[SYCLIntelRegister, SYCLIntelForcePow2Depth]>;
 
 def Naked : InheritableAttr {
   let Spellings = [GCC<"naked">, Declspec<"naked">];
diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td
index 9046d3877ba71..8aa09f175404c 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -2331,7 +2331,7 @@ as ``-mlong-calls`` and ``-mno-long-calls``.
   }];
 }
 
-def IntelFPGADoublePumpAttrDocs : Documentation {
+def SYCLIntelDoublePumpAttrDocs : Documentation {
 let Category = DocCatVariable;
   let Heading = "intel::doublepump";
   let Content = [{
@@ -2352,7 +2352,7 @@ that is clocked at twice the rate of its accessors.
   }];
 }
 
-def IntelFPGASinglePumpAttrDocs : Documentation {
+def SYCLIntelSinglePumpAttrDocs : Documentation {
 let Category = DocCatVariable;
   let Heading = "intel::singlepump";
   let Content = [{
@@ -2373,7 +2373,7 @@ that is clocked at the same rate as its accessors.
   }];
 }
 
-def IntelFPGAMemoryAttrDocs : Documentation {
+def SYCLIntelMemoryAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::fpga_memory";
   let Content = [{
@@ -2397,7 +2397,7 @@ it indicates what type of memory to use.
   }];
 }
 
-def IntelFPGARegisterAttrDocs : Documentation {
+def SYCLIntelRegisterAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::fpga_register";
   let Content = [{
@@ -2418,7 +2418,7 @@ if possible.
   }];
 }
 
-def IntelFPGABankWidthAttrDocs : Documentation {
+def SYCLIntelBankWidthAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::bankwidth";
   let Content = [{
@@ -2440,7 +2440,7 @@ with banks that are N bytes wide.
   }];
 }
 
-def IntelFPGANumBanksAttrDocs : Documentation {
+def SYCLIntelNumBanksAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::numbanks";
   let Content = [{
@@ -2462,7 +2462,7 @@ with N banks.
   }];
 }
 
-def IntelFPGAPrivateCopiesAttrDocs : Documentation {
+def SYCLIntelPrivateCopiesAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::private_copies";
   let Content = [{
@@ -2485,7 +2485,7 @@ threads or loop iterations.
   }];
 }
 
-def IntelFPGAMergeAttrDocs : Documentation {
+def SYCLIntelMergeAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::merge";
   let Content = [{
@@ -2510,7 +2510,7 @@ depth-wise or width-wise manner.
   }];
 }
 
-def IntelFPGAMaxReplicatesAttrDocs : Documentation {
+def SYCLIntelMaxReplicatesAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::max_replicates";
   let Content = [{
@@ -2533,7 +2533,7 @@ simultaneous accesses from different load/store sites in the program.
   }];
 }
 
-def IntelFPGASimpleDualPortAttrDocs : Documentation {
+def SYCLIntelSimpleDualPortAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::simple_dual_port";
   let Content = [{
@@ -2555,7 +2555,7 @@ loads).
   }];
 }
 
-def IntelFPGABankBitsDocs : Documentation {
+def SYCLIntelBankBitsDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::bank_bits";
   let Content = [{
@@ -2583,7 +2583,7 @@ pointer address bits to bank on.
   }];
 }
 
-def IntelFPGAForcePow2DepthAttrDocs : Documentation {
+def SYCLIntelForcePow2DepthAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::force_pow2_depth";
   let Content = [{
@@ -3144,7 +3144,7 @@ sycl_detail namespace.
   }];
 }
 
-def SYCLFPGAPipeDocs : Documentation {
+def SYCLIntelPipeDocs : Documentation {
   let Category = DocCatStmt;
   let Heading = "pipe (read_only, write_only)";
   let Content = [{
@@ -3168,7 +3168,7 @@ with which a pipe interfaces. The id argument is the name of the I/O interface.
   }];
 }
 
-def SYCLIntelFPGAIVDepAttrDocs : Documentation {
+def SYCLIntelIVDepAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::ivdep";
   let Content = [{
@@ -3209,7 +3209,7 @@ or 1 is used.
   }];
 }
 
-def SYCLIntelFPGAInitiationIntervalAttrDocs : Documentation {
+def SYCLIntelInitiationIntervalAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::initiation_interval";
   let Content = [{
@@ -3242,7 +3242,7 @@ The ``[[intel::ii]]`` attribute spelling is a deprecated synonym for
   }];
 }
 
-def SYCLIntelFPGAMaxConcurrencyAttrDocs : Documentation {
+def SYCLIntelMaxConcurrencyAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::max_concurrency";
   let Content = [{
@@ -3270,7 +3270,7 @@ same loop or function, or in conjunction with ``disable_loop_pipelining``.
   }];
 }
 
-def SYCLIntelFPGALoopCoalesceAttrDocs : Documentation {
+def SYCLIntelLoopCoalesceAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::loop_coalesce";
   let Content = [{
@@ -3309,7 +3309,7 @@ of the nested loop levels should be coalesced.
   }];
 }
 
-def SYCLIntelFPGADisableLoopPipeliningAttrDocs : Documentation {
+def SYCLIntelDisableLoopPipeliningAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::disable_loop_pipelining";
   let Content = [{
@@ -3332,7 +3332,7 @@ function, or in conjunction with ``max_interleaving``,
   }];
 }
 
-def SYCLIntelFPGALoopCountAttrDocs : Documentation {
+def SYCLIntelLoopCountAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::loop_count_min, intel::loop_count_max, intel::loop_count_avg, intel::loop_count";
   let Content = [{
@@ -3376,7 +3376,7 @@ using PGO.
   }];
 }
 
-def SYCLIntelFPGAMaxInterleavingAttrDocs : Documentation {
+def SYCLIntelMaxInterleavingAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::max_interleaving";
   let Content = [{
@@ -3402,7 +3402,7 @@ used on the same loop in conjunction with disable_loop_pipelining.
   }];
 }
 
-def SYCLIntelFPGASpeculatedIterationsAttrDocs : Documentation {
+def SYCLIntelSpeculatedIterationsAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::speculated_iterations";
   let Content = [{
@@ -3427,7 +3427,7 @@ used on the same loop in conjunction with disable_loop_pipelining.
   }];
 }
 
-def SYCLIntelFPGANofusionAttrDocs : Documentation {
+def SYCLIntelNofusionAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::nofusion";
   let Content = [{
@@ -3451,7 +3451,7 @@ loop should not be fused with any adjacent loop.
   }];
 }
 
-def SYCLIntelFPGAMaxReinvocationDelayAttrDocs : Documentation {
+def SYCLIntelMaxReinvocationDelayAttrDocs : Documentation {
   let Category = DocCatVariable;
   let Heading = "intel::max_reinvocation_delay";
   let Content = [{
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 41eacf135b43b..c91ce711abe64 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -2277,31 +2277,31 @@ class Sema final {
   /// Same as above, but constructs the AddressSpace index if not provided.
   QualType BuildAddressSpaceAttr(QualType &T, Expr *AddrSpace,
                                  SourceLocation AttrLoc);
-  SYCLIntelFPGAIVDepAttr *
-  BuildSYCLIntelFPGAIVDepAttr(const AttributeCommonInfo &CI, Expr *Expr1,
-                              Expr *Expr2);
+  SYCLIntelIVDepAttr *
+  BuildSYCLIntelIVDepAttr(const AttributeCommonInfo &CI, Expr *Expr1,
+                          Expr *Expr2);
   LoopUnrollHintAttr *BuildLoopUnrollHintAttr(const AttributeCommonInfo &A,
                                               Expr *E);
   OpenCLUnrollHintAttr *
   BuildOpenCLLoopUnrollHintAttr(const AttributeCommonInfo &A, Expr *E);
 
-  SYCLIntelFPGALoopCountAttr *
-  BuildSYCLIntelFPGALoopCountAttr(const AttributeCommonInfo &CI, Expr *E);
-  SYCLIntelFPGAInitiationIntervalAttr *
-  BuildSYCLIntelFPGAInitiationIntervalAttr(const AttributeCommonInfo &CI,
-                                           Expr *E);
-  SYCLIntelFPGAMaxConcurrencyAttr *
-  BuildSYCLIntelFPGAMaxConcurrencyAttr(const AttributeCommonInfo &CI, Expr *E);
-  SYCLIntelFPGAMaxInterleavingAttr *
-  BuildSYCLIntelFPGAMaxInterleavingAttr(const AttributeCommonInfo &CI, Expr *E);
-  SYCLIntelFPGASpeculatedIterationsAttr *
-  BuildSYCLIntelFPGASpeculatedIterationsAttr(const AttributeCommonInfo &CI,
-                                             Expr *E);
-  SYCLIntelFPGALoopCoalesceAttr *
-  BuildSYCLIntelFPGALoopCoalesceAttr(const AttributeCommonInfo &CI, Expr *E);
-  SYCLIntelFPGAMaxReinvocationDelayAttr *
-  BuildSYCLIntelFPGAMaxReinvocationDelayAttr(const AttributeCommonInfo &CI, 
-                                             Expr *E);
+  SYCLIntelLoopCountAttr *
+  BuildSYCLIntelLoopCountAttr(const AttributeCommonInfo &CI, Expr *E);
+  SYCLIntelInitiationIntervalAttr *
+  BuildSYCLIntelInitiationIntervalAttr(const AttributeCommonInfo &CI,
+                                       Expr *E);
+  SYCLIntelMaxConcurrencyAttr *
+  BuildSYCLIntelMaxConcurrencyAttr(const AttributeCommonInfo &CI, Expr *E);
+  SYCLIntelMaxInterleavingAttr *
+  BuildSYCLIntelMaxInterleavingAttr(const AttributeCommonInfo &CI, Expr *E);
+  SYCLIntelSpeculatedIterationsAttr *
+  BuildSYCLIntelSpeculatedIterationsAttr(const AttributeCommonInfo &CI,
+                                         Expr *E);
+  SYCLIntelLoopCoalesceAttr *
+  BuildSYCLIntelLoopCoalesceAttr(const AttributeCommonInfo &CI, Expr *E);
+  SYCLIntelMaxReinvocationDelayAttr *
+  BuildSYCLIntelMaxReinvocationDelayAttr(const AttributeCommonInfo &CI,
+                                         Expr *E);
 
   bool CheckQualifiedFunctionForTypeId(QualType T, SourceLocation Loc);
 
@@ -10988,7 +10988,7 @@ class Sema final {
   /// attribute to be added (usually because of a pragma).
   void AddOptnoneAttributeIfNoConflicts(FunctionDecl *FD, SourceLocation Loc);
 
-  void AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
+  void AddSYCLIntelBankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
                                 Expr **Exprs, unsigned Size);
   void AddWorkGroupSizeHintAttr(Decl *D, const AttributeCommonInfo &CI,
                                 Expr *XDim, Expr *YDim, Expr *ZDim);
@@ -11024,38 +11024,38 @@ class Sema final {
                                 Expr *E);
   SYCLIntelLoopFuseAttr *
   MergeSYCLIntelLoopFuseAttr(Decl *D, const SYCLIntelLoopFuseAttr &A);
-  void AddIntelFPGAPrivateCopiesAttr(Decl *D, const AttributeCommonInfo &CI,
+  void AddSYCLIntelPrivateCopiesAttr(Decl *D, const AttributeCommonInfo &CI,
                                      Expr *E);
-  void AddIntelFPGAMaxReplicatesAttr(Decl *D, const AttributeCommonInfo &CI,
+  void AddSYCLIntelMaxReplicatesAttr(Decl *D, const AttributeCommonInfo &CI,
                                      Expr *E);
-  IntelFPGAMaxReplicatesAttr *
-  MergeIntelFPGAMaxReplicatesAttr(Decl *D, const IntelFPGAMaxReplicatesAttr &A);
-  void AddIntelFPGAForcePow2DepthAttr(Decl *D, const AttributeCommonInfo &CI,
+  SYCLIntelMaxReplicatesAttr *
+  MergeSYCLIntelMaxReplicatesAttr(Decl *D, const SYCLIntelMaxReplicatesAttr &A);
+  void AddSYCLIntelForcePow2DepthAttr(Decl *D, const AttributeCommonInfo &CI,
                                       Expr *E);
-  IntelFPGAForcePow2DepthAttr *
-  MergeIntelFPGAForcePow2DepthAttr(Decl *D,
-                                   const IntelFPGAForcePow2DepthAttr &A);
-  void AddSYCLIntelFPGAInitiationIntervalAttr(Decl *D,
-                                              const AttributeCommonInfo &CI,
-                                              Expr *E);
-  SYCLIntelFPGAInitiationIntervalAttr *MergeSYCLIntelFPGAInitiationIntervalAttr(
-      Decl *D, const SYCLIntelFPGAInitiationIntervalAttr &A);
+  SYCLIntelForcePow2DepthAttr *
+  MergeSYCLIntelForcePow2DepthAttr(Decl *D,
+                                   const SYCLIntelForcePow2DepthAttr &A);
+  void AddSYCLIntelInitiationIntervalAttr(Decl *D,
+                                          const AttributeCommonInfo &CI,
+                                          Expr *E);
+  SYCLIntelInitiationIntervalAttr *MergeSYCLIntelInitiationIntervalAttr(
+      Decl *D, const SYCLIntelInitiationIntervalAttr &A);
 
-  SYCLIntelFPGAMaxConcurrencyAttr *MergeSYCLIntelFPGAMaxConcurrencyAttr(
-      Decl *D, const SYCLIntelFPGAMaxConcurrencyAttr &A);
+  SYCLIntelMaxConcurrencyAttr *MergeSYCLIntelMaxConcurrencyAttr(
+      Decl *D, const SYCLIntelMaxConcurrencyAttr &A);
   void AddSYCLIntelMaxGlobalWorkDimAttr(Decl *D, const AttributeCommonInfo &CI,
                                         Expr *E);
   SYCLIntelMaxGlobalWorkDimAttr *
   MergeSYCLIntelMaxGlobalWorkDimAttr(Decl *D,
                                      const SYCLIntelMaxGlobalWorkDimAttr &A);
-  void AddIntelFPGABankWidthAttr(Decl *D, const AttributeCommonInfo &CI,
+  void AddSYCLIntelBankWidthAttr(Decl *D, const AttributeCommonInfo &CI,
                                  Expr *E);
-  IntelFPGABankWidthAttr *
-  MergeIntelFPGABankWidthAttr(Decl *D, const IntelFPGABankWidthAttr &A);
-  void AddIntelFPGANumBanksAttr(Decl *D, const AttributeCommonInfo &CI,
+  SYCLIntelBankWidthAttr *
+  MergeSYCLIntelBankWidthAttr(Decl *D, const SYCLIntelBankWidthAttr &A);
+  void AddSYCLIntelNumBanksAttr(Decl *D, const AttributeCommonInfo &CI,
                                 Expr *E);
-  IntelFPGANumBanksAttr *
-  MergeIntelFPGANumBanksAttr(Decl *D, const IntelFPGANumBanksAttr &A);
+  SYCLIntelNumBanksAttr *
+  MergeSYCLIntelNumBanksAttr(Decl *D, const SYCLIntelNumBanksAttr &A);
   SYCLDeviceHasAttr *MergeSYCLDeviceHasAttr(Decl *D,
                                             const SYCLDeviceHasAttr &A);
   void AddSYCLDeviceHasAttr(Decl *D, const AttributeCommonInfo &CI,
@@ -11173,11 +11173,11 @@ class Sema final {
   SYCLIntelPipeIOAttr *MergeSYCLIntelPipeIOAttr(Decl *D,
                                                 const SYCLIntelPipeIOAttr &A);
 
-  /// AddSYCLIntelFPGAMaxConcurrencyAttr - Adds a max_concurrency attribute to a
+  /// AddSYCLIntelMaxConcurrencyAttr - Adds a max_concurrency attribute to a
   /// particular declaration.
-  void AddSYCLIntelFPGAMaxConcurrencyAttr(Decl *D,
-                                          const AttributeCommonInfo &CI,
-                                          Expr *E);
+  void AddSYCLIntelMaxConcurrencyAttr(Decl *D,
+                                      const AttributeCommonInfo &CI,
+                                      Expr *E);
 
   bool checkNSReturnsRetainedReturnType(SourceLocation loc, QualType type);
   bool checkAllowedSYCLInitializer(VarDecl *VD);
diff --git a/clang/lib/AST/TypePrinter.cpp b/clang/lib/AST/TypePrinter.cpp
index 759426adcef70..691f5de74994b 100644
--- a/clang/lib/AST/TypePrinter.cpp
+++ b/clang/lib/AST/TypePrinter.cpp
@@ -1754,7 +1754,7 @@ void TypePrinter::printAttributedAfter(const AttributedType *T,
     // AttributedType nodes for them.
     break;
 
-  case attr::SYCLFPGAPipe:
+  case attr::SYCLIntelPipe:
     OS << "pipe";
     break;
 
diff --git a/clang/lib/CodeGen/CGLoopInfo.cpp b/clang/lib/CodeGen/CGLoopInfo.cpp
index ce3d048868db3..da67c18b63c24 100644
--- a/clang/lib/CodeGen/CGLoopInfo.cpp
+++ b/clang/lib/CodeGen/CGLoopInfo.cpp
@@ -1027,41 +1027,41 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx,
   // n - 'llvm.loop.intel.max_reinvocation_delay.count, i32 n' metadata will be
   // emitted
   for (const auto *A : Attrs) {
-    if (const auto *IntelFPGAIVDep = dyn_cast<SYCLIntelFPGAIVDepAttr>(A))
-      addSYCLIVDepInfo(Header->getContext(), IntelFPGAIVDep->getSafelenValue(),
-                       IntelFPGAIVDep->getArrayDecl());
+    if (const auto *SYCLIntelIVDep = dyn_cast<SYCLIntelIVDepAttr>(A))
+      addSYCLIVDepInfo(Header->getContext(), SYCLIntelIVDep->getSafelenValue(),
+                       SYCLIntelIVDep->getArrayDecl());
 
-    if (const auto *IntelFPGAII =
-            dyn_cast<SYCLIntelFPGAInitiationIntervalAttr>(A)) {
-      const auto *CE = cast<ConstantExpr>(IntelFPGAII->getIntervalExpr());
+    if (const auto *SYCLIntelII =
+            dyn_cast<SYCLIntelInitiationIntervalAttr>(A)) {
+      const auto *CE = cast<ConstantExpr>(SYCLIntelII->getIntervalExpr());
       llvm::APSInt ArgVal = CE->getResultAsAPSInt();
       setSYCLIInterval(ArgVal.getSExtValue());
     }
 
-    if (const auto *IntelFPGAMaxConcurrency =
-            dyn_cast<SYCLIntelFPGAMaxConcurrencyAttr>(A)) {
+    if (const auto *SYCLIntelMaxConcurrency =
+            dyn_cast<SYCLIntelMaxConcurrencyAttr>(A)) {
       const auto *CE =
-          cast<ConstantExpr>(IntelFPGAMaxConcurrency->getNThreadsExpr());
+          cast<ConstantExpr>(SYCLIntelMaxConcurrency->getNThreadsExpr());
       llvm::APSInt ArgVal = CE->getResultAsAPSInt();
       setSYCLMaxConcurrencyNThreads(ArgVal.getSExtValue());
     }
 
-    if (const auto *IntelFPGALoopCountAvg =
-            dyn_cast<SYCLIntelFPGALoopCountAttr>(A)) {
+    if (const auto *SYCLIntelLoopCountAvg =
+            dyn_cast<SYCLIntelLoopCountAttr>(A)) {
       const auto *CE =
-          cast<ConstantExpr>(IntelFPGALoopCountAvg->getNTripCount());
+          cast<ConstantExpr>(SYCLIntelLoopCountAvg->getNTripCount());
       llvm::APSInt ArgVal = CE->getResultAsAPSInt();
       const char *Var =
-          IntelFPGALoopCountAvg->isMax()   ? "llvm.loop.intel.loopcount_max"
-          : IntelFPGALoopCountAvg->isMin() ? "llvm.loop.intel.loopcount_min"
-          : IntelFPGALoopCountAvg->isAvg() ? "llvm.loop.intel.loopcount_avg"
+          SYCLIntelLoopCountAvg->isMax()   ? "llvm.loop.intel.loopcount_max"
+          : SYCLIntelLoopCountAvg->isMin() ? "llvm.loop.intel.loopcount_min"
+          : SYCLIntelLoopCountAvg->isAvg() ? "llvm.loop.intel.loopcount_avg"
                                            : "llvm.loop.intel.loopcount";
       setSYCLIntelFPGAVariantCount(Var, ArgVal.getSExtValue());
     }
 
-    if (const auto *IntelFPGALoopCoalesce =
-            dyn_cast<SYCLIntelFPGALoopCoalesceAttr>(A)) {
-      if (const auto *LCE = IntelFPGALoopCoalesce->getNExpr()) {
+    if (const auto *SYCLIntelLoopCoalesce =
+            dyn_cast<SYCLIntelLoopCoalesceAttr>(A)) {
+      if (const auto *LCE = SYCLIntelLoopCoalesce->getNExpr()) {
         const auto *CE = cast<ConstantExpr>(LCE);
         llvm::APSInt ArgVal = CE->getResultAsAPSInt();
         setSYCLLoopCoalesceNLevels(ArgVal.getSExtValue());
@@ -1070,31 +1070,31 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx,
       }
     }
 
-    if (isa<SYCLIntelFPGADisableLoopPipeliningAttr>(A))
+    if (isa<SYCLIntelDisableLoopPipeliningAttr>(A))
       setSYCLLoopPipeliningDisable();
 
-    if (const auto *IntelFPGAMaxInterleaving =
-            dyn_cast<SYCLIntelFPGAMaxInterleavingAttr>(A)) {
-      const auto *CE = cast<ConstantExpr>(IntelFPGAMaxInterleaving->getNExpr());
+    if (const auto *SYCLIntelMaxInterleaving =
+            dyn_cast<SYCLIntelMaxInterleavingAttr>(A)) {
+      const auto *CE = cast<ConstantExpr>(SYCLIntelMaxInterleaving->getNExpr());
       llvm::APSInt ArgVal = CE->getResultAsAPSInt();
       setSYCLMaxInterleavingNInvocations(ArgVal.getSExtValue());
     }
 
-    if (const auto *IntelFPGASpeculatedIterations =
-            dyn_cast<SYCLIntelFPGASpeculatedIterationsAttr>(A)) {
+    if (const auto *SYCLIntelSpeculatedIterations =
+            dyn_cast<SYCLIntelSpeculatedIterationsAttr>(A)) {
       const auto *CE =
-          cast<ConstantExpr>(IntelFPGASpeculatedIterations->getNExpr());
+          cast<ConstantExpr>(SYCLIntelSpeculatedIterations->getNExpr());
       llvm::APSInt ArgVal = CE->getResultAsAPSInt();
       setSYCLSpeculatedIterationsNIterations(ArgVal.getSExtValue());
     }
 
-    if (isa<SYCLIntelFPGANofusionAttr>(A))
+    if (isa<SYCLIntelNofusionAttr>(A))
       setSYCLNofusionEnable();
 
-    if (const auto *IntelFPGAMaxReinvocationDelay =
-            dyn_cast<SYCLIntelFPGAMaxReinvocationDelayAttr>(A)) {
+    if (const auto *SYCLIntelMaxReinvocationDelay =
+            dyn_cast<SYCLIntelMaxReinvocationDelayAttr>(A)) {
       const auto *CE = cast<ConstantExpr>(
-          IntelFPGAMaxReinvocationDelay->getNExpr());
+          SYCLIntelMaxReinvocationDelay->getNExpr());
       llvm::APSInt ArgVal = CE->getResultAsAPSInt();
       setSYCLMaxReinvocationDelayNCycles(ArgVal.getSExtValue());
     }
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index d0580607b6607..c7a97147c71ed 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -734,7 +734,7 @@ void CodeGenFunction::EmitKernelMetadata(const FunctionDecl *FD,
       Fn->setMetadata("no_global_work_offset", llvm::MDNode::get(Context, {}));
   }
 
-  if (const auto *A = FD->getAttr<SYCLIntelFPGAMaxConcurrencyAttr>()) {
+  if (const auto *A = FD->getAttr<SYCLIntelMaxConcurrencyAttr>()) {
     const auto *CE = cast<ConstantExpr>(A->getNThreadsExpr());
     llvm::APSInt ArgVal = CE->getResultAsAPSInt();
     llvm::Metadata *AttrMDArgs[] = {
@@ -742,14 +742,14 @@ void CodeGenFunction::EmitKernelMetadata(const FunctionDecl *FD,
     Fn->setMetadata("max_concurrency", llvm::MDNode::get(Context, AttrMDArgs));
   }
 
-  if (FD->hasAttr<SYCLIntelFPGADisableLoopPipeliningAttr>()) {
+  if (FD->hasAttr<SYCLIntelDisableLoopPipeliningAttr>()) {
     llvm::Metadata *AttrMDArgs[] = {
         llvm::ConstantAsMetadata::get(Builder.getInt32(1))};
     Fn->setMetadata("disable_loop_pipelining",
                     llvm::MDNode::get(Context, AttrMDArgs));
   }
 
-  if (const auto *A = FD->getAttr<SYCLIntelFPGAInitiationIntervalAttr>()) {
+  if (const auto *A = FD->getAttr<SYCLIntelInitiationIntervalAttr>()) {
     const auto *CE = cast<ConstantExpr>(A->getIntervalExpr());
     llvm::APSInt ArgVal = CE->getResultAsAPSInt();
     llvm::Metadata *AttrMDArgs[] = {
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index dcb3ea0453c25..a73e1fb97a06d 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -5104,17 +5104,17 @@ void CodeGenModule::setAspectsEnumDecl(const EnumDecl *ED) {
 void CodeGenModule::generateIntelFPGAAnnotation(
     const Decl *D, llvm::SmallString<256> &AnnotStr) {
   llvm::raw_svector_ostream Out(AnnotStr);
-  if (D->hasAttr<IntelFPGARegisterAttr>())
+  if (D->hasAttr<SYCLIntelRegisterAttr>())
     Out << "{register:1}";
-  if (auto const *MA = D->getAttr<IntelFPGAMemoryAttr>()) {
-    IntelFPGAMemoryAttr::MemoryKind Kind = MA->getKind();
+  if (auto const *MA = D->getAttr<SYCLIntelMemoryAttr>()) {
+    SYCLIntelMemoryAttr::MemoryKind Kind = MA->getKind();
     Out << "{memory:";
     switch (Kind) {
-    case IntelFPGAMemoryAttr::MLAB:
-    case IntelFPGAMemoryAttr::BlockRAM:
-      Out << IntelFPGAMemoryAttr::ConvertMemoryKindToStr(Kind);
+    case SYCLIntelMemoryAttr::MLAB:
+    case SYCLIntelMemoryAttr::BlockRAM:
+      Out << SYCLIntelMemoryAttr::ConvertMemoryKindToStr(Kind);
       break;
-    case IntelFPGAMemoryAttr::Default:
+    case SYCLIntelMemoryAttr::Default:
       Out << "DEFAULT";
       break;
     }
@@ -5138,25 +5138,25 @@ void CodeGenModule::generateIntelFPGAAnnotation(
       Out << '}';
     }
   }
-  if (D->hasAttr<IntelFPGASinglePumpAttr>())
+  if (D->hasAttr<SYCLIntelSinglePumpAttr>())
     Out << "{pump:1}";
-  if (D->hasAttr<IntelFPGADoublePumpAttr>())
+  if (D->hasAttr<SYCLIntelDoublePumpAttr>())
     Out << "{pump:2}";
-  if (const auto *BWA = D->getAttr<IntelFPGABankWidthAttr>()) {
+  if (const auto *BWA = D->getAttr<SYCLIntelBankWidthAttr>()) {
     llvm::APSInt BWAInt = BWA->getValue()->EvaluateKnownConstInt(getContext());
     Out << '{' << BWA->getSpelling() << ':' << BWAInt << '}';
   }
-  if (const auto *PCA = D->getAttr<IntelFPGAPrivateCopiesAttr>()) {
+  if (const auto *PCA = D->getAttr<SYCLIntelPrivateCopiesAttr>()) {
     llvm::APSInt PCAInt = PCA->getValue()->EvaluateKnownConstInt(getContext());
     Out << '{' << PCA->getSpelling() << ':' << PCAInt << '}';
   }
-  if (const auto *NBA = D->getAttr<IntelFPGANumBanksAttr>()) {
+  if (const auto *NBA = D->getAttr<SYCLIntelNumBanksAttr>()) {
     llvm::APSInt NBAInt = NBA->getValue()->EvaluateKnownConstInt(getContext());
     Out << '{' << NBA->getSpelling() << ':' << NBAInt << '}';
   }
-  if (const auto *BBA = D->getAttr<IntelFPGABankBitsAttr>()) {
+  if (const auto *BBA = D->getAttr<SYCLIntelBankBitsAttr>()) {
     Out << '{' << BBA->getSpelling() << ':';
-    for (IntelFPGABankBitsAttr::args_iterator I = BBA->args_begin(),
+    for (SYCLIntelBankBitsAttr::args_iterator I = BBA->args_begin(),
                                               E = BBA->args_end();
          I != E; ++I) {
       if (I != BBA->args_begin())
@@ -5166,17 +5166,17 @@ void CodeGenModule::generateIntelFPGAAnnotation(
     }
     Out << '}';
   }
-  if (const auto *MRA = D->getAttr<IntelFPGAMaxReplicatesAttr>()) {
+  if (const auto *MRA = D->getAttr<SYCLIntelMaxReplicatesAttr>()) {
     llvm::APSInt MRAInt = MRA->getValue()->EvaluateKnownConstInt(getContext());
     Out << '{' << MRA->getSpelling() << ':' << MRAInt << '}';
   }
-  if (const auto *MA = D->getAttr<IntelFPGAMergeAttr>()) {
+  if (const auto *MA = D->getAttr<SYCLIntelMergeAttr>()) {
     Out << '{' << MA->getSpelling() << ':' << MA->getName() << ':'
         << MA->getDirection() << '}';
   }
-  if (D->hasAttr<IntelFPGASimpleDualPortAttr>())
+  if (D->hasAttr<SYCLIntelSimpleDualPortAttr>())
     Out << "{simple_dual_port:1}";
-  if (const auto *FP2D = D->getAttr<IntelFPGAForcePow2DepthAttr>()) {
+  if (const auto *FP2D = D->getAttr<SYCLIntelForcePow2DepthAttr>()) {
     llvm::APSInt FP2DInt =
         FP2D->getValue()->EvaluateKnownConstInt(getContext());
     Out << '{' << FP2D->getSpelling() << ':' << FP2DInt << '}';
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 8d74734b024ab..02b2cc1f12d2a 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -2962,24 +2962,24 @@ static bool mergeDeclAttribute(Sema &S, NamedDecl *D,
     NewAttr = S.MergeSYCLIntelSchedulerTargetFmaxMhzAttr(D, *A);
   else if (const auto *A = dyn_cast<SYCLIntelNoGlobalWorkOffsetAttr>(Attr))
     NewAttr = S.MergeSYCLIntelNoGlobalWorkOffsetAttr(D, *A);
-  else if (const auto *A = dyn_cast<IntelFPGAMaxReplicatesAttr>(Attr))
-    NewAttr = S.MergeIntelFPGAMaxReplicatesAttr(D, *A);
-  else if (const auto *A = dyn_cast<SYCLIntelFPGAMaxConcurrencyAttr>(Attr))
-    NewAttr = S.MergeSYCLIntelFPGAMaxConcurrencyAttr(D, *A);
-  else if (const auto *A = dyn_cast<IntelFPGAForcePow2DepthAttr>(Attr))
-    NewAttr = S.MergeIntelFPGAForcePow2DepthAttr(D, *A);
-  else if (const auto *A = dyn_cast<SYCLIntelFPGAInitiationIntervalAttr>(Attr))
-    NewAttr = S.MergeSYCLIntelFPGAInitiationIntervalAttr(D, *A);
+  else if (const auto *A = dyn_cast<SYCLIntelMaxReplicatesAttr>(Attr))
+    NewAttr = S.MergeSYCLIntelMaxReplicatesAttr(D, *A);
+  else if (const auto *A = dyn_cast<SYCLIntelMaxConcurrencyAttr>(Attr))
+    NewAttr = S.MergeSYCLIntelMaxConcurrencyAttr(D, *A);
+  else if (const auto *A = dyn_cast<SYCLIntelForcePow2DepthAttr>(Attr))
+    NewAttr = S.MergeSYCLIntelForcePow2DepthAttr(D, *A);
+  else if (const auto *A = dyn_cast<SYCLIntelInitiationIntervalAttr>(Attr))
+    NewAttr = S.MergeSYCLIntelInitiationIntervalAttr(D, *A);
   else if (const auto *A = dyn_cast<WorkGroupSizeHintAttr>(Attr))
     NewAttr = S.MergeWorkGroupSizeHintAttr(D, *A);
   else if (const auto *A = dyn_cast<SYCLIntelMaxGlobalWorkDimAttr>(Attr))
     NewAttr = S.MergeSYCLIntelMaxGlobalWorkDimAttr(D, *A);
   else if (const auto *BTFA = dyn_cast<BTFDeclTagAttr>(Attr))
     NewAttr = S.mergeBTFDeclTagAttr(D, *BTFA);
-  else if (const auto *A = dyn_cast<IntelFPGABankWidthAttr>(Attr))
-    NewAttr = S.MergeIntelFPGABankWidthAttr(D, *A);
-  else if (const auto *A = dyn_cast<IntelFPGANumBanksAttr>(Attr))
-    NewAttr = S.MergeIntelFPGANumBanksAttr(D, *A);
+  else if (const auto *A = dyn_cast<SYCLIntelBankWidthAttr>(Attr))
+    NewAttr = S.MergeSYCLIntelBankWidthAttr(D, *A);
+  else if (const auto *A = dyn_cast<SYCLIntelNumBanksAttr>(Attr))
+    NewAttr = S.MergeSYCLIntelNumBanksAttr(D, *A);
   else if (const auto *A = dyn_cast<SYCLDeviceHasAttr>(Attr))
     NewAttr = S.MergeSYCLDeviceHasAttr(D, *A);
   else if (const auto *A = dyn_cast<SYCLUsesAspectsAttr>(Attr))
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index dc1f6ebba01f4..ca2da59bb52e8 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -325,7 +325,7 @@ void Sema::DiagnoseDeprecatedAttribute(const ParsedAttr &A, StringRef NewScope,
 void Sema::CheckDeprecatedSYCLAttributeSpelling(const ParsedAttr &A,
                                                 StringRef NewName) {
   // Additionally, diagnose the old [[intel::ii]] spelling.
-  if (A.getKind() == ParsedAttr::AT_SYCLIntelFPGAInitiationInterval &&
+  if (A.getKind() == ParsedAttr::AT_SYCLIntelInitiationInterval &&
       A.getAttrName()->isStr("ii")) {
     DiagnoseDeprecatedAttribute(A, "intel", "initiation_interval");
     return;
@@ -4091,9 +4091,9 @@ static void handleSYCLIntelUseStallEnableClustersAttr(Sema &S, Decl *D,
 }
 
 // Handles initiation_interval attribute.
-void Sema::AddSYCLIntelFPGAInitiationIntervalAttr(Decl *D,
-                                                  const AttributeCommonInfo &CI,
-                                                  Expr *E) {
+void Sema::AddSYCLIntelInitiationIntervalAttr(Decl *D,
+                                              const AttributeCommonInfo &CI,
+                                              Expr *E) {
   if (!E->isValueDependent()) {
     // Validate that we have an integer constant expression and then store the
     // converted constant expression into the semantic attribute so that we
@@ -4112,7 +4112,7 @@ void Sema::AddSYCLIntelFPGAInitiationIntervalAttr(Decl *D,
     // Check to see if there's a duplicate attribute with different values
     // already applied to the declaration.
     if (const auto *DeclAttr =
-            D->getAttr<SYCLIntelFPGAInitiationIntervalAttr>()) {
+            D->getAttr<SYCLIntelInitiationIntervalAttr>()) {
       // If the other attribute argument is instantiation dependent, we won't
       // have converted it to a constant expression yet and thus we test
       // whether this is a null pointer.
@@ -4129,16 +4129,16 @@ void Sema::AddSYCLIntelFPGAInitiationIntervalAttr(Decl *D,
   }
 
   D->addAttr(::new (Context)
-                 SYCLIntelFPGAInitiationIntervalAttr(Context, CI, E));
+                 SYCLIntelInitiationIntervalAttr(Context, CI, E));
 }
 
-SYCLIntelFPGAInitiationIntervalAttr *
-Sema::MergeSYCLIntelFPGAInitiationIntervalAttr(
-    Decl *D, const SYCLIntelFPGAInitiationIntervalAttr &A) {
+SYCLIntelInitiationIntervalAttr *
+Sema::MergeSYCLIntelInitiationIntervalAttr(
+    Decl *D, const SYCLIntelInitiationIntervalAttr &A) {
   // Check to see if there's a duplicate attribute with different values
   // already applied to the declaration.
   if (const auto *DeclAttr =
-          D->getAttr<SYCLIntelFPGAInitiationIntervalAttr>()) {
+          D->getAttr<SYCLIntelInitiationIntervalAttr>()) {
     if (const auto *DeclExpr =
             dyn_cast<ConstantExpr>(DeclAttr->getIntervalExpr())) {
       if (const auto *MergeExpr = dyn_cast<ConstantExpr>(A.getIntervalExpr())) {
@@ -4153,14 +4153,14 @@ Sema::MergeSYCLIntelFPGAInitiationIntervalAttr(
   }
 
   return ::new (Context)
-      SYCLIntelFPGAInitiationIntervalAttr(Context, A, A.getIntervalExpr());
+      SYCLIntelInitiationIntervalAttr(Context, A, A.getIntervalExpr());
 }
 
-static void handleSYCLIntelFPGAInitiationIntervalAttr(Sema &S, Decl *D,
+static void handleSYCLIntelInitiationIntervalAttr(Sema &S, Decl *D,
                                                       const ParsedAttr &A) {
   S.CheckDeprecatedSYCLAttributeSpelling(A);
 
-  S.AddSYCLIntelFPGAInitiationIntervalAttr(D, A, A.getArgAsExpr(0));
+  S.AddSYCLIntelInitiationIntervalAttr(D, A, A.getArgAsExpr(0));
 }
 
 // Handle scheduler_target_fmax_mhz
@@ -6925,52 +6925,52 @@ static void handleSYCLIntelNoGlobalWorkOffsetAttr(Sema &S, Decl *D,
 }
 
 /// Handle the [[intel::singlepump]] attribute.
-static void handleSYCLIntelFPGASinglePumpAttr(Sema &S, Decl *D,
-                                              const ParsedAttr &AL) {
-  checkForDuplicateAttribute<IntelFPGASinglePumpAttr>(S, D, AL);
+static void handleSYCLIntelSinglePumpAttr(Sema &S, Decl *D,
+                                          const ParsedAttr &AL) {
+  checkForDuplicateAttribute<SYCLIntelSinglePumpAttr>(S, D, AL);
 
   // If the declaration does not have an [[intel::fpga_memory]]
   // attribute, this creates one as an implicit attribute.
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        S.Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        S.Context, SYCLIntelMemoryAttr::Default));
 
-  D->addAttr(::new (S.Context) IntelFPGASinglePumpAttr(S.Context, AL));
+  D->addAttr(::new (S.Context) SYCLIntelSinglePumpAttr(S.Context, AL));
 }
 
 /// Handle the [[intel::doublepump]] attribute.
-static void handleSYCLIntelFPGADoublePumpAttr(Sema &S, Decl *D,
-                                              const ParsedAttr &AL) {
-  checkForDuplicateAttribute<IntelFPGADoublePumpAttr>(S, D, AL);
+static void handleSYCLIntelDoublePumpAttr(Sema &S, Decl *D,
+                                          const ParsedAttr &AL) {
+  checkForDuplicateAttribute<SYCLIntelDoublePumpAttr>(S, D, AL);
 
   // If the declaration does not have an [[intel::fpga_memory]]
   // attribute, this creates one as an implicit attribute.
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        S.Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        S.Context, SYCLIntelMemoryAttr::Default));
 
-  D->addAttr(::new (S.Context) IntelFPGADoublePumpAttr(S.Context, AL));
+  D->addAttr(::new (S.Context) SYCLIntelDoublePumpAttr(S.Context, AL));
 }
 
 /// Handle the [[intel::fpga_memory]] attribute.
 /// This is incompatible with the [[intel::fpga_register]] attribute.
-static void handleIntelFPGAMemoryAttr(Sema &S, Decl *D,
-                                      const ParsedAttr &AL) {
-  checkForDuplicateAttribute<IntelFPGAMemoryAttr>(S, D, AL);
-  if (checkAttrMutualExclusion<IntelFPGARegisterAttr>(S, D, AL))
+static void handleSYCLIntelMemoryAttr(Sema &S, Decl *D,
+                                  const ParsedAttr &AL) {
+  checkForDuplicateAttribute<SYCLIntelMemoryAttr>(S, D, AL);
+  if (checkAttrMutualExclusion<SYCLIntelRegisterAttr>(S, D, AL))
     return;
 
-  IntelFPGAMemoryAttr::MemoryKind Kind;
+  SYCLIntelMemoryAttr::MemoryKind Kind;
   if (AL.getNumArgs() == 0)
-    Kind = IntelFPGAMemoryAttr::Default;
+    Kind = SYCLIntelMemoryAttr::Default;
   else {
     StringRef Str;
     if (!S.checkStringLiteralArgumentAttr(AL, 0, Str))
       return;
     if (Str.empty() ||
-        !IntelFPGAMemoryAttr::ConvertStrToMemoryKind(Str, Kind)) {
+        !SYCLIntelMemoryAttr::ConvertStrToMemoryKind(Str, Kind)) {
       SmallString<256> ValidStrings;
-      IntelFPGAMemoryAttr::generateValidStrings(ValidStrings);
+      SYCLIntelMemoryAttr::generateValidStrings(ValidStrings);
       S.Diag(AL.getLoc(), diag::err_intel_fpga_memory_arg_invalid)
           << AL << ValidStrings;
       return;
@@ -6978,11 +6978,11 @@ static void handleIntelFPGAMemoryAttr(Sema &S, Decl *D,
   }
 
   // We are adding a user memory attribute, drop any implicit default.
-  if (auto *MA = D->getAttr<IntelFPGAMemoryAttr>())
+  if (auto *MA = D->getAttr<SYCLIntelMemoryAttr>())
     if (MA->isImplicit())
-      D->dropAttr<IntelFPGAMemoryAttr>();
+      D->dropAttr<SYCLIntelMemoryAttr>();
 
-  D->addAttr(::new (S.Context) IntelFPGAMemoryAttr(S.Context, AL, Kind));
+  D->addAttr(::new (S.Context) SYCLIntelMemoryAttr(S.Context, AL, Kind));
 }
 
 /// Check for and diagnose attributes incompatible with register.
@@ -6990,9 +6990,9 @@ static void handleIntelFPGAMemoryAttr(Sema &S, Decl *D,
 static bool checkIntelFPGARegisterAttrCompatibility(Sema &S, Decl *D,
                                                     const ParsedAttr &Attr) {
   bool InCompat = false;
-  if (auto *MA = D->getAttr<IntelFPGAMemoryAttr>())
+  if (auto *MA = D->getAttr<SYCLIntelMemoryAttr>())
     if (!MA->isImplicit() &&
-        checkAttrMutualExclusion<IntelFPGAMemoryAttr>(S, D, Attr))
+        checkAttrMutualExclusion<SYCLIntelMemoryAttr>(S, D, Attr))
       InCompat = true;
 
   return InCompat;
@@ -7000,12 +7000,13 @@ static bool checkIntelFPGARegisterAttrCompatibility(Sema &S, Decl *D,
 
 /// Handle the [[intel::fpga_register]] attribute.
 /// This is incompatible with most of the other memory attributes.
-static void handleIntelFPGARegisterAttr(Sema &S, Decl *D, const ParsedAttr &A) {
-  checkForDuplicateAttribute<IntelFPGARegisterAttr>(S, D, A);
+static void handleSYCLIntelRegisterAttr(Sema &S, Decl *D,
+		                        const ParsedAttr &A) {
+  checkForDuplicateAttribute<SYCLIntelRegisterAttr>(S, D, A);
   if (checkIntelFPGARegisterAttrCompatibility(S, D, A))
     return;
 
-  handleSimpleAttribute<IntelFPGARegisterAttr>(S, D, A);
+  handleSimpleAttribute<SYCLIntelRegisterAttr>(S, D, A);
 }
 
 /// Handle the [[intel::bankwidth]] and [[intel::numbanks]] attributes.
@@ -7014,7 +7015,7 @@ static void handleIntelFPGARegisterAttr(Sema &S, Decl *D, const ParsedAttr &A) {
 /// The numbanks and bank_bits attributes are related.  If bank_bits exists
 /// when handling numbanks they are checked for consistency.
 
-void Sema::AddIntelFPGABankWidthAttr(Decl *D, const AttributeCommonInfo &CI,
+void Sema::AddSYCLIntelBankWidthAttr(Decl *D, const AttributeCommonInfo &CI,
                                      Expr *E) {
   if (!E->isValueDependent()) {
     // Validate that we have an integer constant expression and then store the
@@ -7042,7 +7043,7 @@ void Sema::AddIntelFPGABankWidthAttr(Decl *D, const AttributeCommonInfo &CI,
 
     // Check to see if there's a duplicate attribute with different values
     // already applied to the declaration.
-    if (const auto *DeclAttr = D->getAttr<IntelFPGABankWidthAttr>()) {
+    if (const auto *DeclAttr = D->getAttr<SYCLIntelBankWidthAttr>()) {
       // If the other attribute argument is instantiation dependent, we won't
       // have converted it to a constant expression yet and thus we test
       // whether this is a null pointer.
@@ -7059,18 +7060,18 @@ void Sema::AddIntelFPGABankWidthAttr(Decl *D, const AttributeCommonInfo &CI,
 
   // If the declaration does not have an [[intel::fpga_memory]]
   // attribute, this creates one as an implicit attribute.
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        Context, SYCLIntelMemoryAttr::Default));
 
-  D->addAttr(::new (Context) IntelFPGABankWidthAttr(Context, CI, E));
+  D->addAttr(::new (Context) SYCLIntelBankWidthAttr(Context, CI, E));
 }
 
-IntelFPGABankWidthAttr *
-Sema::MergeIntelFPGABankWidthAttr(Decl *D, const IntelFPGABankWidthAttr &A) {
+SYCLIntelBankWidthAttr *
+Sema::MergeSYCLIntelBankWidthAttr(Decl *D, const SYCLIntelBankWidthAttr &A) {
   // Check to see if there's a duplicate attribute with different values
   // already applied to the declaration.
-  if (const auto *DeclAttr = D->getAttr<IntelFPGABankWidthAttr>()) {
+  if (const auto *DeclAttr = D->getAttr<SYCLIntelBankWidthAttr>()) {
     const auto *DeclExpr = dyn_cast<ConstantExpr>(DeclAttr->getValue());
     const auto *MergeExpr = dyn_cast<ConstantExpr>(A.getValue());
     if (DeclExpr && MergeExpr &&
@@ -7081,15 +7082,15 @@ Sema::MergeIntelFPGABankWidthAttr(Decl *D, const IntelFPGABankWidthAttr &A) {
     }
   }
 
-  return ::new (Context) IntelFPGABankWidthAttr(Context, A, A.getValue());
+  return ::new (Context) SYCLIntelBankWidthAttr(Context, A, A.getValue());
 }
 
-static void handleIntelFPGABankWidthAttr(Sema &S, Decl *D,
+static void handleSYCLIntelBankWidthAttr(Sema &S, Decl *D,
                                          const ParsedAttr &A) {
-  S.AddIntelFPGABankWidthAttr(D, A, A.getArgAsExpr(0));
+  S.AddSYCLIntelBankWidthAttr(D, A, A.getArgAsExpr(0));
 }
 
-void Sema::AddIntelFPGANumBanksAttr(Decl *D, const AttributeCommonInfo &CI,
+void Sema::AddSYCLIntelNumBanksAttr(Decl *D, const AttributeCommonInfo &CI,
                                     Expr *E) {
   if (!E->isValueDependent()) {
     // Validate that we have an integer constant expression and then store the
@@ -7116,7 +7117,7 @@ void Sema::AddIntelFPGANumBanksAttr(Decl *D, const AttributeCommonInfo &CI,
     }
 
     // Check or add the related BankBits attribute.
-    if (auto *BBA = D->getAttr<IntelFPGABankBitsAttr>()) {
+    if (auto *BBA = D->getAttr<SYCLIntelBankBitsAttr>()) {
       unsigned NumBankBits = BBA->args_size();
       if (NumBankBits != ArgVal.ceilLogBase2()) {
         Diag(E->getExprLoc(), diag::err_bankbits_numbanks_conflicting) << CI;
@@ -7126,7 +7127,7 @@ void Sema::AddIntelFPGANumBanksAttr(Decl *D, const AttributeCommonInfo &CI,
 
     // Check to see if there's a duplicate attribute with different values
     // already applied to the declaration.
-    if (const auto *DeclAttr = D->getAttr<IntelFPGANumBanksAttr>()) {
+    if (const auto *DeclAttr = D->getAttr<SYCLIntelNumBanksAttr>()) {
       // If the other attribute argument is instantiation dependent, we won't
       // have converted it to a constant expression yet and thus we test
       // whether this is a null pointer.
@@ -7143,24 +7144,24 @@ void Sema::AddIntelFPGANumBanksAttr(Decl *D, const AttributeCommonInfo &CI,
 
   // If the declaration does not have an [[intel::fpga_memory]]
   // attribute, this creates one as an implicit attribute.
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        Context, SYCLIntelMemoryAttr::Default));
 
   // We are adding a user NumBanks attribute, drop any implicit default.
-  if (auto *NBA = D->getAttr<IntelFPGANumBanksAttr>()) {
+  if (auto *NBA = D->getAttr<SYCLIntelNumBanksAttr>()) {
     if (NBA->isImplicit())
-      D->dropAttr<IntelFPGANumBanksAttr>();
+      D->dropAttr<SYCLIntelNumBanksAttr>();
   }
 
-  D->addAttr(::new (Context) IntelFPGANumBanksAttr(Context, CI, E));
+  D->addAttr(::new (Context) SYCLIntelNumBanksAttr(Context, CI, E));
 }
 
-IntelFPGANumBanksAttr *
-Sema::MergeIntelFPGANumBanksAttr(Decl *D, const IntelFPGANumBanksAttr &A) {
+SYCLIntelNumBanksAttr *
+Sema::MergeSYCLIntelNumBanksAttr(Decl *D, const SYCLIntelNumBanksAttr &A) {
   // Check to see if there's a duplicate attribute with different values
   // already applied to the declaration.
-  if (const auto *DeclAttr = D->getAttr<IntelFPGANumBanksAttr>()) {
+  if (const auto *DeclAttr = D->getAttr<SYCLIntelNumBanksAttr>()) {
     const auto *DeclExpr = dyn_cast<ConstantExpr>(DeclAttr->getValue());
     const auto *MergeExpr = dyn_cast<ConstantExpr>(A.getValue());
     if (DeclExpr && MergeExpr &&
@@ -7171,26 +7172,26 @@ Sema::MergeIntelFPGANumBanksAttr(Decl *D, const IntelFPGANumBanksAttr &A) {
     }
   }
 
-  return ::new (Context) IntelFPGANumBanksAttr(Context, A, A.getValue());
+  return ::new (Context) SYCLIntelNumBanksAttr(Context, A, A.getValue());
 }
 
-static void handleIntelFPGANumBanksAttr(Sema &S, Decl *D, const ParsedAttr &A) {
-  S.AddIntelFPGANumBanksAttr(D, A, A.getArgAsExpr(0));
+static void handleSYCLIntelNumBanksAttr(Sema &S, Decl *D, const ParsedAttr &A) {
+  S.AddSYCLIntelNumBanksAttr(D, A, A.getArgAsExpr(0));
 }
 
-static void handleIntelFPGASimpleDualPortAttr(Sema &S, Decl *D,
-                                              const ParsedAttr &AL) {
-  checkForDuplicateAttribute<IntelFPGASimpleDualPortAttr>(S, D, AL);
+static void handleIntelSimpleDualPortAttr(Sema &S, Decl *D,
+                                          const ParsedAttr &AL) {
+  checkForDuplicateAttribute<SYCLIntelSimpleDualPortAttr>(S, D, AL);
 
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        S.Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        S.Context, SYCLIntelMemoryAttr::Default));
 
   D->addAttr(::new (S.Context)
-                 IntelFPGASimpleDualPortAttr(S.Context, AL));
+                 SYCLIntelSimpleDualPortAttr(S.Context, AL));
 }
 
-void Sema::AddIntelFPGAMaxReplicatesAttr(Decl *D, const AttributeCommonInfo &CI,
+void Sema::AddSYCLIntelMaxReplicatesAttr(Decl *D, const AttributeCommonInfo &CI,
                                          Expr *E) {
   if (!E->isValueDependent()) {
     // Validate that we have an integer constant expression and then store the
@@ -7209,7 +7210,7 @@ void Sema::AddIntelFPGAMaxReplicatesAttr(Decl *D, const AttributeCommonInfo &CI,
     }
     // Check to see if there's a duplicate attribute with different values
     // already applied to the declaration.
-    if (const auto *DeclAttr = D->getAttr<IntelFPGAMaxReplicatesAttr>()) {
+    if (const auto *DeclAttr = D->getAttr<SYCLIntelMaxReplicatesAttr>()) {
       // If the other attribute argument is instantiation dependent, we won't
       // have converted it to a constant expression yet and thus we test
       // whether this is a null pointer.
@@ -7226,19 +7227,19 @@ void Sema::AddIntelFPGAMaxReplicatesAttr(Decl *D, const AttributeCommonInfo &CI,
 
   // If the declaration does not have an [[intel::fpga_memory]]
   // attribute, this creates one as an implicit attribute.
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        Context, SYCLIntelMemoryAttr::Default));
 
-  D->addAttr(::new (Context) IntelFPGAMaxReplicatesAttr(Context, CI, E));
+  D->addAttr(::new (Context) SYCLIntelMaxReplicatesAttr(Context, CI, E));
 }
 
-IntelFPGAMaxReplicatesAttr *
-Sema::MergeIntelFPGAMaxReplicatesAttr(Decl *D,
-                                      const IntelFPGAMaxReplicatesAttr &A) {
+SYCLIntelMaxReplicatesAttr *
+Sema::MergeSYCLIntelMaxReplicatesAttr(Decl *D,
+                                      const SYCLIntelMaxReplicatesAttr &A) {
   // Check to see if there's a duplicate attribute with different values
   // already applied to the declaration.
-  if (const auto *DeclAttr = D->getAttr<IntelFPGAMaxReplicatesAttr>()) {
+  if (const auto *DeclAttr = D->getAttr<SYCLIntelMaxReplicatesAttr>()) {
     if (const auto *DeclExpr = dyn_cast<ConstantExpr>(DeclAttr->getValue())) {
       if (const auto *MergeExpr = dyn_cast<ConstantExpr>(A.getValue())) {
         if (DeclExpr->getResultAsAPSInt() != MergeExpr->getResultAsAPSInt()) {
@@ -7251,20 +7252,20 @@ Sema::MergeIntelFPGAMaxReplicatesAttr(Decl *D,
     }
   }
 
-  return ::new (Context) IntelFPGAMaxReplicatesAttr(Context, A, A.getValue());
+  return ::new (Context) SYCLIntelMaxReplicatesAttr(Context, A, A.getValue());
 }
 
-static void handleIntelFPGAMaxReplicatesAttr(Sema &S, Decl *D,
-                                             const ParsedAttr &A) {
-  S.AddIntelFPGAMaxReplicatesAttr(D, A, A.getArgAsExpr(0));
+static void handleSYCLIntelMaxReplicatesAttr(Sema &S, Decl *D,
+                                          const ParsedAttr &A) {
+  S.AddSYCLIntelMaxReplicatesAttr(D, A, A.getArgAsExpr(0));
 }
 
 /// Handle the merge attribute.
 /// This requires two string arguments.  The first argument is a name, the
 /// second is a direction.  The direction must be "depth" or "width".
 /// This is incompatible with the register attribute.
-static void handleIntelFPGAMergeAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
-  checkForDuplicateAttribute<IntelFPGAMergeAttr>(S, D, AL);
+static void handleSYCLIntelMergeAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
+  checkForDuplicateAttribute<SYCLIntelMergeAttr>(S, D, AL);
 
   SmallVector<StringRef, 2> Results;
   for (int I = 0; I < 2; I++) {
@@ -7279,12 +7280,12 @@ static void handleIntelFPGAMergeAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
     Results.push_back(Str);
   }
 
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        S.Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        S.Context, SYCLIntelMemoryAttr::Default));
 
   D->addAttr(::new (S.Context)
-                 IntelFPGAMergeAttr(S.Context, AL, Results[0], Results[1]));
+                 SYCLIntelMergeAttr(S.Context, AL, Results[0], Results[1]));
 }
 
 /// Handle the bank_bits attribute.
@@ -7295,8 +7296,8 @@ static void handleIntelFPGAMergeAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
 /// hasn't been added yet an implicit one is added with the correct value.
 /// If the user later adds a numbanks attribute the implicit one is removed.
 /// The values must be consecutive values (i.e. 3,4,5 or 2,1).
-static void handleIntelFPGABankBitsAttr(Sema &S, Decl *D, const ParsedAttr &A) {
-  checkForDuplicateAttribute<IntelFPGABankBitsAttr>(S, D, A);
+static void handleSYCLIntelBankBitsAttr(Sema &S, Decl *D, const ParsedAttr &A) {
+  checkForDuplicateAttribute<SYCLIntelBankBitsAttr>(S, D, A);
 
   if (!A.checkAtLeastNumArgs(S, 1))
     return;
@@ -7306,12 +7307,12 @@ static void handleIntelFPGABankBitsAttr(Sema &S, Decl *D, const ParsedAttr &A) {
     Args.push_back(A.getArgAsExpr(I));
   }
 
-  S.AddIntelFPGABankBitsAttr(D, A, Args.data(), Args.size());
+  S.AddSYCLIntelBankBitsAttr(D, A, Args.data(), Args.size());
 }
 
-void Sema::AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
+void Sema::AddSYCLIntelBankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
                                     Expr **Exprs, unsigned Size) {
-  IntelFPGABankBitsAttr TmpAttr(Context, CI, Exprs, Size);
+  SYCLIntelBankBitsAttr TmpAttr(Context, CI, Exprs, Size);
   SmallVector<Expr *, 8> Args;
   SmallVector<int64_t, 8> Values;
   bool ListIsValueDep = false;
@@ -7346,7 +7347,7 @@ void Sema::AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
   }
 
   // Check or add the related numbanks attribute.
-  if (auto *NBA = D->getAttr<IntelFPGANumBanksAttr>()) {
+  if (auto *NBA = D->getAttr<SYCLIntelNumBanksAttr>()) {
     Expr *E = NBA->getValue();
     if (!E->isValueDependent()) {
       Expr::EvalResult Result;
@@ -7361,18 +7362,18 @@ void Sema::AddIntelFPGABankBitsAttr(Decl *D, const AttributeCommonInfo &CI,
     llvm::APInt Num(32, (unsigned)(1 << Args.size()));
     Expr *NBE =
         IntegerLiteral::Create(Context, Num, Context.IntTy, SourceLocation());
-    D->addAttr(IntelFPGANumBanksAttr::CreateImplicit(Context, NBE));
+    D->addAttr(SYCLIntelNumBanksAttr::CreateImplicit(Context, NBE));
   }
 
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        Context, SYCLIntelMemoryAttr::Default));
 
   D->addAttr(::new (Context)
-                 IntelFPGABankBitsAttr(Context, CI, Args.data(), Args.size()));
+                 SYCLIntelBankBitsAttr(Context, CI, Args.data(), Args.size()));
 }
 
-void Sema::AddIntelFPGAPrivateCopiesAttr(Decl *D, const AttributeCommonInfo &CI,
+void Sema::AddSYCLIntelPrivateCopiesAttr(Decl *D, const AttributeCommonInfo &CI,
                                          Expr *E) {
   if (!E->isValueDependent()) {
     // Validate that we have an integer constant expression and then store the
@@ -7391,7 +7392,7 @@ void Sema::AddIntelFPGAPrivateCopiesAttr(Decl *D, const AttributeCommonInfo &CI,
     }
     // Check to see if there's a duplicate attribute with different values
     // already applied to the declaration.
-    if (const auto *DeclAttr = D->getAttr<IntelFPGAPrivateCopiesAttr>()) {
+    if (const auto *DeclAttr = D->getAttr<SYCLIntelPrivateCopiesAttr>()) {
       // If the other attribute argument is instantiation dependent, we won't
       // have converted it to a constant expression yet and thus we test
       // whether this is a null pointer.
@@ -7408,19 +7409,19 @@ void Sema::AddIntelFPGAPrivateCopiesAttr(Decl *D, const AttributeCommonInfo &CI,
 
   // If the declaration does not have [[intel::fpga_memory]]
   // attribute, this creates default implicit memory.
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        Context, SYCLIntelMemoryAttr::Default));
 
-  D->addAttr(::new (Context) IntelFPGAPrivateCopiesAttr(Context, CI, E));
+  D->addAttr(::new (Context) SYCLIntelPrivateCopiesAttr(Context, CI, E));
 }
 
-static void handleIntelFPGAPrivateCopiesAttr(Sema &S, Decl *D,
+static void handleSYCLIntelPrivateCopiesAttr(Sema &S, Decl *D,
                                              const ParsedAttr &A) {
-  S.AddIntelFPGAPrivateCopiesAttr(D, A, A.getArgAsExpr(0));
+  S.AddSYCLIntelPrivateCopiesAttr(D, A, A.getArgAsExpr(0));
 }
 
-void Sema::AddIntelFPGAForcePow2DepthAttr(Decl *D,
+void Sema::AddSYCLIntelForcePow2DepthAttr(Decl *D,
                                           const AttributeCommonInfo &CI,
                                           Expr *E) {
   if (!E->isValueDependent()) {
@@ -7442,7 +7443,7 @@ void Sema::AddIntelFPGAForcePow2DepthAttr(Decl *D,
 
     // Check to see if there's a duplicate attribute with different values
     // already applied to the declaration.
-    if (const auto *DeclAttr = D->getAttr<IntelFPGAForcePow2DepthAttr>()) {
+    if (const auto *DeclAttr = D->getAttr<SYCLIntelForcePow2DepthAttr>()) {
       // If the other attribute argument is instantiation dependent, we won't
       // have converted it to a constant expression yet and thus we test
       // whether this is a null pointer.
@@ -7459,19 +7460,19 @@ void Sema::AddIntelFPGAForcePow2DepthAttr(Decl *D,
 
   // If the declaration does not have an [[intel::fpga_memory]]
   // attribute, this creates one as an implicit attribute.
-  if (!D->hasAttr<IntelFPGAMemoryAttr>())
-    D->addAttr(IntelFPGAMemoryAttr::CreateImplicit(
-        Context, IntelFPGAMemoryAttr::Default));
+  if (!D->hasAttr<SYCLIntelMemoryAttr>())
+    D->addAttr(SYCLIntelMemoryAttr::CreateImplicit(
+        Context, SYCLIntelMemoryAttr::Default));
 
-  D->addAttr(::new (Context) IntelFPGAForcePow2DepthAttr(Context, CI, E));
+  D->addAttr(::new (Context) SYCLIntelForcePow2DepthAttr(Context, CI, E));
 }
 
-IntelFPGAForcePow2DepthAttr *
-Sema::MergeIntelFPGAForcePow2DepthAttr(Decl *D,
-                                       const IntelFPGAForcePow2DepthAttr &A) {
+SYCLIntelForcePow2DepthAttr *
+Sema::MergeSYCLIntelForcePow2DepthAttr(Decl *D,
+                                       const SYCLIntelForcePow2DepthAttr &A) {
   // Check to see if there's a duplicate attribute with different values
   // already applied to the declaration.
-  if (const auto *DeclAttr = D->getAttr<IntelFPGAForcePow2DepthAttr>()) {
+  if (const auto *DeclAttr = D->getAttr<SYCLIntelForcePow2DepthAttr>()) {
     if (const auto *DeclExpr = dyn_cast<ConstantExpr>(DeclAttr->getValue())) {
       if (const auto *MergeExpr = dyn_cast<ConstantExpr>(A.getValue())) {
         if (DeclExpr->getResultAsAPSInt() != MergeExpr->getResultAsAPSInt()) {
@@ -7484,12 +7485,12 @@ Sema::MergeIntelFPGAForcePow2DepthAttr(Decl *D,
     }
   }
 
-  return ::new (Context) IntelFPGAForcePow2DepthAttr(Context, A, A.getValue());
+  return ::new (Context) SYCLIntelForcePow2DepthAttr(Context, A, A.getValue());
 }
 
-static void handleIntelFPGAForcePow2DepthAttr(Sema &S, Decl *D,
+static void handleSYCLIntelForcePow2DepthAttr(Sema &S, Decl *D,
                                               const ParsedAttr &A) {
-  S.AddIntelFPGAForcePow2DepthAttr(D, A, A.getArgAsExpr(0));
+  S.AddSYCLIntelForcePow2DepthAttr(D, A, A.getArgAsExpr(0));
 }
 
 static void handleXRayLogArgsAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
@@ -7600,11 +7601,11 @@ static void handleSYCLIntelPipeIOAttr(Sema &S, Decl *D, const ParsedAttr &A) {
   S.addSYCLIntelPipeIOAttr(D, A, E);
 }
 
-SYCLIntelFPGAMaxConcurrencyAttr *Sema::MergeSYCLIntelFPGAMaxConcurrencyAttr(
-    Decl *D, const SYCLIntelFPGAMaxConcurrencyAttr &A) {
+SYCLIntelMaxConcurrencyAttr *Sema::MergeSYCLIntelMaxConcurrencyAttr(
+    Decl *D, const SYCLIntelMaxConcurrencyAttr &A) {
   // Check to see if there's a duplicate attribute with different values
   // already applied to the declaration.
-  if (const auto *DeclAttr = D->getAttr<SYCLIntelFPGAMaxConcurrencyAttr>()) {
+  if (const auto *DeclAttr = D->getAttr<SYCLIntelMaxConcurrencyAttr>()) {
     if (const auto *DeclExpr =
             dyn_cast<ConstantExpr>(DeclAttr->getNThreadsExpr())) {
       if (const auto *MergeExpr = dyn_cast<ConstantExpr>(A.getNThreadsExpr())) {
@@ -7619,12 +7620,12 @@ SYCLIntelFPGAMaxConcurrencyAttr *Sema::MergeSYCLIntelFPGAMaxConcurrencyAttr(
   }
 
   return ::new (Context)
-      SYCLIntelFPGAMaxConcurrencyAttr(Context, A, A.getNThreadsExpr());
+      SYCLIntelMaxConcurrencyAttr(Context, A, A.getNThreadsExpr());
 }
 
-void Sema::AddSYCLIntelFPGAMaxConcurrencyAttr(Decl *D,
-                                              const AttributeCommonInfo &CI,
-                                              Expr *E) {
+void Sema::AddSYCLIntelMaxConcurrencyAttr(Decl *D,
+                                          const AttributeCommonInfo &CI,
+                                          Expr *E) {
   if (!E->isValueDependent()) {
     llvm::APSInt ArgVal;
     ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal);
@@ -7641,7 +7642,7 @@ void Sema::AddSYCLIntelFPGAMaxConcurrencyAttr(Decl *D,
 
     // Check to see if there's a duplicate attribute with different values
     // already applied to the declaration.
-    if (const auto *DeclAttr = D->getAttr<SYCLIntelFPGAMaxConcurrencyAttr>()) {
+    if (const auto *DeclAttr = D->getAttr<SYCLIntelMaxConcurrencyAttr>()) {
       // If the other attribute argument is instantiation dependent, we won't
       // have converted it to a constant expression yet and thus we test
       // whether this is a null pointer.
@@ -7657,13 +7658,13 @@ void Sema::AddSYCLIntelFPGAMaxConcurrencyAttr(Decl *D,
     }
   }
 
-  D->addAttr(::new (Context) SYCLIntelFPGAMaxConcurrencyAttr(Context, CI, E));
+  D->addAttr(::new (Context) SYCLIntelMaxConcurrencyAttr(Context, CI, E));
 }
 
-static void handleSYCLIntelFPGAMaxConcurrencyAttr(Sema &S, Decl *D,
-                                                  const ParsedAttr &A) {
+static void handleSYCLIntelMaxConcurrencyAttr(Sema &S, Decl *D,
+                                              const ParsedAttr &A) {
   Expr *E = A.getArgAsExpr(0);
-  S.AddSYCLIntelFPGAMaxConcurrencyAttr(D, A, E);
+  S.AddSYCLIntelMaxConcurrencyAttr(D, A, E);
 }
 
 // Checks if an expression is a valid filter list for an add_ir_attributes_*
@@ -11487,8 +11488,8 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL,
   case ParsedAttr::AT_SYCLIntelLoopFuse:
     handleSYCLIntelLoopFuseAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_SYCLIntelFPGAInitiationInterval:
-    handleSYCLIntelFPGAInitiationIntervalAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelInitiationInterval:
+    handleSYCLIntelInitiationIntervalAttr(S, D, AL);
     break;
   case ParsedAttr::AT_VecTypeHint:
     handleVecTypeHint(S, D, AL);
@@ -11769,47 +11770,47 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL,
     break;
 
   // Intel FPGA specific attributes
-  case ParsedAttr::AT_IntelFPGADoublePump:
-    handleSYCLIntelFPGADoublePumpAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelDoublePump:
+    handleSYCLIntelDoublePumpAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGASinglePump:
-    handleSYCLIntelFPGASinglePumpAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelSinglePump:
+    handleSYCLIntelSinglePumpAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGAMemory:
-    handleIntelFPGAMemoryAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelMemory:
+    handleSYCLIntelMemoryAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGARegister:
-    handleIntelFPGARegisterAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelRegister:
+    handleSYCLIntelRegisterAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGABankWidth:
-    handleIntelFPGABankWidthAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelBankWidth:
+    handleSYCLIntelBankWidthAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGANumBanks:
-    handleIntelFPGANumBanksAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelNumBanks:
+    handleSYCLIntelNumBanksAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGAPrivateCopies:
-    handleIntelFPGAPrivateCopiesAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelPrivateCopies:
+    handleSYCLIntelPrivateCopiesAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGAMaxReplicates:
-    handleIntelFPGAMaxReplicatesAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelMaxReplicates:
+    handleSYCLIntelMaxReplicatesAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGASimpleDualPort:
-    handleIntelFPGASimpleDualPortAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelSimpleDualPort:
+    handleIntelSimpleDualPortAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGAMerge:
-    handleIntelFPGAMergeAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelMerge:
+    handleSYCLIntelMergeAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGABankBits:
-    handleIntelFPGABankBitsAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelBankBits:
+    handleSYCLIntelBankBitsAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_IntelFPGAForcePow2Depth:
-    handleIntelFPGAForcePow2DepthAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelForcePow2Depth:
+    handleSYCLIntelForcePow2DepthAttr(S, D, AL);
     break;
   case ParsedAttr::AT_SYCLIntelPipeIO:
     handleSYCLIntelPipeIOAttr(S, D, AL);
     break;
-  case ParsedAttr::AT_SYCLIntelFPGAMaxConcurrency:
-    handleSYCLIntelFPGAMaxConcurrencyAttr(S, D, AL);
+  case ParsedAttr::AT_SYCLIntelMaxConcurrency:
+    handleSYCLIntelMaxConcurrencyAttr(S, D, AL);
     break;
   case ParsedAttr::AT_SYCLAddIRAttributesFunction:
     handleSYCLAddIRAttributesFunctionAttr(S, D, AL);
diff --git a/clang/lib/Sema/SemaSYCL.cpp b/clang/lib/Sema/SemaSYCL.cpp
index 6327e7015a12b..a5e4bfa36ad9e 100644
--- a/clang/lib/Sema/SemaSYCL.cpp
+++ b/clang/lib/Sema/SemaSYCL.cpp
@@ -540,9 +540,9 @@ static void collectSYCLAttributes(Sema &S, FunctionDecl *FD,
   // Attributes that should not be propagated from device functions to a kernel.
   if (DirectlyCalled) {
     llvm::copy_if(FD->getAttrs(), std::back_inserter(Attrs), [](Attr *A) {
-      return isa<SYCLIntelLoopFuseAttr, SYCLIntelFPGAMaxConcurrencyAttr,
-                 SYCLIntelFPGADisableLoopPipeliningAttr,
-                 SYCLIntelFPGAInitiationIntervalAttr,
+      return isa<SYCLIntelLoopFuseAttr, SYCLIntelMaxConcurrencyAttr,
+                 SYCLIntelDisableLoopPipeliningAttr,
+                 SYCLIntelInitiationIntervalAttr,
                  SYCLIntelUseStallEnableClustersAttr, SYCLDeviceHasAttr,
                  SYCLAddIRAttributesFunctionAttr>(A);
     });
@@ -4433,9 +4433,9 @@ static void PropagateAndDiagnoseDeviceAttr(
   case attr::Kind::SYCLIntelMaxGlobalWorkDim:
   case attr::Kind::SYCLIntelNoGlobalWorkOffset:
   case attr::Kind::SYCLIntelLoopFuse:
-  case attr::Kind::SYCLIntelFPGAMaxConcurrency:
-  case attr::Kind::SYCLIntelFPGADisableLoopPipelining:
-  case attr::Kind::SYCLIntelFPGAInitiationInterval:
+  case attr::Kind::SYCLIntelMaxConcurrency:
+  case attr::Kind::SYCLIntelDisableLoopPipelining:
+  case attr::Kind::SYCLIntelInitiationInterval:
   case attr::Kind::SYCLIntelUseStallEnableClusters:
   case attr::Kind::SYCLDeviceHas:
   case attr::Kind::SYCLAddIRAttributesFunction:
diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp
index 0d26b4e4a9123..d938d79b4ef84 100644
--- a/clang/lib/Sema/SemaStmtAttr.cpp
+++ b/clang/lib/Sema/SemaStmtAttr.cpp
@@ -68,9 +68,9 @@ static Attr *handleSuppressAttr(Sema &S, Stmt *St, const ParsedAttr &A,
       S.Context, A, DiagnosticIdentifiers.data(), DiagnosticIdentifiers.size());
 }
 
-SYCLIntelFPGAMaxConcurrencyAttr *
-Sema::BuildSYCLIntelFPGAMaxConcurrencyAttr(const AttributeCommonInfo &CI,
-                                           Expr *E) {
+SYCLIntelMaxConcurrencyAttr *
+Sema::BuildSYCLIntelMaxConcurrencyAttr(const AttributeCommonInfo &CI,
+                                       Expr *E) {
   if (!E->isValueDependent()) {
     llvm::APSInt ArgVal;
     ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal);
@@ -86,20 +86,20 @@ Sema::BuildSYCLIntelFPGAMaxConcurrencyAttr(const AttributeCommonInfo &CI,
     }
   }
 
-  return new (Context) SYCLIntelFPGAMaxConcurrencyAttr(Context, CI, E);
+  return new (Context) SYCLIntelMaxConcurrencyAttr(Context, CI, E);
 }
 
-static Attr *handleSYCLIntelFPGAMaxConcurrencyAttr(Sema &S, Stmt *St,
-                                                   const ParsedAttr &A) {
+static Attr *handleSYCLIntelMaxConcurrencyAttr(Sema &S, Stmt *St,
+                                               const ParsedAttr &A) {
   S.CheckDeprecatedSYCLAttributeSpelling(A);
 
   Expr *E = A.getArgAsExpr(0);
-  return S.BuildSYCLIntelFPGAMaxConcurrencyAttr(A, E);
+  return S.BuildSYCLIntelMaxConcurrencyAttr(A, E);
 }
 
-SYCLIntelFPGAInitiationIntervalAttr *
-Sema::BuildSYCLIntelFPGAInitiationIntervalAttr(const AttributeCommonInfo &CI,
-                                               Expr *E) {
+SYCLIntelInitiationIntervalAttr *
+Sema::BuildSYCLIntelInitiationIntervalAttr(const AttributeCommonInfo &CI,
+                                           Expr *E) {
   if (!E->isValueDependent()) {
     llvm::APSInt ArgVal;
     ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal);
@@ -115,20 +115,20 @@ Sema::BuildSYCLIntelFPGAInitiationIntervalAttr(const AttributeCommonInfo &CI,
     }
   }
 
-  return new (Context) SYCLIntelFPGAInitiationIntervalAttr(Context, CI, E);
+  return new (Context) SYCLIntelInitiationIntervalAttr(Context, CI, E);
 }
 
-static Attr *handleSYCLIntelFPGAInitiationIntervalAttr(Sema &S, Stmt *St,
-                                                       const ParsedAttr &A) {
+static Attr *handleSYCLIntelInitiationIntervalAttr(Sema &S, Stmt *St,
+                                                   const ParsedAttr &A) {
   S.CheckDeprecatedSYCLAttributeSpelling(A);
 
   Expr *E = A.getArgAsExpr(0);
-  return S.BuildSYCLIntelFPGAInitiationIntervalAttr(A, E);
+  return S.BuildSYCLIntelInitiationIntervalAttr(A, E);
 }
 
-SYCLIntelFPGAMaxInterleavingAttr *
-Sema::BuildSYCLIntelFPGAMaxInterleavingAttr(const AttributeCommonInfo &CI,
-                                            Expr *E) {
+SYCLIntelMaxInterleavingAttr *
+Sema::BuildSYCLIntelMaxInterleavingAttr(const AttributeCommonInfo &CI,
+                       		        Expr *E) {
   if (!E->isValueDependent()) {
     llvm::APSInt ArgVal;
     ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal);
@@ -144,20 +144,20 @@ Sema::BuildSYCLIntelFPGAMaxInterleavingAttr(const AttributeCommonInfo &CI,
     }
   }
 
-  return new (Context) SYCLIntelFPGAMaxInterleavingAttr(Context, CI, E);
+  return new (Context) SYCLIntelMaxInterleavingAttr(Context, CI, E);
 }
 
-static Attr *handleSYCLIntelFPGAMaxInterleavingAttr(Sema &S, Stmt *St,
-                                                    const ParsedAttr &A) {
+static Attr *handleSYCLIntelMaxInterleavingAttr(Sema &S, Stmt *St,
+                                                const ParsedAttr &A) {
   S.CheckDeprecatedSYCLAttributeSpelling(A);
 
   Expr *E = A.getArgAsExpr(0);
-  return S.BuildSYCLIntelFPGAMaxInterleavingAttr(A, E);
+  return S.BuildSYCLIntelMaxInterleavingAttr(A, E);
 }
 
-SYCLIntelFPGALoopCoalesceAttr *
-Sema::BuildSYCLIntelFPGALoopCoalesceAttr(const AttributeCommonInfo &CI,
-                                         Expr *E) {
+SYCLIntelLoopCoalesceAttr *
+Sema::BuildSYCLIntelLoopCoalesceAttr(const AttributeCommonInfo &CI,
+                                     Expr *E) {
   if (E && !E->isValueDependent()) {
     llvm::APSInt ArgVal;
     ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal);
@@ -173,20 +173,20 @@ Sema::BuildSYCLIntelFPGALoopCoalesceAttr(const AttributeCommonInfo &CI,
     }
   }
 
-  return new (Context) SYCLIntelFPGALoopCoalesceAttr(Context, CI, E);
+  return new (Context) SYCLIntelLoopCoalesceAttr(Context, CI, E);
 }
 
-static Attr *handleSYCLIntelFPGALoopCoalesceAttr(Sema &S, Stmt *St,
-                                                 const ParsedAttr &A) {
+static Attr *handleSYCLIntelLoopCoalesceAttr(Sema &S, Stmt *St,
+                                             const ParsedAttr &A) {
   S.CheckDeprecatedSYCLAttributeSpelling(A);
 
   Expr *E = A.isArgExpr(0) ? A.getArgAsExpr(0) : nullptr;
-  return S.BuildSYCLIntelFPGALoopCoalesceAttr(A, E);
+  return S.BuildSYCLIntelLoopCoalesceAttr(A, E);
 }
 
-SYCLIntelFPGASpeculatedIterationsAttr *
-Sema::BuildSYCLIntelFPGASpeculatedIterationsAttr(const AttributeCommonInfo &CI,
-                                                 Expr *E) {
+SYCLIntelSpeculatedIterationsAttr *
+Sema::BuildSYCLIntelSpeculatedIterationsAttr(const AttributeCommonInfo &CI,
+                                             Expr *E) {
   if (!E->isValueDependent()) {
     llvm::APSInt ArgVal;
     ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal);
@@ -202,24 +202,24 @@ Sema::BuildSYCLIntelFPGASpeculatedIterationsAttr(const AttributeCommonInfo &CI,
     }
   }
 
-  return new (Context) SYCLIntelFPGASpeculatedIterationsAttr(Context, CI, E);
+  return new (Context) SYCLIntelSpeculatedIterationsAttr(Context, CI, E);
 }
 
-static Attr *handleSYCLIntelFPGASpeculatedIterationsAttr(Sema &S, Stmt *St,
-                                                         const ParsedAttr &A) {
+static Attr *handleSYCLIntelSpeculatedIterationsAttr(Sema &S, Stmt *St,
+                                                     const ParsedAttr &A) {
   S.CheckDeprecatedSYCLAttributeSpelling(A);
 
   Expr *E = A.getArgAsExpr(0);
-  return S.BuildSYCLIntelFPGASpeculatedIterationsAttr(A, E);
+  return S.BuildSYCLIntelSpeculatedIterationsAttr(A, E);
 }
 
-static Attr *handleSYCLIntelFPGADisableLoopPipeliningAttr(Sema &S, Stmt *,
-                                                          const ParsedAttr &A) {
+static Attr *handleSYCLIntelDisableLoopPipeliningAttr(Sema &S, Stmt *,
+                                                      const ParsedAttr &A) {
   S.CheckDeprecatedSYCLAttributeSpelling(A);
-  return new (S.Context) SYCLIntelFPGADisableLoopPipeliningAttr(S.Context, A);
+  return new (S.Context) SYCLIntelDisableLoopPipeliningAttr(S.Context, A);
 }
 
-static bool checkSYCLIntelFPGAIVDepSafeLen(Sema &S, llvm::APSInt &Value,
+static bool checkSYCLIntelIVDepSafeLen(Sema &S, llvm::APSInt &Value,
                                            Expr *E) {
   // This attribute requires a non-negative value.
   if (!Value.isNonNegative())
@@ -237,8 +237,8 @@ enum class IVDepExprResult {
   SafeLen,
 };
 
-static IVDepExprResult HandleFPGAIVDepAttrExpr(Sema &S, Expr *E,
-                                               unsigned &SafelenValue) {
+static IVDepExprResult HandleIVDepAttrExpr(Sema &S, Expr *E,
+                                           unsigned &SafelenValue) {
   if (!E)
     return IVDepExprResult::Null;
 
@@ -247,7 +247,7 @@ static IVDepExprResult HandleFPGAIVDepAttrExpr(Sema &S, Expr *E,
 
   Optional<llvm::APSInt> ArgVal = E->getIntegerConstantExpr(S.getASTContext());
   if (ArgVal) {
-    if (checkSYCLIntelFPGAIVDepSafeLen(S, *ArgVal, E))
+    if (checkSYCLIntelIVDepSafeLen(S, *ArgVal, E))
       return IVDepExprResult::Invalid;
     SafelenValue = ArgVal->getZExtValue();
     // ivdep attribute allows both safelen = 0 and safelen = 1 with a warning.
@@ -273,12 +273,12 @@ static IVDepExprResult HandleFPGAIVDepAttrExpr(Sema &S, Expr *E,
 
 // Note: At the time of this call, we don't know the order of the expressions,
 // so we name them vaguely until we can figure it out.
-SYCLIntelFPGAIVDepAttr *
-Sema::BuildSYCLIntelFPGAIVDepAttr(const AttributeCommonInfo &CI, Expr *Expr1,
+SYCLIntelIVDepAttr *
+Sema::BuildSYCLIntelIVDepAttr(const AttributeCommonInfo &CI, Expr *Expr1,
                                   Expr *Expr2) {
   unsigned SafelenValue = 0;
-  IVDepExprResult E1 = HandleFPGAIVDepAttrExpr(*this, Expr1, SafelenValue);
-  IVDepExprResult E2 = HandleFPGAIVDepAttrExpr(*this, Expr2, SafelenValue);
+  IVDepExprResult E1 = HandleIVDepAttrExpr(*this, Expr1, SafelenValue);
+  IVDepExprResult E2 = HandleIVDepAttrExpr(*this, Expr2, SafelenValue);
 
   if (E1 == IVDepExprResult::Invalid || E2 == IVDepExprResult::Invalid)
     return nullptr;
@@ -301,7 +301,7 @@ Sema::BuildSYCLIntelFPGAIVDepAttr(const AttributeCommonInfo &CI, Expr *Expr1,
   }
 
   return new (Context)
-      SYCLIntelFPGAIVDepAttr(Context, CI, SafeLenExpr, ArrayExpr, SafelenValue);
+      SYCLIntelIVDepAttr(Context, CI, SafeLenExpr, ArrayExpr, SafelenValue);
 }
 
 // Filters out any attributes from the list that are either not the specified
@@ -322,34 +322,34 @@ static void FilterAttributeList(ArrayRef<const Attr *> Attrs,
 }
 
 static void
-CheckRedundantSYCLIntelFPGAIVDepAttrs(Sema &S, ArrayRef<const Attr *> Attrs) {
+CheckRedundantSYCLIntelIVDepAttrs(Sema &S, ArrayRef<const Attr *> Attrs) {
   // Skip SEMA if we're in a template, this will be diagnosed later.
   if (S.getCurLexicalContext()->isDependentContext())
     return;
 
-  SmallVector<const SYCLIntelFPGAIVDepAttr *, 8> FilteredAttrs;
+  SmallVector<const SYCLIntelIVDepAttr *, 8> FilteredAttrs;
   // Filter down to just non-dependent ivdeps.
   FilterAttributeList(Attrs, FilteredAttrs);
   if (FilteredAttrs.empty())
     return;
 
-  SmallVector<const SYCLIntelFPGAIVDepAttr *, 8> SortedAttrs(FilteredAttrs);
-  llvm::stable_sort(SortedAttrs, SYCLIntelFPGAIVDepAttr::SafelenCompare);
+  SmallVector<const SYCLIntelIVDepAttr *, 8> SortedAttrs(FilteredAttrs);
+  llvm::stable_sort(SortedAttrs, SYCLIntelIVDepAttr::SafelenCompare);
 
   // Find the maximum without an array expression, which ends up in the 2nd
   // expr.
   const auto *GlobalMaxItr =
-      llvm::find_if(SortedAttrs, [](const SYCLIntelFPGAIVDepAttr *A) {
+      llvm::find_if(SortedAttrs, [](const SYCLIntelIVDepAttr *A) {
         return !A->getArrayExpr();
       });
-  const SYCLIntelFPGAIVDepAttr *GlobalMax =
+  const SYCLIntelIVDepAttr *GlobalMax =
       GlobalMaxItr == SortedAttrs.end() ? nullptr : *GlobalMaxItr;
 
   for (const auto *A : FilteredAttrs) {
     if (A == GlobalMax)
       continue;
 
-    if (GlobalMax && !SYCLIntelFPGAIVDepAttr::SafelenCompare(A, GlobalMax)) {
+    if (GlobalMax && !SYCLIntelIVDepAttr::SafelenCompare(A, GlobalMax)) {
       S.Diag(A->getLocation(), diag::warn_ivdep_redundant)
           << !GlobalMax->isInf() << GlobalMax->getSafelenValue() << !A->isInf()
           << A->getSafelenValue();
@@ -362,13 +362,13 @@ CheckRedundantSYCLIntelFPGAIVDepAttrs(Sema &S, ArrayRef<const Attr *> Attrs) {
 
     const ValueDecl *ArrayDecl = A->getArrayDecl();
     auto Other = llvm::find_if(SortedAttrs,
-                               [ArrayDecl](const SYCLIntelFPGAIVDepAttr *A) {
+                               [ArrayDecl](const SYCLIntelIVDepAttr *A) {
                                  return ArrayDecl == A->getArrayDecl();
                                });
     assert(Other != SortedAttrs.end() && "Should find at least itself");
 
     // Diagnose if lower/equal to the lowest with this array.
-    if (*Other != A && !SYCLIntelFPGAIVDepAttr::SafelenCompare(A, *Other)) {
+    if (*Other != A && !SYCLIntelIVDepAttr::SafelenCompare(A, *Other)) {
       S.Diag(A->getLocation(), diag::warn_ivdep_redundant)
           << !(*Other)->isInf() << (*Other)->getSafelenValue() << !A->isInf()
           << A->getSafelenValue();
@@ -377,12 +377,12 @@ CheckRedundantSYCLIntelFPGAIVDepAttrs(Sema &S, ArrayRef<const Attr *> Attrs) {
   }
 }
 
-static Attr *handleIntelFPGAIVDepAttr(Sema &S, Stmt *St, const ParsedAttr &A) {
+static Attr *handleIntelIVDepAttr(Sema &S, Stmt *St, const ParsedAttr &A) {
   unsigned NumArgs = A.getNumArgs();
 
   S.CheckDeprecatedSYCLAttributeSpelling(A);
 
-  return S.BuildSYCLIntelFPGAIVDepAttr(
+  return S.BuildSYCLIntelIVDepAttr(
       A, NumArgs >= 1 ? A.getArgAsExpr(0) : nullptr,
       NumArgs == 2 ? A.getArgAsExpr(1) : nullptr);
 }
@@ -390,15 +390,15 @@ static Attr *handleIntelFPGAIVDepAttr(Sema &S, Stmt *St, const ParsedAttr &A) {
 static void
 CheckForDuplicateSYCLIntelLoopCountAttrs(Sema &S,
                                          ArrayRef<const Attr *> Attrs) {
-  // Create a list of SYCLIntelFPGALoopCount attributes only.
-  SmallVector<const SYCLIntelFPGALoopCountAttr *, 8> OnlyLoopCountAttrs;
+  // Create a list of SYCLIntelLoopCount attributes only.
+  SmallVector<const SYCLIntelLoopCountAttr *, 8> OnlyLoopCountAttrs;
   llvm::transform(
       Attrs, std::back_inserter(OnlyLoopCountAttrs), [](const Attr *A) {
-        return dyn_cast_or_null<const SYCLIntelFPGALoopCountAttr>(A);
+        return dyn_cast_or_null<const SYCLIntelLoopCountAttr>(A);
       });
   OnlyLoopCountAttrs.erase(
       std::remove(OnlyLoopCountAttrs.begin(), OnlyLoopCountAttrs.end(),
-                  static_cast<const SYCLIntelFPGALoopCountAttr *>(nullptr)),
+                  static_cast<const SYCLIntelLoopCountAttr *>(nullptr)),
       OnlyLoopCountAttrs.end());
   if (OnlyLoopCountAttrs.empty())
     return;
@@ -408,7 +408,7 @@ CheckForDuplicateSYCLIntelLoopCountAttrs(Sema &S,
   unsigned int AvgCount = 0;
   unsigned int Count = 0;
   for (const auto *A : OnlyLoopCountAttrs) {
-    const auto *At = dyn_cast<SYCLIntelFPGALoopCountAttr>(A);
+    const auto *At = dyn_cast<SYCLIntelLoopCountAttr>(A);
     At->isMin()   ? MinCount++
     : At->isMax() ? MaxCount++
     : At->isAvg() ? AvgCount++
@@ -418,8 +418,8 @@ CheckForDuplicateSYCLIntelLoopCountAttrs(Sema &S,
   }
 }
 
-SYCLIntelFPGALoopCountAttr *
-Sema::BuildSYCLIntelFPGALoopCountAttr(const AttributeCommonInfo &CI, Expr *E) {
+SYCLIntelLoopCountAttr *
+Sema::BuildSYCLIntelLoopCountAttr(const AttributeCommonInfo &CI, Expr *E) {
   if (!E->isValueDependent()) {
     llvm::APSInt ArgVal;
     ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal);
@@ -435,25 +435,25 @@ Sema::BuildSYCLIntelFPGALoopCountAttr(const AttributeCommonInfo &CI, Expr *E) {
     }
   }
 
-  return new (Context) SYCLIntelFPGALoopCountAttr(Context, CI, E);
+  return new (Context) SYCLIntelLoopCountAttr(Context, CI, E);
 }
 
-static Attr *handleSYCLIntelFPGALoopCountAttr(Sema &S, Stmt *St,
-                                              const ParsedAttr &A) {
+static Attr *handleSYCLIntelLoopCountAttr(Sema &S, Stmt *St,
+                                          const ParsedAttr &A) {
   S.CheckDeprecatedSYCLAttributeSpelling(A);
 
   Expr *E = A.getArgAsExpr(0);
-  return S.BuildSYCLIntelFPGALoopCountAttr(A, E);
+  return S.BuildSYCLIntelLoopCountAttr(A, E);
 }
 
-static Attr *handleIntelFPGANofusionAttr(Sema &S, Stmt *St,
-                                         const ParsedAttr &A) {
-  return new (S.Context) SYCLIntelFPGANofusionAttr(S.Context, A);
+static Attr *handleIntelNofusionAttr(Sema &S, Stmt *St,
+                                     const ParsedAttr &A) {
+  return new (S.Context) SYCLIntelNofusionAttr(S.Context, A);
 }
 
-SYCLIntelFPGAMaxReinvocationDelayAttr *
-Sema::BuildSYCLIntelFPGAMaxReinvocationDelayAttr(const AttributeCommonInfo &CI,
-                                                 Expr *E) {
+SYCLIntelMaxReinvocationDelayAttr *
+Sema::BuildSYCLIntelMaxReinvocationDelayAttr(const AttributeCommonInfo &CI,
+                                             Expr *E) {
   if (!E->isValueDependent()) {
     llvm::APSInt ArgVal;
     ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal);
@@ -469,15 +469,15 @@ Sema::BuildSYCLIntelFPGAMaxReinvocationDelayAttr(const AttributeCommonInfo &CI,
     }
   }
 
-  return new (Context) SYCLIntelFPGAMaxReinvocationDelayAttr(Context, CI, E);
+  return new (Context) SYCLIntelMaxReinvocationDelayAttr(Context, CI, E);
 }
 
-static Attr * handleSYCLIntelFPGAMaxReinvocationDelayAttr(Sema &S, Stmt *St,
+static Attr * handleSYCLIntelMaxReinvocationDelayAttr(Sema &S, Stmt *St,
                                                       const ParsedAttr &A) {
   S.CheckDeprecatedSYCLAttributeSpelling(A);
 
   Expr *E = A.getArgAsExpr(0);
-  return S.BuildSYCLIntelFPGAMaxReinvocationDelayAttr(A, E);
+  return S.BuildSYCLIntelMaxReinvocationDelayAttr(A, E);
 }
 
 static Attr *handleLoopHintAttr(Sema &S, Stmt *St, const ParsedAttr &A,
@@ -846,22 +846,22 @@ CheckForDuplicationSYCLLoopAttribute(Sema &S,
 
 static void CheckForIncompatibleSYCLLoopAttributes(
     Sema &S, const SmallVectorImpl<const Attr *> &Attrs) {
-  CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAInitiationIntervalAttr>(
+  CheckForDuplicationSYCLLoopAttribute<SYCLIntelInitiationIntervalAttr>(
       S, Attrs);
-  CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAMaxConcurrencyAttr>(S,
+  CheckForDuplicationSYCLLoopAttribute<SYCLIntelMaxConcurrencyAttr>(S,
                                                                         Attrs);
-  CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGALoopCoalesceAttr>(S, Attrs);
-  CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGADisableLoopPipeliningAttr>(
+  CheckForDuplicationSYCLLoopAttribute<SYCLIntelLoopCoalesceAttr>(S, Attrs);
+  CheckForDuplicationSYCLLoopAttribute<SYCLIntelDisableLoopPipeliningAttr>(
       S, Attrs);
-  CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAMaxInterleavingAttr>(S,
+  CheckForDuplicationSYCLLoopAttribute<SYCLIntelMaxInterleavingAttr>(S,
                                                                          Attrs);
-  CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGASpeculatedIterationsAttr>(
+  CheckForDuplicationSYCLLoopAttribute<SYCLIntelSpeculatedIterationsAttr>(
       S, Attrs);
   CheckForDuplicateSYCLIntelLoopCountAttrs(S, Attrs);
   CheckForDuplicationSYCLLoopAttribute<LoopUnrollHintAttr>(S, Attrs, false);
-  CheckRedundantSYCLIntelFPGAIVDepAttrs(S, Attrs);
-  CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGANofusionAttr>(S, Attrs);
-  CheckForDuplicationSYCLLoopAttribute<SYCLIntelFPGAMaxReinvocationDelayAttr>(
+  CheckRedundantSYCLIntelIVDepAttrs(S, Attrs);
+  CheckForDuplicationSYCLLoopAttribute<SYCLIntelNofusionAttr>(S, Attrs);
+  CheckForDuplicationSYCLLoopAttribute<SYCLIntelMaxReinvocationDelayAttr>(
       S, Attrs);
 }
 
@@ -975,22 +975,22 @@ static Attr *ProcessStmtAttribute(Sema &S, Stmt *St, const ParsedAttr &A,
     return handleFallThroughAttr(S, St, A, Range);
   case ParsedAttr::AT_LoopHint:
     return handleLoopHintAttr(S, St, A, Range);
-  case ParsedAttr::AT_SYCLIntelFPGAIVDep:
-    return handleIntelFPGAIVDepAttr(S, St, A);
-  case ParsedAttr::AT_SYCLIntelFPGAInitiationInterval:
-    return handleSYCLIntelFPGAInitiationIntervalAttr(S, St, A);
-  case ParsedAttr::AT_SYCLIntelFPGAMaxConcurrency:
-    return handleSYCLIntelFPGAMaxConcurrencyAttr(S, St, A);
-  case ParsedAttr::AT_SYCLIntelFPGALoopCoalesce:
-    return handleSYCLIntelFPGALoopCoalesceAttr(S, St, A);
-  case ParsedAttr::AT_SYCLIntelFPGADisableLoopPipelining:
-    return handleSYCLIntelFPGADisableLoopPipeliningAttr(S, St, A);
-  case ParsedAttr::AT_SYCLIntelFPGAMaxInterleaving:
-    return handleSYCLIntelFPGAMaxInterleavingAttr(S, St, A);
-  case ParsedAttr::AT_SYCLIntelFPGASpeculatedIterations:
-    return handleSYCLIntelFPGASpeculatedIterationsAttr(S, St, A);
-  case ParsedAttr::AT_SYCLIntelFPGALoopCount:
-    return handleSYCLIntelFPGALoopCountAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelIVDep:
+    return handleIntelIVDepAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelInitiationInterval:
+    return handleSYCLIntelInitiationIntervalAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelMaxConcurrency:
+    return handleSYCLIntelMaxConcurrencyAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelLoopCoalesce:
+    return handleSYCLIntelLoopCoalesceAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelDisableLoopPipelining:
+    return handleSYCLIntelDisableLoopPipeliningAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelMaxInterleaving:
+    return handleSYCLIntelMaxInterleavingAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelSpeculatedIterations:
+    return handleSYCLIntelSpeculatedIterationsAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelLoopCount:
+    return handleSYCLIntelLoopCountAttr(S, St, A);
   case ParsedAttr::AT_OpenCLUnrollHint:
   case ParsedAttr::AT_LoopUnrollHint:
     return handleLoopUnrollHint(S, St, A, Range);
@@ -1006,10 +1006,10 @@ static Attr *ProcessStmtAttribute(Sema &S, Stmt *St, const ParsedAttr &A,
     return handleLikely(S, St, A, Range);
   case ParsedAttr::AT_Unlikely:
     return handleUnlikely(S, St, A, Range);
-  case ParsedAttr::AT_SYCLIntelFPGANofusion:
-    return handleIntelFPGANofusionAttr(S, St, A);
-  case ParsedAttr::AT_SYCLIntelFPGAMaxReinvocationDelay:
-    return handleSYCLIntelFPGAMaxReinvocationDelayAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelNofusion:
+    return handleIntelNofusionAttr(S, St, A);
+  case ParsedAttr::AT_SYCLIntelMaxReinvocationDelay:
+    return handleSYCLIntelMaxReinvocationDelayAttr(S, St, A);
   default:
     // N.B., ClangAttrEmitter.cpp emits a diagnostic helper that ensures a
     // declaration attribute is not written on a statement, but this code is
@@ -1032,6 +1032,6 @@ void Sema::ProcessStmtAttributes(Stmt *S, const ParsedAttributes &InAttrs,
   CheckForIncompatibleUnrollHintAttributes(*this, OutAttrs, InAttrs.Range);
 }
 bool Sema::CheckRebuiltAttributedStmtAttributes(ArrayRef<const Attr *> Attrs) {
-  CheckRedundantSYCLIntelFPGAIVDepAttrs(*this, Attrs);
+  CheckRedundantSYCLIntelIVDepAttrs(*this, Attrs);
   return false;
 }
diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp
index 26528e5f9f024..0204dd9359673 100644
--- a/clang/lib/Sema/SemaTemplateInstantiate.cpp
+++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp
@@ -1266,29 +1266,29 @@ namespace {
                           bool AllowInjectedClassName = false);
 
     const LoopHintAttr *TransformLoopHintAttr(const LoopHintAttr *LH);
-    const SYCLIntelFPGAIVDepAttr *
-    TransformSYCLIntelFPGAIVDepAttr(const SYCLIntelFPGAIVDepAttr *IV);
-    const SYCLIntelFPGAInitiationIntervalAttr *
-    TransformSYCLIntelFPGAInitiationIntervalAttr(
-        const SYCLIntelFPGAInitiationIntervalAttr *II);
-    const SYCLIntelFPGAMaxConcurrencyAttr *
-    TransformSYCLIntelFPGAMaxConcurrencyAttr(
-        const SYCLIntelFPGAMaxConcurrencyAttr *MC);
+    const SYCLIntelIVDepAttr *
+    TransformSYCLIntelIVDepAttr(const SYCLIntelIVDepAttr *IV);
+    const SYCLIntelInitiationIntervalAttr *
+    TransformSYCLIntelInitiationIntervalAttr(
+        const SYCLIntelInitiationIntervalAttr *II);
+    const SYCLIntelMaxConcurrencyAttr *
+    TransformSYCLIntelMaxConcurrencyAttr(
+        const SYCLIntelMaxConcurrencyAttr *MC);
     const LoopUnrollHintAttr *
     TransformLoopUnrollHintAttr(const LoopUnrollHintAttr *LU);
-    const SYCLIntelFPGALoopCoalesceAttr *TransformSYCLIntelFPGALoopCoalesceAttr(
-        const SYCLIntelFPGALoopCoalesceAttr *LC);
-    const SYCLIntelFPGAMaxInterleavingAttr *
-    TransformSYCLIntelFPGAMaxInterleavingAttr(
-        const SYCLIntelFPGAMaxInterleavingAttr *MI);
-    const SYCLIntelFPGASpeculatedIterationsAttr *
-    TransformSYCLIntelFPGASpeculatedIterationsAttr(
-        const SYCLIntelFPGASpeculatedIterationsAttr *SI);
-    const SYCLIntelFPGALoopCountAttr *
-    TransformSYCLIntelFPGALoopCountAttr(const SYCLIntelFPGALoopCountAttr *SI);
-    const SYCLIntelFPGAMaxReinvocationDelayAttr *
-    TransformSYCLIntelFPGAMaxReinvocationDelayAttr(
-        const SYCLIntelFPGAMaxReinvocationDelayAttr *MRD);
+    const SYCLIntelLoopCoalesceAttr *TransformSYCLIntelLoopCoalesceAttr(
+        const SYCLIntelLoopCoalesceAttr *LC);
+    const SYCLIntelMaxInterleavingAttr *
+    TransformSYCLIntelMaxInterleavingAttr(
+        const SYCLIntelMaxInterleavingAttr *MI);
+    const SYCLIntelSpeculatedIterationsAttr *
+    TransformSYCLIntelSpeculatedIterationsAttr(
+        const SYCLIntelSpeculatedIterationsAttr *SI);
+    const SYCLIntelLoopCountAttr *
+    TransformSYCLIntelLoopCountAttr(const SYCLIntelLoopCountAttr *SI);
+    const SYCLIntelMaxReinvocationDelayAttr *
+    TransformSYCLIntelMaxReinvocationDelayAttr(
+        const SYCLIntelMaxReinvocationDelayAttr *MRD);
 
     ExprResult TransformPredefinedExpr(PredefinedExpr *E);
     ExprResult TransformDeclRefExpr(DeclRefExpr *E);
@@ -1768,9 +1768,9 @@ TemplateInstantiator::TransformLoopHintAttr(const LoopHintAttr *LH) {
                                       LH->getState(), TransformedExpr, *LH);
 }
 
-const SYCLIntelFPGAIVDepAttr *
-TemplateInstantiator::TransformSYCLIntelFPGAIVDepAttr(
-    const SYCLIntelFPGAIVDepAttr *IVDep) {
+const SYCLIntelIVDepAttr *
+TemplateInstantiator::TransformSYCLIntelIVDepAttr(
+    const SYCLIntelIVDepAttr *IVDep) {
 
   Expr *Expr1 = IVDep->getSafelenExpr()
                     ? getDerived().TransformExpr(IVDep->getSafelenExpr()).get()
@@ -1779,54 +1779,54 @@ TemplateInstantiator::TransformSYCLIntelFPGAIVDepAttr(
                     ? getDerived().TransformExpr(IVDep->getArrayExpr()).get()
                     : nullptr;
 
-  return getSema().BuildSYCLIntelFPGAIVDepAttr(*IVDep, Expr1, Expr2);
+  return getSema().BuildSYCLIntelIVDepAttr(*IVDep, Expr1, Expr2);
 }
 
-const SYCLIntelFPGAInitiationIntervalAttr *
-TemplateInstantiator::TransformSYCLIntelFPGAInitiationIntervalAttr(
-    const SYCLIntelFPGAInitiationIntervalAttr *II) {
+const SYCLIntelInitiationIntervalAttr *
+TemplateInstantiator::TransformSYCLIntelInitiationIntervalAttr(
+    const SYCLIntelInitiationIntervalAttr *II) {
   Expr *TransformedExpr =
       getDerived().TransformExpr(II->getIntervalExpr()).get();
-  return getSema().BuildSYCLIntelFPGAInitiationIntervalAttr(*II,
+  return getSema().BuildSYCLIntelInitiationIntervalAttr(*II,
                                                             TransformedExpr);
 }
 
-const SYCLIntelFPGAMaxConcurrencyAttr *
-TemplateInstantiator::TransformSYCLIntelFPGAMaxConcurrencyAttr(
-    const SYCLIntelFPGAMaxConcurrencyAttr *MC) {
+const SYCLIntelMaxConcurrencyAttr *
+TemplateInstantiator::TransformSYCLIntelMaxConcurrencyAttr(
+    const SYCLIntelMaxConcurrencyAttr *MC) {
   Expr *TransformedExpr =
       getDerived().TransformExpr(MC->getNThreadsExpr()).get();
-  return getSema().BuildSYCLIntelFPGAMaxConcurrencyAttr(*MC, TransformedExpr);
+  return getSema().BuildSYCLIntelMaxConcurrencyAttr(*MC, TransformedExpr);
 }
 
-const SYCLIntelFPGALoopCoalesceAttr *
-TemplateInstantiator::TransformSYCLIntelFPGALoopCoalesceAttr(
-    const SYCLIntelFPGALoopCoalesceAttr *LC) {
+const SYCLIntelLoopCoalesceAttr *
+TemplateInstantiator::TransformSYCLIntelLoopCoalesceAttr(
+    const SYCLIntelLoopCoalesceAttr *LC) {
   Expr *TransformedExpr = getDerived().TransformExpr(LC->getNExpr()).get();
-  return getSema().BuildSYCLIntelFPGALoopCoalesceAttr(*LC, TransformedExpr);
+  return getSema().BuildSYCLIntelLoopCoalesceAttr(*LC, TransformedExpr);
 }
 
-const SYCLIntelFPGAMaxInterleavingAttr *
-TemplateInstantiator::TransformSYCLIntelFPGAMaxInterleavingAttr(
-    const SYCLIntelFPGAMaxInterleavingAttr *MI) {
+const SYCLIntelMaxInterleavingAttr *
+TemplateInstantiator::TransformSYCLIntelMaxInterleavingAttr(
+    const SYCLIntelMaxInterleavingAttr *MI) {
   Expr *TransformedExpr = getDerived().TransformExpr(MI->getNExpr()).get();
-  return getSema().BuildSYCLIntelFPGAMaxInterleavingAttr(*MI, TransformedExpr);
+  return getSema().BuildSYCLIntelMaxInterleavingAttr(*MI, TransformedExpr);
 }
 
-const SYCLIntelFPGASpeculatedIterationsAttr *
-TemplateInstantiator::TransformSYCLIntelFPGASpeculatedIterationsAttr(
-    const SYCLIntelFPGASpeculatedIterationsAttr *SI) {
+const SYCLIntelSpeculatedIterationsAttr *
+TemplateInstantiator::TransformSYCLIntelSpeculatedIterationsAttr(
+    const SYCLIntelSpeculatedIterationsAttr *SI) {
   Expr *TransformedExpr = getDerived().TransformExpr(SI->getNExpr()).get();
-  return getSema().BuildSYCLIntelFPGASpeculatedIterationsAttr(*SI,
+  return getSema().BuildSYCLIntelSpeculatedIterationsAttr(*SI,
                                                               TransformedExpr);
 }
 
-const SYCLIntelFPGALoopCountAttr *
-TemplateInstantiator::TransformSYCLIntelFPGALoopCountAttr(
-    const SYCLIntelFPGALoopCountAttr *LCA) {
+const SYCLIntelLoopCountAttr *
+TemplateInstantiator::TransformSYCLIntelLoopCountAttr(
+    const SYCLIntelLoopCountAttr *LCA) {
   Expr *TransformedExpr =
       getDerived().TransformExpr(LCA->getNTripCount()).get();
-  return getSema().BuildSYCLIntelFPGALoopCountAttr(*LCA, TransformedExpr);
+  return getSema().BuildSYCLIntelLoopCountAttr(*LCA, TransformedExpr);
 }
 
 const LoopUnrollHintAttr *TemplateInstantiator::TransformLoopUnrollHintAttr(
@@ -1836,11 +1836,11 @@ const LoopUnrollHintAttr *TemplateInstantiator::TransformLoopUnrollHintAttr(
   return getSema().BuildLoopUnrollHintAttr(*LU, TransformedExpr);
 }
 
-const SYCLIntelFPGAMaxReinvocationDelayAttr *
-TemplateInstantiator::TransformSYCLIntelFPGAMaxReinvocationDelayAttr(
-    const SYCLIntelFPGAMaxReinvocationDelayAttr *MRD) {
+const SYCLIntelMaxReinvocationDelayAttr *
+TemplateInstantiator::TransformSYCLIntelMaxReinvocationDelayAttr(
+    const SYCLIntelMaxReinvocationDelayAttr *MRD) {
   Expr *TransformedExpr = getDerived().TransformExpr(MRD->getNExpr()).get();
-  return getSema().BuildSYCLIntelFPGAMaxReinvocationDelayAttr(*MRD,
+  return getSema().BuildSYCLIntelMaxReinvocationDelayAttr(*MRD,
                                                               TransformedExpr);
 }
 
diff --git a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
index 0436e9bb8b341..ce2aa49d2214a 100644
--- a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
+++ b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
@@ -597,39 +597,39 @@ static void instantiateDependentAMDGPUWavesPerEUAttr(
   S.addAMDGPUWavesPerEUAttr(New, Attr, MinExpr, MaxExpr);
 }
 
-static void instantiateIntelFPGAForcePow2DepthAttr(
+static void instantiateSYCLIntelForcePow2DepthAttr(
     Sema &S, const MultiLevelTemplateArgumentList &TemplateArgs,
-    const IntelFPGAForcePow2DepthAttr *Attr, Decl *New) {
+    const SYCLIntelForcePow2DepthAttr *Attr, Decl *New) {
   EnterExpressionEvaluationContext Unevaluated(
       S, Sema::ExpressionEvaluationContext::ConstantEvaluated);
   ExprResult Result = S.SubstExpr(Attr->getValue(), TemplateArgs);
   if (!Result.isInvalid())
-    return S.AddIntelFPGAForcePow2DepthAttr(New, *Attr, Result.getAs<Expr>());
+    return S.AddSYCLIntelForcePow2DepthAttr(New, *Attr, Result.getAs<Expr>());
 }
 
-static void instantiateIntelFPGABankWidthAttr(
+static void instantiateSYCLIntelBankWidthAttr(
     Sema &S, const MultiLevelTemplateArgumentList &TemplateArgs,
-    const IntelFPGABankWidthAttr *Attr, Decl *New) {
+    const SYCLIntelBankWidthAttr *Attr, Decl *New) {
   EnterExpressionEvaluationContext Unevaluated(
       S, Sema::ExpressionEvaluationContext::ConstantEvaluated);
   ExprResult Result = S.SubstExpr(Attr->getValue(), TemplateArgs);
   if (!Result.isInvalid())
-    S.AddIntelFPGABankWidthAttr(New, *Attr, Result.getAs<Expr>());
+    S.AddSYCLIntelBankWidthAttr(New, *Attr, Result.getAs<Expr>());
 }
 
-static void instantiateIntelFPGANumBanksAttr(
+static void instantiateSYCLIntelNumBanksAttr(
     Sema &S, const MultiLevelTemplateArgumentList &TemplateArgs,
-    const IntelFPGANumBanksAttr *Attr, Decl *New) {
+    const SYCLIntelNumBanksAttr *Attr, Decl *New) {
   EnterExpressionEvaluationContext Unevaluated(
       S, Sema::ExpressionEvaluationContext::ConstantEvaluated);
   ExprResult Result = S.SubstExpr(Attr->getValue(), TemplateArgs);
   if (!Result.isInvalid())
-    S.AddIntelFPGANumBanksAttr(New, *Attr, Result.getAs<Expr>());
+    S.AddSYCLIntelNumBanksAttr(New, *Attr, Result.getAs<Expr>());
 }
 
-static void instantiateIntelFPGABankBitsAttr(
+static void instantiateSYCLIntelBankBitsAttr(
     Sema &S, const MultiLevelTemplateArgumentList &TemplateArgs,
-    const IntelFPGABankBitsAttr *Attr, Decl *New) {
+    const SYCLIntelBankBitsAttr *Attr, Decl *New) {
   EnterExpressionEvaluationContext Unevaluated(
       S, Sema::ExpressionEvaluationContext::ConstantEvaluated);
   SmallVector<Expr *, 8> Args;
@@ -639,7 +639,7 @@ static void instantiateIntelFPGABankBitsAttr(
       return;
     Args.push_back(Result.getAs<Expr>());
   }
-  S.AddIntelFPGABankBitsAttr(New, *Attr, Args.data(), Args.size());
+  S.AddSYCLIntelBankBitsAttr(New, *Attr, Args.data(), Args.size());
 }
 
 static void
@@ -744,44 +744,44 @@ static void instantiateSYCLIntelMaxGlobalWorkDimAttr(
     S.AddSYCLIntelMaxGlobalWorkDimAttr(New, *A, Result.getAs<Expr>());
 }
 
-static void instantiateSYCLIntelFPGAMaxConcurrencyAttr(
+static void instantiateSYCLIntelMaxConcurrencyAttr(
     Sema &S, const MultiLevelTemplateArgumentList &TemplateArgs,
-    const SYCLIntelFPGAMaxConcurrencyAttr *A, Decl *New) {
+    const SYCLIntelMaxConcurrencyAttr *A, Decl *New) {
   EnterExpressionEvaluationContext Unevaluated(
       S, Sema::ExpressionEvaluationContext::ConstantEvaluated);
   ExprResult Result = S.SubstExpr(A->getNThreadsExpr(), TemplateArgs);
   if (!Result.isInvalid())
-    S.AddSYCLIntelFPGAMaxConcurrencyAttr(New, *A, Result.getAs<Expr>());
+    S.AddSYCLIntelMaxConcurrencyAttr(New, *A, Result.getAs<Expr>());
 }
 
-static void instantiateIntelFPGAPrivateCopiesAttr(
+static void instantiateSYCLIntelPrivateCopiesAttr(
     Sema &S, const MultiLevelTemplateArgumentList &TemplateArgs,
-    const IntelFPGAPrivateCopiesAttr *A, Decl *New) {
+    const SYCLIntelPrivateCopiesAttr *A, Decl *New) {
   EnterExpressionEvaluationContext Unevaluated(
       S, Sema::ExpressionEvaluationContext::ConstantEvaluated);
   ExprResult Result = S.SubstExpr(A->getValue(), TemplateArgs);
   if (!Result.isInvalid())
-    S.AddIntelFPGAPrivateCopiesAttr(New, *A, Result.getAs<Expr>());
+    S.AddSYCLIntelPrivateCopiesAttr(New, *A, Result.getAs<Expr>());
 }
 
-static void instantiateIntelFPGAMaxReplicatesAttr(
+static void instantiateSYCLIntelMaxReplicatesAttr(
     Sema &S, const MultiLevelTemplateArgumentList &TemplateArgs,
-    const IntelFPGAMaxReplicatesAttr *A, Decl *New) {
+    const SYCLIntelMaxReplicatesAttr *A, Decl *New) {
   EnterExpressionEvaluationContext Unevaluated(
       S, Sema::ExpressionEvaluationContext::ConstantEvaluated);
   ExprResult Result = S.SubstExpr(A->getValue(), TemplateArgs);
   if (!Result.isInvalid())
-    S.AddIntelFPGAMaxReplicatesAttr(New, *A, Result.getAs<Expr>());
+    S.AddSYCLIntelMaxReplicatesAttr(New, *A, Result.getAs<Expr>());
 }
 
-static void instantiateSYCLIntelFPGAInitiationIntervalAttr(
+static void instantiateSYCLIntelInitiationIntervalAttr(
     Sema &S, const MultiLevelTemplateArgumentList &TemplateArgs,
-    const SYCLIntelFPGAInitiationIntervalAttr *A, Decl *New) {
+    const SYCLIntelInitiationIntervalAttr *A, Decl *New) {
   EnterExpressionEvaluationContext Unevaluated(
       S, Sema::ExpressionEvaluationContext::ConstantEvaluated);
   ExprResult Result = S.SubstExpr(A->getIntervalExpr(), TemplateArgs);
   if (!Result.isInvalid())
-    S.AddSYCLIntelFPGAInitiationIntervalAttr(New, *A, Result.getAs<Expr>());
+    S.AddSYCLIntelInitiationIntervalAttr(New, *A, Result.getAs<Expr>());
 }
 
 static void instantiateSYCLIntelESimdVectorizeAttr(
@@ -1076,36 +1076,36 @@ void Sema::InstantiateAttrs(const MultiLevelTemplateArgumentList &TemplateArgs,
                                                *AMDGPUFlatWorkGroupSize, New);
     }
 
-    if (const auto *IntelFPGABankWidth =
-            dyn_cast<IntelFPGABankWidthAttr>(TmplAttr)) {
-      instantiateIntelFPGABankWidthAttr(*this, TemplateArgs, IntelFPGABankWidth,
+    if (const auto *SYCLIntelBankWidth =
+            dyn_cast<SYCLIntelBankWidthAttr>(TmplAttr)) {
+      instantiateSYCLIntelBankWidthAttr(*this, TemplateArgs, SYCLIntelBankWidth,
                                         New);
     }
 
-    if (const auto *IntelFPGANumBanks =
-            dyn_cast<IntelFPGANumBanksAttr>(TmplAttr)) {
-      instantiateIntelFPGANumBanksAttr(*this, TemplateArgs, IntelFPGANumBanks,
+    if (const auto *SYCLIntelNumBanks =
+            dyn_cast<SYCLIntelNumBanksAttr>(TmplAttr)) {
+      instantiateSYCLIntelNumBanksAttr(*this, TemplateArgs, SYCLIntelNumBanks,
                                        New);
     }
-    if (const auto *IntelFPGAPrivateCopies =
-            dyn_cast<IntelFPGAPrivateCopiesAttr>(TmplAttr)) {
-      instantiateIntelFPGAPrivateCopiesAttr(*this, TemplateArgs,
-                                            IntelFPGAPrivateCopies, New);
+    if (const auto *SYCLIntelPrivateCopies =
+            dyn_cast<SYCLIntelPrivateCopiesAttr>(TmplAttr)) {
+      instantiateSYCLIntelPrivateCopiesAttr(*this, TemplateArgs,
+                                            SYCLIntelPrivateCopies, New);
     }
-    if (const auto *IntelFPGAMaxReplicates =
-            dyn_cast<IntelFPGAMaxReplicatesAttr>(TmplAttr)) {
-      instantiateIntelFPGAMaxReplicatesAttr(*this, TemplateArgs,
-                                            IntelFPGAMaxReplicates, New);
+    if (const auto *SYCLIntelMaxReplicates =
+            dyn_cast<SYCLIntelMaxReplicatesAttr>(TmplAttr)) {
+      instantiateSYCLIntelMaxReplicatesAttr(*this, TemplateArgs,
+                                            SYCLIntelMaxReplicates, New);
     }
-    if (const auto *IntelFPGABankBits =
-            dyn_cast<IntelFPGABankBitsAttr>(TmplAttr)) {
-      instantiateIntelFPGABankBitsAttr(*this, TemplateArgs, IntelFPGABankBits,
+    if (const auto *SYCLIntelBankBits =
+            dyn_cast<SYCLIntelBankBitsAttr>(TmplAttr)) {
+      instantiateSYCLIntelBankBitsAttr(*this, TemplateArgs, SYCLIntelBankBits,
                                        New);
     }
-    if (const auto *IntelFPGAForcePow2Depth =
-            dyn_cast<IntelFPGAForcePow2DepthAttr>(TmplAttr)) {
-      instantiateIntelFPGAForcePow2DepthAttr(*this, TemplateArgs,
-                                             IntelFPGAForcePow2Depth, New);
+    if (const auto *SYCLIntelForcePow2Depth =
+            dyn_cast<SYCLIntelForcePow2DepthAttr>(TmplAttr)) {
+      instantiateSYCLIntelForcePow2DepthAttr(*this, TemplateArgs,
+                                             SYCLIntelForcePow2Depth, New);
     }
     if (const auto *SYCLIntelPipeIO = dyn_cast<SYCLIntelPipeIOAttr>(TmplAttr)) {
       instantiateSYCLIntelPipeIOAttr(*this, TemplateArgs, SYCLIntelPipeIO, New);
@@ -1160,14 +1160,14 @@ void Sema::InstantiateAttrs(const MultiLevelTemplateArgumentList &TemplateArgs,
       continue;
     }
     if (const auto *SYCLIntelMaxConcurrency =
-            dyn_cast<SYCLIntelFPGAMaxConcurrencyAttr>(TmplAttr)) {
-      instantiateSYCLIntelFPGAMaxConcurrencyAttr(*this, TemplateArgs,
+            dyn_cast<SYCLIntelMaxConcurrencyAttr>(TmplAttr)) {
+      instantiateSYCLIntelMaxConcurrencyAttr(*this, TemplateArgs,
                                                  SYCLIntelMaxConcurrency, New);
     }
-    if (const auto *SYCLIntelFPGAInitiationInterval =
-            dyn_cast<SYCLIntelFPGAInitiationIntervalAttr>(TmplAttr)) {
-      instantiateSYCLIntelFPGAInitiationIntervalAttr(
-          *this, TemplateArgs, SYCLIntelFPGAInitiationInterval, New);
+    if (const auto *SYCLIntelInitiationInterval =
+            dyn_cast<SYCLIntelInitiationIntervalAttr>(TmplAttr)) {
+      instantiateSYCLIntelInitiationIntervalAttr(
+          *this, TemplateArgs, SYCLIntelInitiationInterval, New);
       continue;
     }
     if (const auto *SYCLIntelESimdVectorize =
diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index 3be3cc42acd40..9cbff31857593 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -6825,8 +6825,8 @@ static void HandleAddressSpaceTypeAttribute(QualType &Type,
   }
 }
 
-static void HandleSYCLFPGAPipeAttribute(QualType &Type, const ParsedAttr &Attr,
-                                        TypeProcessingState &State) {
+static void HandleSYCLPipeAttribute(QualType &Type, const ParsedAttr &Attr,
+                                    TypeProcessingState &State) {
   Sema &S = State.getSema();
   ASTContext &Ctx = S.Context;
 
@@ -6866,7 +6866,7 @@ static void HandleSYCLFPGAPipeAttribute(QualType &Type, const ParsedAttr &Attr,
     return;
   }
 
-  auto *PipeAttr = ::new (Ctx) SYCLFPGAPipeAttr(Ctx, Attr, Str);
+  auto *PipeAttr = ::new (Ctx) SYCLIntelPipeAttr(Ctx, Attr, Str);
 
   // Apply pipe qualifiers just to the equivalent type, as the expression is not
   // value dependent (not templated).
@@ -8528,8 +8528,8 @@ static void processTypeAttrs(TypeProcessingState &state, QualType &type,
       HandleOpenCLAccessAttr(type, attr, state.getSema());
       attr.setUsedAsTypeAttr();
       break;
-    case ParsedAttr::AT_SYCLFPGAPipe:
-      HandleSYCLFPGAPipeAttribute(type, attr, state);
+    case ParsedAttr::AT_SYCLIntelPipe:
+      HandleSYCLPipeAttribute(type, attr, state);
       attr.setUsedAsTypeAttr();
       break;
     case ParsedAttr::AT_LifetimeBound:
diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
index 2e5c70ea57346..c7c7b35be77f5 100644
--- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test
+++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
@@ -170,11 +170,11 @@
 // CHECK-NEXT: SYCLDeviceHas (SubjectMatchRule_function)
 // CHECK-NEXT: SYCLDeviceIndirectlyCallable (SubjectMatchRule_function)
 // CHECK-NEXT: SYCLGlobalVariableAllowed (SubjectMatchRule_record)
-// CHECK-NEXT: SYCLIntelFPGADisableLoopPipelining (SubjectMatchRule_function)
-// CHECK-NEXT: SYCLIntelFPGAInitiationInterval (SubjectMatchRule_function)
-// CHECK-NEXT: SYCLIntelFPGAMaxConcurrency (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelDisableLoopPipelining (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelInitiationInterval (SubjectMatchRule_function)
 // CHECK-NEXT: SYCLIntelKernelArgsRestrict (SubjectMatchRule_function)
 // CHECK-NEXT: SYCLIntelLoopFuse (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelMaxConcurrency (SubjectMatchRule_function)
 // CHECK-NEXT: SYCLIntelMaxGlobalWorkDim (SubjectMatchRule_function)
 // CHECK-NEXT: SYCLIntelMaxWorkGroupSize (SubjectMatchRule_function)
 // CHECK-NEXT: SYCLIntelNoGlobalWorkOffset (SubjectMatchRule_function)
diff --git a/clang/test/SemaSYCL/disable_loop_pipelining.cpp b/clang/test/SemaSYCL/disable_loop_pipelining.cpp
index c36f0f6d29cdb..9591e1e6580d0 100644
--- a/clang/test/SemaSYCL/disable_loop_pipelining.cpp
+++ b/clang/test/SemaSYCL/disable_loop_pipelining.cpp
@@ -19,12 +19,12 @@ struct FuncObj {
 int main() {
   deviceQueue.submit([&](sycl::handler &h) {
     // CHECK-LABEL: FunctionDecl {{.*}}test_kernel1
-    // CHECK:       SYCLIntelFPGADisableLoopPipeliningAttr {{.*}}
+    // CHECK:       SYCLIntelDisableLoopPipeliningAttr {{.*}}
     h.single_task<class test_kernel1>(
         FuncObj());
 
     // CHECK-LABEL: FunctionDecl {{.*}}test_kernel2
-    // CHECK:       SYCLIntelFPGADisableLoopPipeliningAttr {{.*}}
+    // CHECK:       SYCLIntelDisableLoopPipeliningAttr {{.*}}
     h.single_task<class test_kernel2>(
         []() [[intel::disable_loop_pipelining]]{});
   });
diff --git a/clang/test/SemaSYCL/initiation_interval_ast.cpp b/clang/test/SemaSYCL/initiation_interval_ast.cpp
index 0fde5999d1d29..9d2b21f4c4c09 100644
--- a/clang/test/SemaSYCL/initiation_interval_ast.cpp
+++ b/clang/test/SemaSYCL/initiation_interval_ast.cpp
@@ -7,7 +7,7 @@ sycl::queue deviceQueue;
 
 // CHECK: FunctionDecl {{.*}} func1 'void ()'
 // CHECK-NEXT: CompoundStmt
-// CHECK-NEXT: SYCLIntelFPGAInitiationIntervalAttr {{.*}} initiation_interval
+// CHECK-NEXT: SYCLIntelInitiationIntervalAttr {{.*}} initiation_interval
 // CHECK-NEXT: ConstantExpr{{.*}}'int'
 // CHECK-NEXT: value: Int 4
 // CHECK-NEXT: IntegerLiteral {{.*}} 'int' 4
@@ -17,12 +17,12 @@ sycl::queue deviceQueue;
 // CHECK: FunctionTemplateDecl {{.*}} func2
 // CHECK: FunctionDecl {{.*}} func2 'void ()'
 // CHECK-NEXT: CompoundStmt
-// CHECK-NEXT: SYCLIntelFPGAInitiationIntervalAttr {{.*}} initiation_interval
+// CHECK-NEXT: SYCLIntelInitiationIntervalAttr {{.*}} initiation_interval
 // CHECK-NEXT: DeclRefExpr {{.*}} 'int' NonTypeTemplateParm {{.*}} 'N' 'int'
 // CHECK: FunctionDecl {{.*}} func2 'void ()'
 // CHECK-NEXT: TemplateArgument integral 6
 // CHECK-NEXT: CompoundStmt
-// CHECK-NEXT: SYCLIntelFPGAInitiationIntervalAttr {{.*}} initiation_interval
+// CHECK-NEXT: SYCLIntelInitiationIntervalAttr {{.*}} initiation_interval
 // CHECK-NEXT: ConstantExpr{{.*}}'int'
 // CHECK-NEXT: value: Int 6
 // CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -33,7 +33,7 @@ template <int N>
 
 // No diagnostic is emitted because the arguments match. Duplicate attribute is silently ignored.
 // CHECK: FunctionDecl {{.*}} {{.*}} func3 'void ()'
-// CHECK: SYCLIntelFPGAInitiationIntervalAttr {{.*}} initiation_interval
+// CHECK: SYCLIntelInitiationIntervalAttr {{.*}} initiation_interval
 // CHECK-NEXT: ConstantExpr {{.*}} 'int'
 // CHECK-NEXT: value: Int 10
 // CHECK-NEXT: IntegerLiteral{{.*}}10{{$}}
@@ -58,12 +58,12 @@ class KernelFunctor2 {
 int main() {
   deviceQueue.submit([&](sycl::handler &h) {
     // CHECK-LABEL: FunctionDecl {{.*}}kernel_name_1
-    // CHECK-NOT: SYCLIntelFPGAInitiationIntervalAttr
+    // CHECK-NOT: SYCLIntelInitiationIntervalAttr
     KernelFunctor f1;
     h.single_task<class kernel_name_1>(f1);
 
     // CHECK-LABEL: FunctionDecl {{.*}}kernel_name_2
-    // CHECK: SYCLIntelFPGAInitiationIntervalAttr {{.*}} initiation_interval
+    // CHECK: SYCLIntelInitiationIntervalAttr {{.*}} initiation_interval
     // CHECK-NEXT: ConstantExpr{{.*}}'int'
     // CHECK-NEXT: value: Int 3
     // CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -73,7 +73,7 @@ int main() {
     h.single_task<class kernel_name_2>(f2);
     
     // CHECK-LABEL: FunctionDecl {{.*}}kernel_name_3
-    // CHECK: SYCLIntelFPGAInitiationIntervalAttr {{.*}} initiation_interval
+    // CHECK: SYCLIntelInitiationIntervalAttr {{.*}} initiation_interval
     // CHECK-NEXT: ConstantExpr{{.*}}'int'
     // CHECK-NEXT: value: Int 4
     // CHECK-NEXT: IntegerLiteral {{.*}} 'int' 4
@@ -83,7 +83,7 @@ int main() {
     // Ignore duplicate attribute.
     h.single_task<class kernel_name_4>(
     // CHECK-LABEL: FunctionDecl {{.*}}kernel_name_4
-    // CHECK: SYCLIntelFPGAInitiationIntervalAttr {{.*}} initiation_interval
+    // CHECK: SYCLIntelInitiationIntervalAttr {{.*}} initiation_interval
     // CHECK-NEXT: ConstantExpr {{.*}} 'int'
     // CHECK-NEXT: value: Int 6
     // CHECK-NEXT: IntegerLiteral{{.*}}6{{$}}
diff --git a/clang/test/SemaSYCL/intel-fpga-global-const.cpp b/clang/test/SemaSYCL/intel-fpga-global-const.cpp
index 2d92bd1ae18a1..3484d680d8b1f 100644
--- a/clang/test/SemaSYCL/intel-fpga-global-const.cpp
+++ b/clang/test/SemaSYCL/intel-fpga-global-const.cpp
@@ -1,16 +1,16 @@
 // RUN: %clang_cc1 -fsycl-is-device -fsyntax-only -ast-dump -verify -pedantic %s | FileCheck %s
 
 // Test that checks global constant variable (which allows the redeclaration) since
-// IntelFPGAConstVar is one of the subjects listed for [[intel::max_replicates()]] attribute.
+// SYCLIntelConstVar is one of the subjects listed for [[intel::max_replicates()]] attribute.
 
 // Check duplicate argument values with implicit memory attribute.
 //CHECK: VarDecl{{.*}}var_max_replicates
-//CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-//CHECK: IntelFPGAMaxReplicatesAttr
+//CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+//CHECK: SYCLIntelMaxReplicatesAttr
 //CHECK-NEXT: ConstantExpr
 //CHECK-NEXT: value:{{.*}}12
 //CHECK-NEXT: IntegerLiteral{{.*}}12{{$}}
-//CHECK: IntelFPGAMaxReplicatesAttr
+//CHECK: SYCLIntelMaxReplicatesAttr
 //CHECK-NEXT: ConstantExpr
 //CHECK-NEXT: value:{{.*}}12
 //CHECK-NEXT: IntegerLiteral{{.*}}12{{$}}
@@ -34,12 +34,12 @@
 
 // Checking of duplicate argument values.
 //CHECK: VarDecl{{.*}}force_pow2_depth
-//CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-//CHECK: IntelFPGAForcePow2DepthAttr
+//CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+//CHECK: SYCLIntelForcePow2DepthAttr
 //CHECK-NEXT: ConstantExpr
 //CHECK-NEXT: value:{{.*}}1
 //CHECK-NEXT: IntegerLiteral{{.*}}1{{$}}
-//CHECK: IntelFPGAForcePow2DepthAttr
+//CHECK: SYCLIntelForcePow2DepthAttr
 //CHECK-NEXT: ConstantExpr
 //CHECK-NEXT: value:{{.*}}1
 //CHECK-NEXT: IntegerLiteral{{.*}}1{{$}}
@@ -63,12 +63,12 @@
 
 // Checking of duplicate argument values.
 //CHECK: VarDecl{{.*}}numbanks
-//CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-//CHECK: IntelFPGANumBanksAttr
+//CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+//CHECK: SYCLIntelNumBanksAttr
 //CHECK-NEXT: ConstantExpr{{.*}}'int'
 //CHECK-NEXT: value: Int 16
 //CHECK-NEXT: IntegerLiteral{{.*}}'int' 16
-//CHECK: IntelFPGANumBanksAttr
+//CHECK: SYCLIntelNumBanksAttr
 //CHECK-NEXT: ConstantExpr{{.*}}'int'
 //CHECK-NEXT: value: Int 16
 //CHECK-NEXT: IntegerLiteral{{.*}}'int' 16
@@ -92,12 +92,12 @@
 
 // Checking of duplicate argument values.
 //CHECK: VarDecl{{.*}}bankwidth
-//CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-//CHECK: IntelFPGABankWidthAttr
+//CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+//CHECK: SYCLIntelBankWidthAttr
 //CHECK-NEXT: ConstantExpr{{.*}}'int'
 //CHECK-NEXT: value: Int 8
 //CHECK-NEXT: IntegerLiteral{{.*}}'int' 8
-//CHECK: IntelFPGABankWidthAttr
+//CHECK: SYCLIntelBankWidthAttr
 //CHECK-NEXT: ConstantExpr{{.*}}'int'
 //CHECK-NEXT: value: Int 8
 //CHECK-NEXT: IntegerLiteral{{.*}}'int' 8
diff --git a/clang/test/SemaSYCL/intel-fpga-local.cpp b/clang/test/SemaSYCL/intel-fpga-local.cpp
index 757cf575ebb27..a62ed6d91ddf5 100644
--- a/clang/test/SemaSYCL/intel-fpga-local.cpp
+++ b/clang/test/SemaSYCL/intel-fpga-local.cpp
@@ -8,70 +8,70 @@ sycl::queue deviceQueue;
 void check_ast()
 {
   //CHECK: VarDecl{{.*}}doublepump
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGADoublePumpAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelDoublePumpAttr
   [[intel::doublepump]] unsigned int doublepump[64];
 
   //CHECK: VarDecl{{.*}}memory
-  //CHECK: IntelFPGAMemoryAttr
+  //CHECK: SYCLIntelMemoryAttr
   [[intel::fpga_memory]] unsigned int memory[64];
 
   //CHECK: VarDecl{{.*}}memory_mlab
-  //CHECK: IntelFPGAMemoryAttr{{.*}}MLAB
+  //CHECK: SYCLIntelMemoryAttr{{.*}}MLAB
   [[intel::fpga_memory("MLAB")]] unsigned int memory_mlab[64];
 
   //CHECK: VarDecl{{.*}}mem_blockram
-  //CHECK: IntelFPGAMemoryAttr{{.*}}BlockRAM
+  //CHECK: SYCLIntelMemoryAttr{{.*}}BlockRAM
   [[intel::fpga_memory("BLOCK_RAM")]] unsigned int mem_blockram[32];
 
   //CHECK: VarDecl{{.*}}reg
-  //CHECK: IntelFPGARegisterAttr
+  //CHECK: SYCLIntelRegisterAttr
   [[intel::fpga_register]] unsigned int reg[64];
 
   //CHECK: VarDecl{{.*}}singlepump
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGASinglePumpAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelSinglePumpAttr
   [[intel::singlepump]] unsigned int singlepump[64];
 
   //CHECK: VarDecl{{.*}}bankwidth
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGABankWidthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelBankWidthAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}4
   //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}}
   [[intel::bankwidth(4)]] unsigned int bankwidth[32];
 
   //CHECK: VarDecl{{.*}}numbanks
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGANumBanksAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelNumBanksAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}8
   //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}}
   [[intel::numbanks(8)]] unsigned int numbanks[32];
 
   //CHECK: VarDecl{{.*}}private_copies
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAPrivateCopiesAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelPrivateCopiesAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}8
   //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}}
   [[intel::private_copies(8)]] unsigned int private_copies[64];
 
   //CHECK: VarDecl{{.*}}merge_depth
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAMergeAttr{{.*}}"mrg1" "depth"{{$}}
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelMergeAttr{{.*}}"mrg1" "depth"{{$}}
   [[intel::merge("mrg1", "depth")]] unsigned int merge_depth[64];
 
   //CHECK: VarDecl{{.*}}merge_width
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAMergeAttr{{.*}}"mrg2" "width"{{$}}
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelMergeAttr{{.*}}"mrg2" "width"{{$}}
   [[intel::merge("mrg2", "width")]] unsigned int merge_width[64];
 
   //CHECK: VarDecl{{.*}}bankbits
-  //CHECK: IntelFPGANumBanksAttr{{.*}}Implicit{{$}}
+  //CHECK: SYCLIntelNumBanksAttr{{.*}}Implicit{{$}}
   //CHECK-NEXT: IntegerLiteral{{.*}}16{{$}}
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGABankBitsAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelBankBitsAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}2
   //CHECK-NEXT: IntegerLiteral{{.*}}2{{$}}
@@ -87,53 +87,53 @@ void check_ast()
   [[intel::bank_bits(2, 3, 4, 5)]] unsigned int bankbits[64];
 
   //CHECK: VarDecl{{.*}}bank_bits_width
-  //CHECK-NEXT: IntelFPGANumBanksAttr{{.*}}Implicit{{$}}
+  //CHECK-NEXT: SYCLIntelNumBanksAttr{{.*}}Implicit{{$}}
   //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}}
-  //CHECK-NEXT: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK-NEXT: IntelFPGABankBitsAttr
+  //CHECK-NEXT: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK-NEXT: SYCLIntelBankBitsAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}2
   //CHECK-NEXT: IntegerLiteral{{.*}}2{{$}}
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}3
   //CHECK-NEXT: IntegerLiteral{{.*}}3{{$}}
-  //CHECK-NEXT: IntelFPGABankWidthAttr
+  //CHECK-NEXT: SYCLIntelBankWidthAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}16
   //CHECK-NEXT: IntegerLiteral{{.*}}16{{$}}
   [[intel::bank_bits(2, 3), intel::bankwidth(16)]] unsigned int bank_bits_width[64];
 
   //CHECK: VarDecl{{.*}}doublepump_mlab
-  //CHECK: IntelFPGADoublePumpAttr
-  //CHECK: IntelFPGAMemoryAttr{{.*}}MLAB{{$}}
+  //CHECK: SYCLIntelDoublePumpAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}MLAB{{$}}
   [[intel::doublepump]]
   [[intel::fpga_memory("MLAB")]] unsigned int doublepump_mlab[64];
 
   // Add implicit memory attribute.
   //CHECK: VarDecl{{.*}}max_replicates
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAMaxReplicatesAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelMaxReplicatesAttr
   //CHECK: ConstantExpr
   //CHECK-NEXT: value:{{.*}}2
   //CHECK: IntegerLiteral{{.*}}2{{$}}
   [[intel::max_replicates(2)]] unsigned int max_replicates[64];
 
   //CHECK: VarDecl{{.*}}dual_port
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGASimpleDualPortAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelSimpleDualPortAttr
   [[intel::simple_dual_port]] unsigned int dual_port[64];
 
   //CHECK: VarDecl{{.*}}arr_force_p2d_0
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAForcePow2DepthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelForcePow2DepthAttr
   //CHECK: ConstantExpr
   //CHECK-NEXT: value:{{.*}}0
   //CHECK: IntegerLiteral{{.*}}0{{$}}
   [[intel::force_pow2_depth(0)]] unsigned int arr_force_p2d_0[64];
 
   //CHECK: VarDecl{{.*}}arr_force_p2d_1
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAForcePow2DepthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelForcePow2DepthAttr
   //CHECK: ConstantExpr
   //CHECK-NEXT: value:{{.*}}1
   //CHECK: IntegerLiteral{{.*}}1{{$}}
@@ -150,8 +150,8 @@ void check_ast()
 
   // Check duplicate argument values with implicit memory attribute.
   //CHECK: VarDecl{{.*}}var_max_replicates
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAMaxReplicatesAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelMaxReplicatesAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}12
   //CHECK-NEXT: IntegerLiteral{{.*}}12{{$}}
@@ -160,8 +160,8 @@ void check_ast()
 
   // Check duplicate argument values.
   //CHECK: VarDecl{{.*}}var_private_copies
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAPrivateCopiesAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelPrivateCopiesAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}12
   //CHECK-NEXT: IntegerLiteral{{.*}}12{{$}}
@@ -170,8 +170,8 @@ void check_ast()
 
   // Checking of duplicate argument values.
   //CHECK: VarDecl{{.*}}var_forcep2d
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAForcePow2DepthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelForcePow2DepthAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}1
   //CHECK-NEXT: IntegerLiteral{{.*}}1{{$}}
@@ -182,8 +182,8 @@ void check_ast()
   // No diagnostic is emitted because the arguments match.
   // Duplicate attribute is silently ignored.
   //CHECK: VarDecl{{.*}}var_bankwidth 'int'
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit Default
-  //CHECK: IntelFPGABankWidthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit Default
+  //CHECK: SYCLIntelBankWidthAttr
   //CHECK-NEXT: ConstantExpr{{.*}}'int'
   //CHECK-NEXT: value: Int 16
   //CHECK-NEXT: IntegerLiteral{{.*}}'int' 16
@@ -194,8 +194,8 @@ void check_ast()
   // No diagnostic is emitted because the arguments match.
   // Duplicate attribute is silently ignored.
   //CHECK: VarDecl{{.*}}var_numbanks 'int'
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit Default
-  //CHECK: IntelFPGANumBanksAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit Default
+  //CHECK: SYCLIntelNumBanksAttr
   //CHECK-NEXT: ConstantExpr{{.*}}'int'
   //CHECK-NEXT: value: Int 8
   //CHECK-NEXT: IntegerLiteral{{.*}}'int' 8
@@ -208,8 +208,8 @@ void diagnostics()
 {
   // **doublepump
   //CHECK: VarDecl{{.*}}doublepump
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGADoublePumpAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelDoublePumpAttr
   [[intel::doublepump]] unsigned int doublepump[64];
 
   //expected-warning@+1 {{unknown attribute 'doublepump' ignored}}
@@ -233,8 +233,8 @@ void diagnostics()
 
   // **singlepump
   //CHECK: VarDecl{{.*}}singlepump
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGASinglePumpAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelSinglePumpAttr
   [[intel::singlepump]] unsigned int singlepump[64];
 
   //expected-warning@+1 {{unknown attribute 'singlepump' ignored}}
@@ -257,7 +257,7 @@ void diagnostics()
 
   // **fpga_register
   //CHECK: VarDecl{{.*}}reg
-  //CHECK: IntelFPGARegisterAttr
+  //CHECK: SYCLIntelRegisterAttr
   [[intel::fpga_register]] unsigned int reg[64];
 
   //expected-warning@+1 {{unknown attribute 'register' ignored}}
@@ -349,7 +349,7 @@ void diagnostics()
 
   // **memory
   //CHECK: VarDecl{{.*}}memory
-  //CHECK: IntelFPGAMemoryAttr
+  //CHECK: SYCLIntelMemoryAttr
   [[intel::fpga_memory]] unsigned int memory[64];
 
   //expected-error@+2{{attributes are not compatible}}
@@ -366,8 +366,8 @@ void diagnostics()
 
   // bankwidth
   //CHECK: VarDecl{{.*}}bankwidth
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGABankWidthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelBankWidthAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}4
   //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}}
@@ -386,8 +386,8 @@ void diagnostics()
   // **max_replicates
   // Add implicit memory attribute.
   //CHECK: VarDecl{{.*}}max_replicates
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAMaxReplicatesAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelMaxReplicatesAttr
   //CHECK: ConstantExpr
   //CHECK-NEXT: value:{{.*}}2
   //CHECK: IntegerLiteral{{.*}}2{{$}}
@@ -417,8 +417,8 @@ void diagnostics()
   [[intel::simple_dual_port(0)]] unsigned int sdp[64];
 
   //CHECK: VarDecl{{.*}}dual_port
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGASimpleDualPortAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelSimpleDualPortAttr
   [[intel::simple_dual_port]] unsigned int dual_port[64];
 
   //expected-warning@+1 {{unknown attribute 'simple_dual_port' ignored}}
@@ -431,8 +431,8 @@ void diagnostics()
 
   // Checking of different argument values.
   //CHECK: VarDecl{{.*}}bw_bw 'unsigned int[64]'
-  //CHECK:IntelFPGAMemoryAttr{{.*}}Implicit Default
-  //CHECK: IntelFPGABankWidthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit Default
+  //CHECK: SYCLIntelBankWidthAttr
   //CHECK-NEXT: ConstantExpr{{.*}}'int'
   //CHECK-NEXT: value: Int 8
   //CHECK-NEXT: IntegerLiteral{{.*}}'int' 8
@@ -460,8 +460,8 @@ void diagnostics()
 
   // private_copies_
   //CHECK: VarDecl{{.*}}private_copies
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAPrivateCopiesAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelPrivateCopiesAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}8
   //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}}
@@ -496,8 +496,8 @@ void diagnostics()
 
   // numbanks
   //CHECK: VarDecl{{.*}}numbanks
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGANumBanksAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelNumBanksAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}8
   //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}}
@@ -510,8 +510,8 @@ void diagnostics()
   unsigned int nb_reg[64];
 
   //CHECK: VarDecl{{.*}}nb_nb 'unsigned int[64]'
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit Default
-  //CHECK:IntelFPGANumBanksAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit Default
+  //CHECK: SYCLIntelNumBanksAttr
   //CHECK-NEXT: ConstantExpr{{.*}}'int'
   //CHECK-NEXT: value: Int 8
   //CHECK-NEXT: IntegerLiteral{{.*}}'int' 8
@@ -542,8 +542,8 @@ void diagnostics()
 
   // merge
   //CHECK: VarDecl{{.*}}merge_depth
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAMergeAttr{{.*}}"mrg1" "depth"{{$}}
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelMergeAttr{{.*}}"mrg1" "depth"{{$}}
   [[intel::merge("mrg1", "depth")]] unsigned int merge_depth[64];
 
   //expected-warning@+1 {{unknown attribute 'merge' ignored}}
@@ -569,18 +569,18 @@ void diagnostics()
 
   //Last one is applied and others ignored.
   //CHECK: VarDecl{{.*}}mrg_mrg
-  //CHECK: IntelFPGAMergeAttr{{.*}}"mrg4" "depth"{{$}}
-  //CHECK: IntelFPGAMergeAttr{{.*}}"mrg5" "width"{{$}}
+  //CHECK: SYCLIntelMergeAttr{{.*}}"mrg4" "depth"{{$}}
+  //CHECK: SYCLIntelMergeAttr{{.*}}"mrg5" "width"{{$}}
   //expected-warning@+2{{attribute 'merge' is already applied}}
   [[intel::merge("mrg4", "depth")]]
   [[intel::merge("mrg5", "width")]] unsigned int mrg_mrg[4];
 
   // bank_bits
   //CHECK: VarDecl{{.*}}bankbits
-  //CHECK: IntelFPGANumBanksAttr{{.*}}Implicit{{$}}
+  //CHECK: SYCLIntelNumBanksAttr{{.*}}Implicit{{$}}
   //CHECK-NEXT: IntegerLiteral{{.*}}16{{$}}
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGABankBitsAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelBankBitsAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}2
   //CHECK-NEXT: IntegerLiteral{{.*}}2{{$}}
@@ -596,10 +596,10 @@ void diagnostics()
   [[intel::bank_bits(2, 3, 4, 5)]] unsigned int bankbits[64];
 
   //CHECK: VarDecl{{.*}} bb_reg 'unsigned int[4]'
-  //CHECK: IntelFPGANumBanksAttr{{.*}}Implicit
+  //CHECK: SYCLIntelNumBanksAttr{{.*}}Implicit
   //CHECK-NEXT: IntegerLiteral{{.*}}'int' 4
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit Default
-  //CHECK: IntelFPGABankBitsAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit Default
+  //CHECK: SYCLIntelBankBitsAttr
   //CHECK-NEXT: ConstantExpr{{.*}}'int'
   //CHECK-NEXT: value: Int 2
   //CHECK-NEXT: IntegerLiteral{{.*}}'int' 2
@@ -613,14 +613,14 @@ void diagnostics()
   unsigned int bb_reg[4];
 
   //CHECK: VarDecl{{.*}}bb_bb
-  //CHECK: IntelFPGABankBitsAttr
+  //CHECK: SYCLIntelBankBitsAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}42
   //CHECK-NEXT: IntegerLiteral{{.*}}42{{$}}
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}43
   //CHECK-NEXT: IntegerLiteral{{.*}}43{{$}}
-  //CHECK: IntelFPGABankBitsAttr
+  //CHECK: SYCLIntelBankBitsAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}1
   //CHECK-NEXT: IntegerLiteral{{.*}}1{{$}}
@@ -651,8 +651,8 @@ void diagnostics()
 
   // force_pow2_depth
   //CHECK: VarDecl{{.*}}arr_force_p2d_0
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAForcePow2DepthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelForcePow2DepthAttr
   //CHECK: ConstantExpr
   //CHECK-NEXT: value:{{.*}}0
   //CHECK: IntegerLiteral{{.*}}0{{$}}
@@ -673,8 +673,8 @@ void diagnostics()
 
   // Checking of different argument values.
   //CHECK: VarDecl{{.*}}force_p2d_dup
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAForcePow2DepthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelForcePow2DepthAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}1
   //CHECK-NEXT: IntegerLiteral{{.*}}1{{$}}
@@ -745,74 +745,74 @@ void force_p2d_attr_on_func_arg([[intel::force_pow2_depth(0)]] int pc) {}
 
 struct foo {
   //CHECK: FieldDecl{{.*}}doublepump
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGADoublePumpAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelDoublePumpAttr
   [[intel::doublepump]] unsigned int doublepump[64];
 
   //CHECK: FieldDecl{{.*}}memory
-  //CHECK: IntelFPGAMemoryAttr
+  //CHECK: SYCLIntelMemoryAttr
   [[intel::fpga_memory]] unsigned int memory[64];
 
   //CHECK: FieldDecl{{.*}}memory_mlab
-  //CHECK: IntelFPGAMemoryAttr{{.*}}MLAB{{$}}
+  //CHECK: SYCLIntelMemoryAttr{{.*}}MLAB{{$}}
   [[intel::fpga_memory("MLAB")]] unsigned int memory_mlab[64];
 
   //CHECK: FieldDecl{{.*}}mem_blockram
-  //CHECK: IntelFPGAMemoryAttr{{.*}}BlockRAM{{$}}
+  //CHECK: SYCLIntelMemoryAttr{{.*}}BlockRAM{{$}}
   [[intel::fpga_memory("BLOCK_RAM")]] unsigned int mem_blockram[64];
 
   //CHECK: FieldDecl{{.*}}mem_blockram_doublepump
-  //CHECK: IntelFPGAMemoryAttr{{.*}}BlockRAM{{$}}
-  //CHECK: IntelFPGADoublePumpAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}BlockRAM{{$}}
+  //CHECK: SYCLIntelDoublePumpAttr
   [[intel::fpga_memory("BLOCK_RAM")]]
   [[intel::doublepump]] unsigned int mem_blockram_doublepump[64];
 
   //CHECK: FieldDecl{{.*}}reg
-  //CHECK: IntelFPGARegisterAttr
+  //CHECK: SYCLIntelRegisterAttr
   [[intel::fpga_register]] unsigned int reg[64];
 
   //CHECK: FieldDecl{{.*}}singlepump
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGASinglePumpAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelSinglePumpAttr
   [[intel::singlepump]] unsigned int singlepump[64];
 
   //CHECK: FieldDecl{{.*}}bankwidth
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGABankWidthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelBankWidthAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}4
   //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}}
   [[intel::bankwidth(4)]] unsigned int bankwidth[64];
 
   //CHECK: FieldDecl{{.*}}numbanks
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGANumBanksAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelNumBanksAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}8
   //CHECK-NEXT: IntegerLiteral{{.*}}8{{$}}
   [[intel::numbanks(8)]] unsigned int numbanks[64];
 
   //CHECK: FieldDecl{{.*}}private_copies
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAPrivateCopiesAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelPrivateCopiesAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}4
   //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}}
   [[intel::private_copies(4)]] unsigned int private_copies[64];
 
   //CHECK: FieldDecl{{.*}}merge_depth
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAMergeAttr{{.*}}"mrg1" "depth"{{$}}
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelMergeAttr{{.*}}"mrg1" "depth"{{$}}
   [[intel::merge("mrg1", "depth")]] unsigned int merge_depth[64];
 
   //CHECK: FieldDecl{{.*}}merge_width
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAMergeAttr{{.*}}"mrg2" "width"{{$}}
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelMergeAttr{{.*}}"mrg2" "width"{{$}}
   [[intel::merge("mrg2", "width")]] unsigned int merge_width[64];
 
   //CHECK: FieldDecl{{.*}}bankbits
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGABankBitsAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelBankBitsAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}2
   //CHECK-NEXT: IntegerLiteral{{.*}}2{{$}}
@@ -822,8 +822,8 @@ struct foo {
   [[intel::bank_bits(2, 3)]] unsigned int bankbits[64];
 
   //CHECK: FieldDecl{{.*}}force_p2d_field
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAForcePow2DepthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelForcePow2DepthAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}1
   //CHECK-NEXT: IntegerLiteral{{.*}}1{{$}}
@@ -834,8 +834,8 @@ struct foo {
 template <int A, int B, int C, int D, int E>
 void check_template_parameters() {
   //CHECK: VarDecl{{.*}}numbanks
-  //CHECK-NEXT: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK-NEXT: IntelFPGANumBanksAttr
+  //CHECK-NEXT: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK-NEXT: SYCLIntelNumBanksAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}8
   //CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -844,8 +844,8 @@ void check_template_parameters() {
   [[intel::numbanks(C)]] unsigned int numbanks;
 
   //CHECK: VarDecl{{.*}}private_copies
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAPrivateCopiesAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelPrivateCopiesAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}8
   //CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -854,10 +854,10 @@ void check_template_parameters() {
   [[intel::private_copies(C)]] unsigned int private_copies;
 
   //CHECK: VarDecl{{.*}}bank_bits_width
-  //CHECK: IntelFPGANumBanksAttr{{.*}}Implicit{{$}}
+  //CHECK: SYCLIntelNumBanksAttr{{.*}}Implicit{{$}}
   //CHECK-NEXT: IntegerLiteral{{.*}}4{{$}}
-  //CHECK-NEXT: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK-NEXT: IntelFPGABankBitsAttr
+  //CHECK-NEXT: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK-NEXT: SYCLIntelBankBitsAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}2
   //CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -866,7 +866,7 @@ void check_template_parameters() {
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}3
   //CHECK-NEXT: IntegerLiteral{{.*}}3{{$}}
-  //CHECK: IntelFPGABankWidthAttr
+  //CHECK: SYCLIntelBankWidthAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}8
   //CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -876,8 +876,8 @@ void check_template_parameters() {
 
   // Add implicit memory attribute.
   //CHECK: VarDecl{{.*}}max_replicates
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAMaxReplicatesAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelMaxReplicatesAttr
   //CHECK: ConstantExpr
   //CHECK-NEXT: value:{{.*}}2
   //CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -942,8 +942,8 @@ void check_template_parameters() {
 
   // Test that checks template instantiations for different arg values.
   //CHECK: VarDecl{{.*}}force_p2d_dup
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAForcePow2DepthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelForcePow2DepthAttr
   //CHECK-NEXT: ConstantExpr
   //CHECK-NEXT: value:{{.*}}1
   //CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -957,8 +957,8 @@ void check_template_parameters() {
 template <int A>
 struct templ_st {
   //CHECK: FieldDecl{{.*}}templ_force_p2d_field
-  //CHECK: IntelFPGAMemoryAttr{{.*}}Implicit
-  //CHECK: IntelFPGAForcePow2DepthAttr
+  //CHECK: SYCLIntelMemoryAttr{{.*}}Implicit
+  //CHECK: SYCLIntelForcePow2DepthAttr
   //CHECK: ConstantExpr
   //CHECK-NEXT: value:{{.*}}0
   //CHECK-NEXT: SubstNonTypeTemplateParmExpr
diff --git a/clang/test/SemaSYCL/intel-fpga-nofusion.cpp b/clang/test/SemaSYCL/intel-fpga-nofusion.cpp
index 0ab64ee407ab5..fd64b2ac7fcac 100644
--- a/clang/test/SemaSYCL/intel-fpga-nofusion.cpp
+++ b/clang/test/SemaSYCL/intel-fpga-nofusion.cpp
@@ -10,20 +10,20 @@ void nofusion() {
   int a1[10], a2[10];
 
   // CHECK: AttributedStmt
-  // CHECK-NEXT: SYCLIntelFPGANofusionAttr {{.*}}
+  // CHECK-NEXT: SYCLIntelNofusionAttr {{.*}}
   [[intel::nofusion]] for (int p = 0; p < 10; ++p) {
     a1[p] = a2[p] = 0;
   }
 
   // CHECK: AttributedStmt
-  // CHECK-NEXT: SYCLIntelFPGANofusionAttr {{.*}}
+  // CHECK-NEXT: SYCLIntelNofusionAttr {{.*}}
   int i = 0;
   [[intel::nofusion]] while (i < 10) {
     a1[i] += 3;
   }
 
   // CHECK: AttributedStmt
-  // CHECK-NEXT: SYCLIntelFPGANofusionAttr {{.*}}
+  // CHECK-NEXT: SYCLIntelNofusionAttr {{.*}}
   for (int i = 0; i < 10; ++i) {
     [[intel::nofusion]] for (int j = 0; j < 10; ++j) {
       a1[i] += a1[j];
diff --git a/clang/test/SemaSYCL/max-concurrency-ast.cpp b/clang/test/SemaSYCL/max-concurrency-ast.cpp
index 61f9f60d6a2f0..654ce182fed67 100644
--- a/clang/test/SemaSYCL/max-concurrency-ast.cpp
+++ b/clang/test/SemaSYCL/max-concurrency-ast.cpp
@@ -8,7 +8,7 @@ queue q;
 
 // CHECK: FunctionDecl {{.*}} func1 'void ()'
 // CHECK-NEXT: CompoundStmt
-// CHECK-NEXT: SYCLIntelFPGAMaxConcurrencyAttr
+// CHECK-NEXT: SYCLIntelMaxConcurrencyAttr
 // CHECK-NEXT: ConstantExpr{{.*}}'int'
 // CHECK-NEXT: value: Int 1
 // CHECK-NEXT: IntegerLiteral {{.*}} 'int' 1
@@ -16,7 +16,7 @@ queue q;
 
 // CHECK: FunctionDecl {{.*}} func2 'void ()'
 // CHECK-NEXT: CompoundStmt
-// CHECK-NEXT: SYCLIntelFPGAMaxConcurrencyAttr
+// CHECK-NEXT: SYCLIntelMaxConcurrencyAttr
 // CHECK-NEXT: ConstantExpr{{.*}}'int'
 // CHECK-NEXT: value: Int 0
 // CHECK-NEXT: IntegerLiteral {{.*}} 'int' 0
@@ -25,12 +25,12 @@ queue q;
 // CHECK: FunctionTemplateDecl {{.*}} func3
 // CHECK: FunctionDecl {{.*}} func3 'void ()'
 // CHECK-NEXT: CompoundStmt
-// CHECK-NEXT: SYCLIntelFPGAMaxConcurrencyAttr
+// CHECK-NEXT: SYCLIntelMaxConcurrencyAttr
 // CHECK-NEXT: DeclRefExpr {{.*}} 'int' NonTypeTemplateParm {{.*}} 'N' 'int'
 // CHECK: FunctionDecl {{.*}} func3 'void ()'
 // CHECK-NEXT: TemplateArgument integral 5
 // CHECK-NEXT: CompoundStmt
-// CHECK-NEXT: SYCLIntelFPGAMaxConcurrencyAttr
+// CHECK-NEXT: SYCLIntelMaxConcurrencyAttr
 // CHECK-NEXT: ConstantExpr{{.*}}'int'
 // CHECK-NEXT: value: Int 5
 // CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -58,12 +58,12 @@ void foo() {
   q.submit([&](handler &h) {
     // Test attribute is not propagated.
     // CHECK: FunctionDecl {{.*}}kernel_name_1
-    // CHECK-NOT: SYCLIntelFPGAMaxConcurrencyAttr
+    // CHECK-NOT: SYCLIntelMaxConcurrencyAttr
     KernelFunctor f1;
     h.single_task<class kernel_name_1>(f1);
 
     // CHECK: FunctionDecl {{.*}}kernel_name_2
-    // CHECK: SYCLIntelFPGAMaxConcurrencyAttr
+    // CHECK: SYCLIntelMaxConcurrencyAttr
     // CHECK-NEXT: ConstantExpr{{.*}}'int'
     // CHECK-NEXT: value: Int 3
     // CHECK-NEXT: SubstNonTypeTemplateParmExpr
@@ -73,7 +73,7 @@ void foo() {
     h.single_task<class kernel_name_2>(f2);
 
     // CHECK: FunctionDecl {{.*}}kernel_name_3
-    // CHECK: SYCLIntelFPGAMaxConcurrencyAttr
+    // CHECK: SYCLIntelMaxConcurrencyAttr
     // CHECK-NEXT: ConstantExpr{{.*}}'int'
     // CHECK-NEXT: value: Int 4
     // CHECK-NEXT: IntegerLiteral {{.*}} 'int' 4
@@ -83,11 +83,11 @@ void foo() {
     // Ignore duplicate attribute.
     h.single_task<class kernel_name_4>(
         // CHECK: FunctionDecl {{.*}}kernel_name_4
-        // CHECK: SYCLIntelFPGAMaxConcurrencyAttr
+        // CHECK: SYCLIntelMaxConcurrencyAttr
         // CHECK-NEXT: ConstantExpr {{.*}} 'int'
         // CHECK-NEXT: value: Int 3
         // CHECK-NEXT: IntegerLiteral{{.*}}3{{$}}
-        // CHECK-NOT: SYCLIntelFPGAMaxConcurrencyAttr
+        // CHECK-NOT: SYCLIntelMaxConcurrencyAttr
         []() [[intel::max_concurrency(3),
                intel::max_concurrency(3)]] {});
   });