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Milestones

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  • No due date
    6/6 issues closed
  • Cleanup and production generation.

    Overdue by 3 year(s)
    Due by January 31, 2022
    6/14 issues closed
  • Tracking for SiFive Milestone 2. This roughly encompasses supporting a path from Hight FIRRTL IR input to Verilog output.

    Overdue by 3 year(s)
    Due by November 30, 2021
    89/99 issues closed