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hchandelHarsh Chandel
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Harsh Chandel
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[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)
This extension adds eleven instructions to accelerate interrupt servicing. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <[email protected]>
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -196,6 +196,7 @@
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// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension)
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// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-NEXT: xqciint 0.2 'Xqciint' (Qualcomm uC Interrupts Extension)
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// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
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// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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// CHECK-EMPTY:

‎llvm/docs/RISCVUsage.rst

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@@ -447,6 +447,9 @@ The current vendor extensions supported are:
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``experimental-Xqcicsr``
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LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqciint``
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LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcilsm``
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LLVM implements `version 0.2 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md

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@@ -235,6 +235,8 @@ Changes to the RISC-V Backend
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcicm` (Conditonal Move)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqciint` (Interrupts)
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extension.
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* Added ``Sdext`` and ``Sdtrig`` extensions.
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Changes to the WebAssembly Backend

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

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@@ -717,6 +717,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
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bool isUImm6() const { return IsUImm<6>(); }
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bool isUImm7() const { return IsUImm<7>(); }
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bool isUImm8() const { return IsUImm<8>(); }
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bool isUImm10() const { return IsUImm<10>(); }
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bool isUImm11() const { return IsUImm<11>(); }
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bool isUImm16() const { return IsUImm<16>(); }
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bool isUImm20() const { return IsUImm<20>(); }
@@ -1590,6 +1591,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return generateImmOutOfRangeError(
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Operands, ErrorInfo, -(1 << 9), (1 << 9) - 16,
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"immediate must be a multiple of 16 bytes and non-zero in the range");
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case Match_InvalidUImm10:
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 10) - 1);
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case Match_InvalidUImm11:
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return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 11) - 1);
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case Match_InvalidSImm12:

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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@@ -700,6 +700,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
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"Qualcomm uC Conditional Load Immediate custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicm, DecoderTableXqcicm32,
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"Qualcomm uC Conditional Move custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
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"Qualcomm uC Interrupts custom opcode table");
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TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
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return MCDisassembler::Fail;
@@ -732,6 +734,8 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
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TRY_TO_DECODE_FEATURE(
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RISCV::FeatureVendorXqcicm, DecoderTableXqcicm16,
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"Qualcomm uC Conditional Move custom 16bit opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint16,
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"Qualcomm uC Interrupts custom 16bit opcode table");
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TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXwchc),
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DecoderTableXwchc16,
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"WCH QingKe XW custom opcode table");

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

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@@ -313,6 +313,7 @@ enum OperandType : unsigned {
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OPERAND_UIMM8_LSB000,
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OPERAND_UIMM8_GE32,
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OPERAND_UIMM9_LSB000,
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OPERAND_UIMM10,
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OPERAND_UIMM10_LSB00_NONZERO,
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OPERAND_UIMM11,
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OPERAND_UIMM12,

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1302,6 +1302,14 @@ def HasVendorXqcicm
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AssemblerPredicate<(all_of FeatureVendorXqcicm),
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"'Xqcicm' (Qualcomm uC Conditional Move Extension)">;
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def FeatureVendorXqciint
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: RISCVExperimentalExtension<0, 2, "Qualcomm uC Interrupts Extension",
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[FeatureStdExtZca]>;
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def HasVendorXqciint
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: Predicate<"Subtarget->hasVendorXqciint()">,
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AssemblerPredicate<(all_of FeatureVendorXqciint),
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"'Xqciint' (Qualcomm uC Interrupts Extension)">;
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//===----------------------------------------------------------------------===//
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// LLVM specific features and extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

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@@ -2473,6 +2473,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
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CASE_OPERAND_UIMM(6)
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CASE_OPERAND_UIMM(7)
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CASE_OPERAND_UIMM(8)
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CASE_OPERAND_UIMM(10)
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CASE_OPERAND_UIMM(12)
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CASE_OPERAND_UIMM(20)
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// clang-format on

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

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@@ -28,6 +28,8 @@ def uimm5gt3 : RISCVOp<XLenVT>, ImmLeaf<XLenVT,
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let OperandType = "OPERAND_UIMM5_GT3";
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}
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def uimm10 : RISCVUImmLeafOp<10>;
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def uimm11 : RISCVUImmLeafOp<11>;
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//===----------------------------------------------------------------------===//
@@ -166,6 +168,36 @@ class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
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let rs2 = imm;
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}
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
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class QCIRVInst16CI_RS1<bits<5> funct5, string OpcodeStr>
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: RVInst16CI<0b000, 0b10, (outs), (ins GPRNoX0:$rs1), OpcodeStr, "$rs1"> {
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bits<5> rs1;
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let Inst{12} = 0b1;
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let Inst{11-7} = rs1;
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let Inst{6-2} = funct5{4-0};
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}
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let hasSideEffects = 1 in
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class QCIRVInst16CI_NONE<bits<5> funct5, string OpcodeStr>
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: RVInst16CI<0b000, 0b10, (outs), (ins), OpcodeStr, ""> {
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let Inst{12} = 0b1;
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let Inst{11-7} = funct5;
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let Inst{6-2} = 0b00100;
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}
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
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class QCIInt_IMM<bits<1> funct1, string opcodestr>
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: RVInstIBase<0b000, OPC_SYSTEM, (outs), (ins uimm10:$imm10), opcodestr,
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"$imm10"> {
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bits<10> imm10;
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let rd = 0;
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let rs1 = imm10{4-0};
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let Inst{31-25} = {0b110011, funct1};
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let Inst{24-20} = imm10{9-5};
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
@@ -312,6 +344,38 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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def QC_MVGEUI : QCIMVCCI<0b111, "qc.mvgeui", uimm5>;
313345
} // Predicates = [HasVendorXqcicm, IsRV32], DecoderNamespace = "Xqcicm"
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let Predicates = [HasVendorXqciint, IsRV32], DecoderNamespace = "Xqciint" in {
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let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
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def QC_C_DIR : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd), (ins),
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"qc.c.dir", "$rd"> {
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bits<5> rd;
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let Inst{12} = 0b1;
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let Inst{11-7} = rd;
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let Inst{6-2} = 0b00000;
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}
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def QC_SETINTI : QCIInt_IMM<0b0, "qc.setinti">;
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def QC_CLRINTI : QCIInt_IMM<0b1, "qc.clrinti">;
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def QC_C_EIR : QCIRVInst16CI_RS1<0b00001, "qc.c.eir">;
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def QC_C_SETINT : QCIRVInst16CI_RS1<0b00010, "qc.c.setint">;
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def QC_C_CLRINT : QCIRVInst16CI_RS1<0b00011, "qc.c.clrint">;
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let mayLoad = 0, mayStore = 0 in {
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def QC_C_DI : QCIRVInst16CI_NONE<0b10110, "qc.c.di">;
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def QC_C_EI : QCIRVInst16CI_NONE<0b10111, "qc.c.ei">;
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} // mayLoad =0, mayStore = 0
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let mayLoad = 1, mayStore = 1 in {
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def QC_C_MIENTER : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">;
372+
def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">;
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} // mayLoad = 1, mayStore = 1
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let mayLoad = 1, mayStore = 1, isReturn = 1, isTerminator = 1 in
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def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
377+
} // Predicates = [HasVendorXqciint, IsRV32], DecoderNamespace = "Xqciint"
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//===----------------------------------------------------------------------===//
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// Aliases
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//===----------------------------------------------------------------------===//

‎llvm/lib/TargetParser/RISCVISAInfo.cpp

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@@ -742,8 +742,8 @@ Error RISCVISAInfo::checkDependency() {
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bool HasZvl = MinVLen != 0;
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bool HasZcmt = Exts.count("zcmt") != 0;
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static constexpr StringLiteral XqciExts[] = {
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{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"},
746-
{"xqcics"}, {"xqcicsr"}, {"xqcilsm"}, {"xqcisls"}};
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{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"},
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{"xqcicsr"}, {"xqciint"}, {"xqcilsm"}, {"xqcisls"}};
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748748
if (HasI && HasE)
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return getIncompatibleError("i", "e");

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