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jmmartinezjmmartinez
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Revert "AMDGPU: Try constant fold after folding immediate (#141862)"
This reverts commit 80064b6. The patch triggers a crash when the folded use can have 2 operands in the fold list. See #148187 for more info. SWDEV-542372
1 parent e8f1125 commit 2f8a888

10 files changed

+46
-22
lines changed

‎llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1782,12 +1782,6 @@ bool SIFoldOperandsImpl::foldInstOperand(MachineInstr &MI,
17821782
LLVM_DEBUG(dbgs() << "Folded source from " << MI << " into OpNo "
17831783
<< static_cast<int>(Fold.UseOpNo) << " of "
17841784
<< *Fold.UseMI);
1785-
1786-
if (Fold.isImm() && tryConstantFoldOp(Fold.UseMI)) {
1787-
LLVM_DEBUG(dbgs() << "Constant folded " << *Fold.UseMI);
1788-
Changed = true;
1789-
}
1790-
17911785
} else if (Fold.Commuted) {
17921786
// Restoring instruction's original operand order if fold has failed.
17931787
TII->commuteInstruction(*Fold.UseMI, false);

‎llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,8 +105,9 @@ define i64 @v_xor_i64_known_i32_from_range_use_out_of_block(i64 %x) {
105105
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
106106
; CHECK-NEXT: ; %bb.1: ; %inc
107107
; CHECK-NEXT: v_not_b32_e32 v2, v4
108+
; CHECK-NEXT: v_not_b32_e32 v3, 0
108109
; CHECK-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2
109-
; CHECK-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc
110+
; CHECK-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc
110111
; CHECK-NEXT: ; %bb.2: ; %UnifiedReturnBlock
111112
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
112113
; CHECK-NEXT: v_mov_b32_e32 v0, v2

‎llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -973,7 +973,7 @@ body: |
973973
; GCN: liveins: $vgpr0, $vgpr1
974974
; GCN-NEXT: {{ $}}
975975
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
976-
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
976+
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 0, [[COPY]], implicit $exec
977977
; GCN-NEXT: S_ENDPGM 0, implicit [[COPY1]]
978978
%0:vgpr_32 = COPY $vgpr0
979979
%1:vgpr_32 = COPY $vgpr1

‎llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,8 @@ body: |
4343
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
4444
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
4545
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[DEF]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub1
46-
; GCN-NEXT: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[DEF2]], [[REG_SEQUENCE]].sub0, implicit $exec
46+
; GCN-NEXT: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 0, [[DEF1]], implicit $exec
47+
; GCN-NEXT: [[V_XOR_B32_e32_1:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[DEF2]], [[REG_SEQUENCE]].sub0, implicit $exec
4748
%0:vgpr_32 = IMPLICIT_DEF
4849
%1:vgpr_32 = IMPLICIT_DEF
4950
%2:vgpr_32 = IMPLICIT_DEF

‎llvm/test/CodeGen/AMDGPU/fold-zero-high-bits-skips-non-reg.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ body: |
88
; CHECK-LABEL: name: test_tryFoldZeroHighBits_skips_nonreg
99
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
1010
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
11-
; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
12-
; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
11+
; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 65535, 0, implicit $exec
12+
; CHECK-NEXT: S_NOP 0, implicit [[V_AND_B32_e64_]]
1313
%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
1414
%1:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1
1515
%2:vgpr_32 = V_AND_B32_e64 65535, %1.sub0, implicit $exec

‎llvm/test/CodeGen/AMDGPU/sdiv64.ll

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -404,11 +404,12 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) {
404404
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
405405
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v0
406406
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v1, vcc
407-
; GCN-IR-NEXT: v_not_b32_e32 v4, v10
407+
; GCN-IR-NEXT: v_not_b32_e32 v5, v10
408408
; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[6:7], v8
409-
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, v4, v11
409+
; GCN-IR-NEXT: v_not_b32_e32 v4, 0
410+
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, v5, v11
410411
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
411-
; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], -1, 0, vcc
412+
; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc
412413
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
413414
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
414415
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0

‎llvm/test/CodeGen/AMDGPU/si-fold-operands-swdev-542372.ll

Lines changed: 25 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,32 @@
1-
; RUN: not --crash llc -O3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s -o /dev/null
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -O3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s -o - | FileCheck %s
23

34
@lds = internal addrspace(3) global [5 x i32] poison
45

56
define amdgpu_kernel void @kernel() {
7+
; CHECK-LABEL: kernel:
8+
; CHECK: ; %bb.0: ; %entry
9+
; CHECK-NEXT: v_mov_b32_e32 v0, 0
10+
; CHECK-NEXT: ds_read_b64 v[2:3], v0
11+
; CHECK-NEXT: ds_write_b32 v0, v0
12+
; CHECK-NEXT: s_waitcnt lgkmcnt(1)
13+
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 2, v2
14+
; CHECK-NEXT: s_cbranch_vccnz .LBB0_3
15+
; CHECK-NEXT: ; %bb.1: ; %land.rhs49
16+
; CHECK-NEXT: ds_read_b64 v[0:1], v0
17+
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
18+
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 1, v0
19+
; CHECK-NEXT: s_cbranch_vccnz .LBB0_3
20+
; CHECK-NEXT: ; %bb.2: ; %land.rhs57
21+
; CHECK-NEXT: s_mov_b32 s0, 0
22+
; CHECK-NEXT: s_mov_b32 s1, s0
23+
; CHECK-NEXT: v_mov_b32_e32 v2, 0
24+
; CHECK-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
25+
; CHECK-NEXT: s_or_b32 s0, 0, 0
26+
; CHECK-NEXT: s_cmp_lg_u32 s0, 0
27+
; CHECK-NEXT: ds_write_b64 v2, v[0:1]
28+
; CHECK-NEXT: .LBB0_3: ; %land.end59
29+
; CHECK-NEXT: s_endpgm
630
entry:
731
%load.lds.0 = load <2 x i32>, ptr addrspace(3) @lds
832
%vecext.i55 = extractelement <2 x i32> %load.lds.0, i64 0

‎llvm/test/CodeGen/AMDGPU/srem64.ll

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -380,11 +380,12 @@ define i64 @v_test_srem(i64 %x, i64 %y) {
380380
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
381381
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v2
382382
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v3, vcc
383-
; GCN-IR-NEXT: v_not_b32_e32 v6, v12
383+
; GCN-IR-NEXT: v_not_b32_e32 v7, v12
384384
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v8
385-
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v6, v13
385+
; GCN-IR-NEXT: v_not_b32_e32 v6, 0
386+
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v7, v13
386387
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
387-
; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], -1, 0, vcc
388+
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc
388389
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
389390
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
390391
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0

‎llvm/test/CodeGen/AMDGPU/udiv64.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -348,9 +348,10 @@ define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
348348
; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v10
349349
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v3, vcc
350350
; GCN-IR-NEXT: v_not_b32_e32 v0, v14
351+
; GCN-IR-NEXT: v_not_b32_e32 v1, 0
351352
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v15
352353
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
353-
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], -1, 0, vcc
354+
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
354355
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
355356
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
356357
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0

‎llvm/test/CodeGen/AMDGPU/urem64.ll

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -355,11 +355,12 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) {
355355
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
356356
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2
357357
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc
358-
; GCN-IR-NEXT: v_not_b32_e32 v6, v12
358+
; GCN-IR-NEXT: v_not_b32_e32 v7, v12
359359
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v8
360-
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v6, v13
360+
; GCN-IR-NEXT: v_not_b32_e32 v6, 0
361+
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v7, v13
361362
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
362-
; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], -1, 0, vcc
363+
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc
363364
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
364365
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
365366
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0

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