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RKSimonRKSimon
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[MC][X86] Add (V)PMADDUBSW constant comment handling
1 parent 035e0fa commit 6ae75c2

17 files changed

+127
-110
lines changed

‎llvm/lib/Target/X86/X86MCInstLower.cpp

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1916,6 +1916,23 @@ static void addConstantComments(const MachineInstr *MI,
19161916
INSTR_CASE(V, Instr, Z, kz)
19171917

19181918
// TODO: Add additional instructions when useful.
1919+
CASE_ARITH_RM(PMADDUBSW) {
1920+
unsigned SrcIdx = getSrcIdx(MI, 1);
1921+
if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) {
1922+
if (C->getType()->getScalarSizeInBits() == 8) {
1923+
std::string Comment;
1924+
raw_string_ostream CS(Comment);
1925+
unsigned VectorWidth =
1926+
X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1927+
CS << "[";
1928+
printConstant(C, VectorWidth, CS);
1929+
CS << "]";
1930+
OutStreamer.AddComment(CS.str());
1931+
}
1932+
}
1933+
break;
1934+
}
1935+
19191936
CASE_ARITH_RM(PMADDWD)
19201937
CASE_ARITH_RM(PMULLW)
19211938
CASE_ARITH_RM(PMULHW)

‎llvm/test/CodeGen/X86/combine-mul.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -542,9 +542,9 @@ define <16 x i8> @PR35579(<16 x i8> %x) {
542542
; SSE-LABEL: PR35579:
543543
; SSE: # %bb.0:
544544
; SSE-NEXT: movdqa %xmm0, %xmm1
545-
; SSE-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
545+
; SSE-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
546546
; SSE-NEXT: psllw $8, %xmm1
547-
; SSE-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
547+
; SSE-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [0,0,2,0,4,0,2,0,8,0,2,0,4,0,2,0]
548548
; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
549549
; SSE-NEXT: por %xmm1, %xmm0
550550
; SSE-NEXT: retq

‎llvm/test/CodeGen/X86/gfni-shifts.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -386,18 +386,18 @@ define <16 x i8> @constant_shl_v16i8(<16 x i8> %a) nounwind {
386386
; GFNISSE-LABEL: constant_shl_v16i8:
387387
; GFNISSE: # %bb.0:
388388
; GFNISSE-NEXT: movdqa %xmm0, %xmm1
389-
; GFNISSE-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
389+
; GFNISSE-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
390390
; GFNISSE-NEXT: psllw $8, %xmm1
391-
; GFNISSE-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
391+
; GFNISSE-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0]
392392
; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
393393
; GFNISSE-NEXT: por %xmm1, %xmm0
394394
; GFNISSE-NEXT: retq
395395
;
396396
; GFNIAVX1-LABEL: constant_shl_v16i8:
397397
; GFNIAVX1: # %bb.0:
398-
; GFNIAVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
398+
; GFNIAVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
399399
; GFNIAVX1-NEXT: vpsllw $8, %xmm1, %xmm1
400-
; GFNIAVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
400+
; GFNIAVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0]
401401
; GFNIAVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
402402
; GFNIAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
403403
; GFNIAVX1-NEXT: retq
@@ -1256,17 +1256,17 @@ define <32 x i8> @constant_shl_v32i8(<32 x i8> %a) nounwind {
12561256
;
12571257
; GFNIAVX2-LABEL: constant_shl_v32i8:
12581258
; GFNIAVX2: # %bb.0:
1259-
; GFNIAVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
1259+
; GFNIAVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
12601260
; GFNIAVX2-NEXT: vpsllw $8, %ymm1, %ymm1
1261-
; GFNIAVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1261+
; GFNIAVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0,1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0]
12621262
; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
12631263
; GFNIAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
12641264
; GFNIAVX2-NEXT: retq
12651265
;
12661266
; GFNIAVX512VL-LABEL: constant_shl_v32i8:
12671267
; GFNIAVX512VL: # %bb.0:
1268-
; GFNIAVX512VL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
1269-
; GFNIAVX512VL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1268+
; GFNIAVX512VL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 # [1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0,1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0]
1269+
; GFNIAVX512VL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
12701270
; GFNIAVX512VL-NEXT: vpsllw $8, %ymm0, %ymm0
12711271
; GFNIAVX512VL-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
12721272
; GFNIAVX512VL-NEXT: retq
@@ -2666,8 +2666,8 @@ define <64 x i8> @constant_shl_v64i8(<64 x i8> %a) nounwind {
26662666
;
26672667
; GFNIAVX512BW-LABEL: constant_shl_v64i8:
26682668
; GFNIAVX512BW: # %bb.0:
2669-
; GFNIAVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
2670-
; GFNIAVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
2669+
; GFNIAVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 # [1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0,1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0,1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0,1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0]
2670+
; GFNIAVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
26712671
; GFNIAVX512BW-NEXT: vpsllw $8, %zmm0, %zmm0
26722672
; GFNIAVX512BW-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
26732673
; GFNIAVX512BW-NEXT: retq

‎llvm/test/CodeGen/X86/pmul.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,9 @@ define <16 x i8> @mul_v16i8c(<16 x i8> %i) nounwind {
2323
; SSE41-LABEL: mul_v16i8c:
2424
; SSE41: # %bb.0: # %entry
2525
; SSE41-NEXT: movdqa %xmm0, %xmm1
26-
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
26+
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117]
2727
; SSE41-NEXT: psllw $8, %xmm1
28-
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
28+
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0]
2929
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
3030
; SSE41-NEXT: por %xmm1, %xmm0
3131
; SSE41-NEXT: retq
@@ -420,18 +420,18 @@ define <32 x i8> @mul_v32i8c(<32 x i8> %i) nounwind {
420420
;
421421
; AVX2-LABEL: mul_v32i8c:
422422
; AVX2: # %bb.0: # %entry
423-
; AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
423+
; AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 # [0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117]
424424
; AVX2-NEXT: vpsllw $8, %ymm1, %ymm1
425-
; AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
425+
; AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0]
426426
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
427427
; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
428428
; AVX2-NEXT: retq
429429
;
430430
; AVX512F-LABEL: mul_v32i8c:
431431
; AVX512F: # %bb.0: # %entry
432-
; AVX512F-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
432+
; AVX512F-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 # [0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117]
433433
; AVX512F-NEXT: vpsllw $8, %ymm1, %ymm1
434-
; AVX512F-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
434+
; AVX512F-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0]
435435
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
436436
; AVX512F-NEXT: vpor %ymm1, %ymm0, %ymm0
437437
; AVX512F-NEXT: retq
@@ -844,8 +844,8 @@ define <64 x i8> @mul_v64i8c(<64 x i8> %i) nounwind {
844844
;
845845
; AVX512BW-LABEL: mul_v64i8c:
846846
; AVX512BW: # %bb.0: # %entry
847-
; AVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1
848-
; AVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
847+
; AVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 # [117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0]
848+
; AVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117,0,117]
849849
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm0
850850
; AVX512BW-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
851851
; AVX512BW-NEXT: retq

‎llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -2280,11 +2280,11 @@ define <32 x i1> @pr51133(<32 x i8> %x, <32 x i8> %y) {
22802280
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm4
22812281
; CHECK-SSE41-NEXT: movq %rdi, %rax
22822282
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm0
2283-
; CHECK-SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
2283+
; CHECK-SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [171,0,183,0,61,0,127,0,9,0,41,0,1,0,161,0]
22842284
; CHECK-SSE41-NEXT: pmovzxbw {{.*#+}} xmm5 = [255,255,255,255,255,255,255,255]
22852285
; CHECK-SSE41-NEXT: pand %xmm5, %xmm0
22862286
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm6
2287-
; CHECK-SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
2287+
; CHECK-SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 # [0,103,0,171,0,1,0,183,0,0,0,183,0,1,0,221]
22882288
; CHECK-SSE41-NEXT: psllw $8, %xmm6
22892289
; CHECK-SSE41-NEXT: por %xmm0, %xmm6
22902290
; CHECK-SSE41-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6
@@ -2307,9 +2307,9 @@ define <32 x i1> @pr51133(<32 x i8> %x, <32 x i8> %y) {
23072307
; CHECK-SSE41-NEXT: movaps {{.*#+}} xmm0 = [255,255,255,255,255,0,255,255,255,255,255,255,255,255,255,255]
23082308
; CHECK-SSE41-NEXT: pblendvb %xmm0, %xmm7, %xmm1
23092309
; CHECK-SSE41-NEXT: movdqa %xmm4, %xmm0
2310-
; CHECK-SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
2310+
; CHECK-SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [197,0,27,0,1,0,1,0,223,0,205,0,161,0,171,0]
23112311
; CHECK-SSE41-NEXT: pand %xmm5, %xmm0
2312-
; CHECK-SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
2312+
; CHECK-SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 # [0,205,0,241,0,1,0,163,0,223,0,183,0,1,0,239]
23132313
; CHECK-SSE41-NEXT: psllw $8, %xmm4
23142314
; CHECK-SSE41-NEXT: por %xmm0, %xmm4
23152315
; CHECK-SSE41-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
@@ -2345,10 +2345,10 @@ define <32 x i1> @pr51133(<32 x i8> %x, <32 x i8> %y) {
23452345
; CHECK-AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [20224,26368,6912,30976,33024,33024,33024,12032]
23462346
; CHECK-AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
23472347
; CHECK-AVX1-NEXT: vpackuswb %xmm3, %xmm4, %xmm4
2348-
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm5
2348+
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm5 # [0,0,0,0,1,0,1,0,1,0,0,0,0,0,0,0]
23492349
; CHECK-AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
23502350
; CHECK-AVX1-NEXT: vpand %xmm3, %xmm5, %xmm5
2351-
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm6
2351+
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm6 # [0,0,0,0,0,1,0,0,0,1,0,1,0,1,0,1]
23522352
; CHECK-AVX1-NEXT: vpsllw $8, %xmm6, %xmm6
23532353
; CHECK-AVX1-NEXT: vpor %xmm6, %xmm5, %xmm5
23542354
; CHECK-AVX1-NEXT: vpaddb %xmm5, %xmm4, %xmm4
@@ -2365,9 +2365,9 @@ define <32 x i1> @pr51133(<32 x i8> %x, <32 x i8> %y) {
23652365
; CHECK-AVX1-NEXT: vbroadcastss {{.*#+}} xmm5 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
23662366
; CHECK-AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
23672367
; CHECK-AVX1-NEXT: vpaddb %xmm4, %xmm6, %xmm4
2368-
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm6
2368+
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm6 # [13,0,19,0,2,0,2,0,62,0,5,0,97,0,3,0]
23692369
; CHECK-AVX1-NEXT: vpand %xmm3, %xmm6, %xmm6
2370-
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4
2370+
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm4 # [0,5,0,34,0,8,0,88,0,62,0,7,0,2,0,60]
23712371
; CHECK-AVX1-NEXT: vpsllw $8, %xmm4, %xmm4
23722372
; CHECK-AVX1-NEXT: vpor %xmm4, %xmm6, %xmm4
23732373
; CHECK-AVX1-NEXT: vpsubb %xmm4, %xmm0, %xmm4
@@ -2379,9 +2379,9 @@ define <32 x i1> @pr51133(<32 x i8> %x, <32 x i8> %y) {
23792379
; CHECK-AVX1-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm7, %xmm7 # [22016,24320,37632,11008,12544,32512,16640,37632]
23802380
; CHECK-AVX1-NEXT: vpsrlw $8, %xmm7, %xmm7
23812381
; CHECK-AVX1-NEXT: vpackuswb %xmm6, %xmm7, %xmm6
2382-
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm7
2382+
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm7 # [0,0,1,0,0,0,0,0,0,0,0,0,1,0,0,0]
23832383
; CHECK-AVX1-NEXT: vpand %xmm3, %xmm7, %xmm7
2384-
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm8
2384+
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm8 # [0,0,0,0,0,255,0,1,0,1,0,1,0,1,0,1]
23852385
; CHECK-AVX1-NEXT: vpsllw $8, %xmm8, %xmm8
23862386
; CHECK-AVX1-NEXT: vpor %xmm7, %xmm8, %xmm7
23872387
; CHECK-AVX1-NEXT: vpaddb %xmm7, %xmm6, %xmm6
@@ -2398,9 +2398,9 @@ define <32 x i1> @pr51133(<32 x i8> %x, <32 x i8> %y) {
23982398
; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6, %xmm6
23992399
; CHECK-AVX1-NEXT: vpand %xmm5, %xmm6, %xmm5
24002400
; CHECK-AVX1-NEXT: vpaddb %xmm5, %xmm7, %xmm5
2401-
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm6
2401+
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm6 # [3,0,7,0,84,0,127,0,114,0,50,0,2,0,97,0]
24022402
; CHECK-AVX1-NEXT: vpand %xmm3, %xmm6, %xmm3
2403-
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5
2403+
; CHECK-AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm5 # [0,87,0,6,0,128,0,56,0,1,0,7,0,8,0,117]
24042404
; CHECK-AVX1-NEXT: vpsllw $8, %xmm5, %xmm5
24052405
; CHECK-AVX1-NEXT: vpor %xmm5, %xmm3, %xmm3
24062406
; CHECK-AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0
@@ -2427,10 +2427,10 @@ define <32 x i1> @pr51133(<32 x i8> %x, <32 x i8> %y) {
24272427
; CHECK-AVX2-NEXT: vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm4, %ymm4 # [20224,26368,6912,30976,33024,33024,33024,12032,22016,24320,37632,11008,12544,32512,16640,37632]
24282428
; CHECK-AVX2-NEXT: vpsrlw $8, %ymm4, %ymm4
24292429
; CHECK-AVX2-NEXT: vpackuswb %ymm3, %ymm4, %ymm3
2430-
; CHECK-AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm4
2430+
; CHECK-AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm4 # [0,0,0,0,1,0,1,0,1,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,1,0,0,0]
24312431
; CHECK-AVX2-NEXT: vpbroadcastw {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
24322432
; CHECK-AVX2-NEXT: vpand %ymm5, %ymm4, %ymm4
2433-
; CHECK-AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm6
2433+
; CHECK-AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm6 # [0,0,0,0,0,1,0,0,0,1,0,1,0,1,0,1,0,0,0,0,0,255,0,1,0,1,0,1,0,1,0,1]
24342434
; CHECK-AVX2-NEXT: vpsllw $8, %ymm6, %ymm6
24352435
; CHECK-AVX2-NEXT: vpor %ymm6, %ymm4, %ymm4
24362436
; CHECK-AVX2-NEXT: vpaddb %ymm4, %ymm3, %ymm3
@@ -2447,9 +2447,9 @@ define <32 x i1> @pr51133(<32 x i8> %x, <32 x i8> %y) {
24472447
; CHECK-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
24482448
; CHECK-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
24492449
; CHECK-AVX2-NEXT: vpaddb %ymm3, %ymm4, %ymm3
2450-
; CHECK-AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm4
2450+
; CHECK-AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm4 # [13,0,19,0,2,0,2,0,62,0,5,0,97,0,3,0,3,0,7,0,84,0,127,0,114,0,50,0,2,0,97,0]
24512451
; CHECK-AVX2-NEXT: vpand %ymm5, %ymm4, %ymm4
2452-
; CHECK-AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3
2452+
; CHECK-AVX2-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm3 # [0,5,0,34,0,8,0,88,0,62,0,7,0,2,0,60,0,87,0,6,0,128,0,56,0,1,0,7,0,8,0,117]
24532453
; CHECK-AVX2-NEXT: vpsllw $8, %ymm3, %ymm3
24542454
; CHECK-AVX2-NEXT: vpor %ymm3, %ymm4, %ymm3
24552455
; CHECK-AVX2-NEXT: vpsubb %ymm3, %ymm0, %ymm0
@@ -2462,8 +2462,8 @@ define <32 x i1> @pr51133(<32 x i8> %x, <32 x i8> %y) {
24622462
;
24632463
; CHECK-AVX512VL-LABEL: pr51133:
24642464
; CHECK-AVX512VL: # %bb.0:
2465-
; CHECK-AVX512VL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2
2466-
; CHECK-AVX512VL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3
2465+
; CHECK-AVX512VL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2 # [197,0,27,0,1,0,1,0,223,0,205,0,161,0,171,0,171,0,183,0,61,0,127,0,9,0,41,0,1,0,161,0]
2466+
; CHECK-AVX512VL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm3 # [0,205,0,241,0,1,0,163,0,223,0,183,0,1,0,239,0,103,0,171,0,1,0,183,0,0,0,183,0,1,0,221]
24672467
; CHECK-AVX512VL-NEXT: vpsllw $8, %ymm3, %ymm3
24682468
; CHECK-AVX512VL-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm3
24692469
; CHECK-AVX512VL-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm3, %ymm2

‎llvm/test/CodeGen/X86/vector-fshr-128.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2011,10 +2011,10 @@ define <16 x i8> @constant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
20112011
; SSE41-NEXT: packuswb %xmm1, %xmm3
20122012
; SSE41-NEXT: paddb %xmm0, %xmm0
20132013
; SSE41-NEXT: movdqa %xmm0, %xmm1
2014-
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
2014+
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,64,0,16,0,4,0,1,0,1,0,4,0,16,0,64]
20152015
; SSE41-NEXT: psllw $8, %xmm1
20162016
; SSE41-NEXT: por %xmm3, %xmm1
2017-
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
2017+
; SSE41-NEXT: pmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [128,0,32,0,8,0,2,0,128,0,2,0,8,0,32,0]
20182018
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
20192019
; SSE41-NEXT: por %xmm1, %xmm0
20202020
; SSE41-NEXT: retq
@@ -2030,10 +2030,10 @@ define <16 x i8> @constant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
20302030
; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
20312031
; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
20322032
; AVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0
2033-
; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2
2033+
; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm2 # [0,64,0,16,0,4,0,1,0,1,0,4,0,16,0,64]
20342034
; AVX1-NEXT: vpsllw $8, %xmm2, %xmm2
20352035
; AVX1-NEXT: vpor %xmm1, %xmm2, %xmm1
2036-
; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
2036+
; AVX1-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [128,0,32,0,8,0,2,0,128,0,2,0,8,0,32,0]
20372037
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
20382038
; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
20392039
; AVX1-NEXT: retq

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