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[llvm-objcopy][libObject] Add RISC-V big-endian support (#146913)
Add support for big-endian RISC-V ELF files: - Add riscv32be/riscv64be target architectures to Triple - Support elf32-bigriscv and elf64-bigriscv output targets in llvm-objcopy - Update ELFObjectFile to handle BE RISC-V format strings and architecture detection - Add BE RISC-V support to RelocationResolver - Add tests for new functionality This is a subset of a bigger RISC-V big-endian support patch, containing only the llvm-objcopy and libObject changes. Other changes will be added later.
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8 files changed

+264
-214
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‎clang/test/Driver/frame-pointer-elim.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@
162162
// RUN: FileCheck --check-prefix=KEEP-ALL %s
163163
// RUN: %clang -### --target=riscv64-linux-android -O1 -S %s 2>&1 | \
164164
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
165-
// RUN: not %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s 2>&1 | \
165+
// RUN: %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s 2>&1 | \
166166
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
167167

168168
// On ARM backend bare metal targets, frame pointer is omitted

‎llvm/include/llvm/Object/ELFObjectFile.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1312,7 +1312,7 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
13121312
case ELF::EM_PPC:
13131313
return (IsLittleEndian ? "elf32-powerpcle" : "elf32-powerpc");
13141314
case ELF::EM_RISCV:
1315-
return "elf32-littleriscv";
1315+
return (IsLittleEndian ? "elf32-littleriscv" : "elf32-bigriscv");
13161316
case ELF::EM_CSKY:
13171317
return "elf32-csky";
13181318
case ELF::EM_SPARC:
@@ -1338,7 +1338,7 @@ StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
13381338
case ELF::EM_PPC64:
13391339
return (IsLittleEndian ? "elf64-powerpcle" : "elf64-powerpc");
13401340
case ELF::EM_RISCV:
1341-
return "elf64-littleriscv";
1341+
return (IsLittleEndian ? "elf64-littleriscv" : "elf64-bigriscv");
13421342
case ELF::EM_S390:
13431343
return "elf64-s390";
13441344
case ELF::EM_SPARCV9:
@@ -1400,9 +1400,9 @@ template <class ELFT> Triple::ArchType ELFObjectFile<ELFT>::getArch() const {
14001400
case ELF::EM_RISCV:
14011401
switch (EF.getHeader().e_ident[ELF::EI_CLASS]) {
14021402
case ELF::ELFCLASS32:
1403-
return Triple::riscv32;
1403+
return IsLittleEndian ? Triple::riscv32 : Triple::riscv32be;
14041404
case ELF::ELFCLASS64:
1405-
return Triple::riscv64;
1405+
return IsLittleEndian ? Triple::riscv64 : Triple::riscv64be;
14061406
default:
14071407
report_fatal_error("Invalid ELFCLASS!");
14081408
}

‎llvm/include/llvm/TargetParser/Triple.h

Lines changed: 64 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -49,62 +49,64 @@ class Triple {
4949
enum ArchType {
5050
UnknownArch,
5151

52-
arm, // ARM (little endian): arm, armv.*, xscale
53-
armeb, // ARM (big endian): armeb
54-
aarch64, // AArch64 (little endian): aarch64
55-
aarch64_be, // AArch64 (big endian): aarch64_be
56-
aarch64_32, // AArch64 (little endian) ILP32: aarch64_32
57-
arc, // ARC: Synopsys ARC
58-
avr, // AVR: Atmel AVR microcontroller
59-
bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
60-
bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
61-
csky, // CSKY: csky
62-
dxil, // DXIL 32-bit DirectX bytecode
63-
hexagon, // Hexagon: hexagon
64-
loongarch32, // LoongArch (32-bit): loongarch32
65-
loongarch64, // LoongArch (64-bit): loongarch64
66-
m68k, // M68k: Motorola 680x0 family
67-
mips, // MIPS: mips, mipsallegrex, mipsr6
68-
mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
69-
mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
70-
mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
71-
msp430, // MSP430: msp430
72-
ppc, // PPC: powerpc
73-
ppcle, // PPCLE: powerpc (little endian)
74-
ppc64, // PPC64: powerpc64, ppu
75-
ppc64le, // PPC64LE: powerpc64le
76-
r600, // R600: AMD GPUs HD2XXX - HD6XXX
77-
amdgcn, // AMDGCN: AMD GCN GPUs
78-
riscv32, // RISC-V (32-bit): riscv32
79-
riscv64, // RISC-V (64-bit): riscv64
80-
sparc, // Sparc: sparc
81-
sparcv9, // Sparcv9: Sparcv9
82-
sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
83-
systemz, // SystemZ: s390x
84-
tce, // TCE (http://tce.cs.tut.fi/): tce
85-
tcele, // TCE little endian (http://tce.cs.tut.fi/): tcele
86-
thumb, // Thumb (little endian): thumb, thumbv.*
87-
thumbeb, // Thumb (big endian): thumbeb
88-
x86, // X86: i[3-9]86
89-
x86_64, // X86-64: amd64, x86_64
90-
xcore, // XCore: xcore
91-
xtensa, // Tensilica: Xtensa
92-
nvptx, // NVPTX: 32-bit
93-
nvptx64, // NVPTX: 64-bit
94-
amdil, // AMDIL
95-
amdil64, // AMDIL with 64-bit pointers
96-
hsail, // AMD HSAIL
97-
hsail64, // AMD HSAIL with 64-bit pointers
98-
spir, // SPIR: standard portable IR for OpenCL 32-bit version
99-
spir64, // SPIR: standard portable IR for OpenCL 64-bit version
100-
spirv, // SPIR-V with logical memory layout.
101-
spirv32, // SPIR-V with 32-bit pointers
102-
spirv64, // SPIR-V with 64-bit pointers
103-
kalimba, // Kalimba: generic kalimba
104-
shave, // SHAVE: Movidius vector VLIW processors
105-
lanai, // Lanai: Lanai 32-bit
106-
wasm32, // WebAssembly with 32-bit pointers
107-
wasm64, // WebAssembly with 64-bit pointers
52+
arm, // ARM (little endian): arm, armv.*, xscale
53+
armeb, // ARM (big endian): armeb
54+
aarch64, // AArch64 (little endian): aarch64
55+
aarch64_be, // AArch64 (big endian): aarch64_be
56+
aarch64_32, // AArch64 (little endian) ILP32: aarch64_32
57+
arc, // ARC: Synopsys ARC
58+
avr, // AVR: Atmel AVR microcontroller
59+
bpfel, // eBPF or extended BPF or 64-bit BPF (little endian)
60+
bpfeb, // eBPF or extended BPF or 64-bit BPF (big endian)
61+
csky, // CSKY: csky
62+
dxil, // DXIL 32-bit DirectX bytecode
63+
hexagon, // Hexagon: hexagon
64+
loongarch32, // LoongArch (32-bit): loongarch32
65+
loongarch64, // LoongArch (64-bit): loongarch64
66+
m68k, // M68k: Motorola 680x0 family
67+
mips, // MIPS: mips, mipsallegrex, mipsr6
68+
mipsel, // MIPSEL: mipsel, mipsallegrexe, mipsr6el
69+
mips64, // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6
70+
mips64el, // MIPS64EL: mips64el, mips64r6el, mipsn32el, mipsn32r6el
71+
msp430, // MSP430: msp430
72+
ppc, // PPC: powerpc
73+
ppcle, // PPCLE: powerpc (little endian)
74+
ppc64, // PPC64: powerpc64, ppu
75+
ppc64le, // PPC64LE: powerpc64le
76+
r600, // R600: AMD GPUs HD2XXX - HD6XXX
77+
amdgcn, // AMDGCN: AMD GCN GPUs
78+
riscv32, // RISC-V (32-bit, little endian): riscv32
79+
riscv64, // RISC-V (64-bit, little endian): riscv64
80+
riscv32be, // RISC-V (32-bit, big endian): riscv32be
81+
riscv64be, // RISC-V (64-bit, big endian): riscv64be
82+
sparc, // Sparc: sparc
83+
sparcv9, // Sparcv9: Sparcv9
84+
sparcel, // Sparc: (endianness = little). NB: 'Sparcle' is a CPU variant
85+
systemz, // SystemZ: s390x
86+
tce, // TCE (http://tce.cs.tut.fi/): tce
87+
tcele, // TCE little endian (http://tce.cs.tut.fi/): tcele
88+
thumb, // Thumb (little endian): thumb, thumbv.*
89+
thumbeb, // Thumb (big endian): thumbeb
90+
x86, // X86: i[3-9]86
91+
x86_64, // X86-64: amd64, x86_64
92+
xcore, // XCore: xcore
93+
xtensa, // Tensilica: Xtensa
94+
nvptx, // NVPTX: 32-bit
95+
nvptx64, // NVPTX: 64-bit
96+
amdil, // AMDIL
97+
amdil64, // AMDIL with 64-bit pointers
98+
hsail, // AMD HSAIL
99+
hsail64, // AMD HSAIL with 64-bit pointers
100+
spir, // SPIR: standard portable IR for OpenCL 32-bit version
101+
spir64, // SPIR: standard portable IR for OpenCL 64-bit version
102+
spirv, // SPIR-V with logical memory layout.
103+
spirv32, // SPIR-V with 32-bit pointers
104+
spirv64, // SPIR-V with 64-bit pointers
105+
kalimba, // Kalimba: generic kalimba
106+
shave, // SHAVE: Movidius vector VLIW processors
107+
lanai, // Lanai: Lanai 32-bit
108+
wasm32, // WebAssembly with 32-bit pointers
109+
wasm64, // WebAssembly with 64-bit pointers
108110
renderscript32, // 32-bit RenderScript
109111
renderscript64, // 64-bit RenderScript
110112
ve, // NEC SX-Aurora Vector Engine
@@ -1064,10 +1066,14 @@ class Triple {
10641066
}
10651067

10661068
/// Tests whether the target is 32-bit RISC-V.
1067-
bool isRISCV32() const { return getArch() == Triple::riscv32; }
1069+
bool isRISCV32() const {
1070+
return getArch() == Triple::riscv32 || getArch() == Triple::riscv32be;
1071+
}
10681072

10691073
/// Tests whether the target is 64-bit RISC-V.
1070-
bool isRISCV64() const { return getArch() == Triple::riscv64; }
1074+
bool isRISCV64() const {
1075+
return getArch() == Triple::riscv64 || getArch() == Triple::riscv64be;
1076+
}
10711077

10721078
/// Tests whether the target is RISC-V (32- and 64-bit).
10731079
bool isRISCV() const { return isRISCV32() || isRISCV64(); }

‎llvm/lib/Object/RelocationResolver.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -812,6 +812,7 @@ getRelocationResolver(const ObjectFile &Obj) {
812812
case Triple::amdgcn:
813813
return {supportsAmdgpu, resolveAmdgpu};
814814
case Triple::riscv64:
815+
case Triple::riscv64be:
815816
return {supportsRISCV, resolveRISCV};
816817
default:
817818
if (isAMDGPU(Obj))
@@ -851,6 +852,7 @@ getRelocationResolver(const ObjectFile &Obj) {
851852
case Triple::r600:
852853
return {supportsAmdgpu, resolveAmdgpu};
853854
case Triple::riscv32:
855+
case Triple::riscv32be:
854856
return {supportsRISCV, resolveRISCV};
855857
case Triple::csky:
856858
return {supportsCSKY, resolveCSKY};
@@ -897,7 +899,9 @@ uint64_t resolveRelocation(RelocationResolver Resolver, const RelocationRef &R,
897899
if (Obj->getArch() != Triple::loongarch32 &&
898900
Obj->getArch() != Triple::loongarch64 &&
899901
Obj->getArch() != Triple::riscv32 &&
900-
Obj->getArch() != Triple::riscv64)
902+
Obj->getArch() != Triple::riscv64 &&
903+
Obj->getArch() != Triple::riscv32be &&
904+
Obj->getArch() != Triple::riscv64be)
901905
LocData = 0;
902906
}
903907
}

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