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[Clang][RISCV] Remove RVV intrinsics vread_csr,vwrite_csr
As proposed in riscv-non-isa/rvv-intrinsic-doc#249, removing the interface. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D156321
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clang/include/clang/Basic/riscv_vector.td

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@@ -990,56 +990,6 @@ multiclass RVVPseudoVNCVTBuiltin<string IR, string MName, string type_range,
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}
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}
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// Define vread_csr&vwrite_csr described in RVV intrinsics doc.
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let HeaderCode =
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[{
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enum RVV_CSR {
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RVV_VSTART = 0,
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RVV_VXSAT,
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RVV_VXRM,
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RVV_VCSR,
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};
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static __inline__ __attribute__((__always_inline__, __nodebug__))
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unsigned long __riscv_vread_csr(enum RVV_CSR __csr) {
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unsigned long __rv = 0;
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switch (__csr) {
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case RVV_VSTART:
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__asm__ __volatile__ ("csrr\t%0, vstart" : "=r"(__rv) : : "memory");
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break;
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case RVV_VXSAT:
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__asm__ __volatile__ ("csrr\t%0, vxsat" : "=r"(__rv) : : "memory");
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break;
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case RVV_VXRM:
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__asm__ __volatile__ ("csrr\t%0, vxrm" : "=r"(__rv) : : "memory");
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break;
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case RVV_VCSR:
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__asm__ __volatile__ ("csrr\t%0, vcsr" : "=r"(__rv) : : "memory");
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break;
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}
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return __rv;
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}
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static __inline__ __attribute__((__always_inline__, __nodebug__))
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void __riscv_vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
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switch (__csr) {
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case RVV_VSTART:
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__asm__ __volatile__ ("csrw\tvstart, %z0" : : "rJ"(__value) : "memory");
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break;
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case RVV_VXSAT:
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__asm__ __volatile__ ("csrw\tvxsat, %z0" : : "rJ"(__value) : "memory");
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break;
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case RVV_VXRM:
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__asm__ __volatile__ ("csrw\tvxrm, %z0" : : "rJ"(__value) : "memory");
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break;
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case RVV_VCSR:
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__asm__ __volatile__ ("csrw\tvcsr, %z0" : : "rJ"(__value) : "memory");
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break;
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}
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}
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}] in
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def vread_vwrite_csr: RVVHeader;
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let HeaderCode =
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[{
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#define __riscv_vlenb() __builtin_rvv_vlenb()

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vread-csr.c

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clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vwrite-csr.c

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