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[Xtensa] Minor fixes, remove redundant code.
Removed redundant operations promotions and actions. Also removed setcc lowering and redundant branch kind cases from GetBranchKind() function. Implemented additional br_cc tests.
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4 files changed

+127
-58
lines changed

4 files changed

+127
-58
lines changed

‎llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

Lines changed: 1 addition & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -85,26 +85,13 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
8585
// indirect jump.
8686
setOperationAction(ISD::BR_JT, MVT::Other, Custom);
8787

88-
setOperationPromotedToType(ISD::BR_CC, MVT::i1, MVT::i32);
8988
setOperationAction(ISD::BR_CC, MVT::i32, Legal);
9089
setOperationAction(ISD::BR_CC, MVT::i64, Expand);
9190
setOperationAction(ISD::BR_CC, MVT::f32, Expand);
9291

93-
// Used by legalize types to correctly generate the setcc result.
94-
setOperationPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
95-
setOperationPromotedToType(ISD::BR_CC, MVT::i1, MVT::i32);
96-
97-
setOperationAction(ISD::BR_CC, MVT::i32, Legal);
98-
setOperationAction(ISD::BR_CC, MVT::i64, Expand);
99-
10092
setOperationAction(ISD::SELECT, MVT::i32, Expand);
101-
setOperationAction(ISD::SELECT, MVT::i64, Expand);
102-
10393
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
104-
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
105-
106-
setOperationAction(ISD::SETCC, MVT::i32, Custom);
107-
setOperationAction(ISD::SETCC, MVT::i64, Expand);
94+
setOperationAction(ISD::SETCC, MVT::i32, Expand);
10895

10996
// Implement custom stack allocations
11097
setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
@@ -546,22 +533,6 @@ SDValue XtensaTargetLowering::LowerSELECT_CC(SDValue Op,
546533
FalseValue, TargetCC);
547534
}
548535

549-
SDValue XtensaTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
550-
SDLoc DL(Op);
551-
EVT Ty = Op.getOperand(0).getValueType();
552-
SDValue LHS = Op.getOperand(0);
553-
SDValue RHS = Op.getOperand(1);
554-
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
555-
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
556-
557-
// Expand to target SELECT_CC
558-
SDValue TrueValue = DAG.getConstant(1, DL, Op.getValueType());
559-
SDValue FalseValue = DAG.getConstant(0, DL, Op.getValueType());
560-
561-
return DAG.getNode(XtensaISD::SELECT_CC, DL, Ty, LHS, RHS, TrueValue,
562-
FalseValue, TargetCC);
563-
}
564-
565536
SDValue XtensaTargetLowering::LowerImmediate(SDValue Op,
566537
SelectionDAG &DAG) const {
567538
const ConstantSDNode *CN = cast<ConstantSDNode>(Op);
@@ -724,8 +695,6 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
724695
return LowerJumpTable(Op, DAG);
725696
case ISD::ConstantPool:
726697
return LowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
727-
case ISD::SETCC:
728-
return LowerSETCC(Op, DAG);
729698
case ISD::SELECT_CC:
730699
return LowerSELECT_CC(Op, DAG);
731700
case ISD::STACKSAVE:
@@ -749,8 +718,6 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
749718
return "XtensaISD::PCREL_WRAPPER";
750719
case XtensaISD::RET:
751720
return "XtensaISD::RET";
752-
case XtensaISD::SELECT:
753-
return "XtensaISD::SELECT";
754721
case XtensaISD::SELECT_CC:
755722
return "XtensaISD::SELECT_CC";
756723
}
@@ -764,26 +731,18 @@ const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
764731
static int GetBranchKind(int Cond, bool &BrInv) {
765732
switch (Cond) {
766733
case ISD::SETEQ:
767-
case ISD::SETOEQ:
768-
case ISD::SETUEQ:
769734
return Xtensa::BEQ;
770735
case ISD::SETNE:
771-
case ISD::SETONE:
772-
case ISD::SETUNE:
773736
return Xtensa::BNE;
774737
case ISD::SETLT:
775-
case ISD::SETOLT:
776738
return Xtensa::BLT;
777739
case ISD::SETLE:
778-
case ISD::SETOLE:
779740
BrInv = true;
780741
return Xtensa::BGE;
781742
case ISD::SETGT:
782-
case ISD::SETOGT:
783743
BrInv = true;
784744
return Xtensa::BLT;
785745
case ISD::SETGE:
786-
case ISD::SETOGE:
787746
return Xtensa::BGE;
788747
case ISD::SETULT:
789748
return Xtensa::BLTU;

‎llvm/lib/Target/Xtensa/XtensaISelLowering.h

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -35,11 +35,10 @@ enum {
3535
PCREL_WRAPPER,
3636
RET,
3737

38-
// Selects between operand 0 and operand 1. Operand 2 is the
39-
// mask of condition-code values for which operand 0 should be
40-
// chosen over operand 1; it has the same form as BR_CCMASK.
41-
// Operand 3 is the flag operand.
42-
SELECT,
38+
// Select with condition operator - This selects between a true value and
39+
// a false value (ops #2 and #3) based on the boolean result of comparing
40+
// the lhs and rhs (ops #0 and #1) of a conditional expression with the
41+
// condition code in op #4
4342
SELECT_CC
4443
};
4544
}
@@ -104,8 +103,6 @@ class XtensaTargetLowering : public TargetLowering {
104103

105104
SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
106105

107-
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
108-
109106
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
110107

111108
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;

‎llvm/lib/Target/Xtensa/XtensaOperators.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,5 @@ def Xtensa_callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XtensaCallSeqEnd,
4444

4545
def Xtensa_brjt: SDNode<"XtensaISD::BR_JT", SDT_XtensaBrJT, [SDNPHasChain]>;
4646

47-
def Xtensa_select : SDNode<"XtensaISD::SELECT", SDTSelect>;
4847
def Xtensa_select_cc: SDNode<"XtensaISD::SELECT_CC", SDT_XtensaSelectCC,
4948
[SDNPInGlue]>;

‎llvm/test/CodeGen/Xtensa/brcc.ll

Lines changed: 122 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
; RUN: llc -march=xtensa < %s | FileCheck %s
22

3-
; CHECK-LABEL: brcc1:
3+
; CHECK-LABEL: brcc_sgt:
44
; CHECK: bge a3, a2, .LBB0_2
55
; CHECK: addi a2, a2, 4
66
; CHECK: .LBB0_2:
7-
define i32 @brcc1(i32 %a, i32 %b) nounwind {
7+
define i32 @brcc_sgt(i32 %a, i32 %b) nounwind {
88
entry:
99
%wb = icmp sgt i32 %a, %b
1010
br i1 %wb, label %t1, label %t2
@@ -19,11 +19,11 @@ exit:
1919
ret i32 %v
2020
}
2121

22-
; CHECK-LABEL: brcc2
22+
; CHECK-LABEL: brcc_ugt
2323
; CHECK: bgeu a3, a2, .LBB1_2
2424
; CHECK: addi a2, a2, 4
2525
; CHECK: .LBB1_2:
26-
define i32 @brcc2(i32 %a, i32 %b) nounwind {
26+
define i32 @brcc_ugt(i32 %a, i32 %b) nounwind {
2727
entry:
2828
%wb = icmp ugt i32 %a, %b
2929
br i1 %wb, label %t1, label %t2
@@ -38,11 +38,11 @@ exit:
3838
ret i32 %v
3939
}
4040

41-
; CHECK-LABEL: brcc3:
41+
; CHECK-LABEL: brcc_sle:
4242
; CHECK: blt a3, a2, .LBB2_2
4343
; CHECK: addi a2, a2, 4
4444
; CHECK: .LBB2_2:
45-
define i32 @brcc3(i32 %a, i32 %b) nounwind {
45+
define i32 @brcc_sle(i32 %a, i32 %b) nounwind {
4646
entry:
4747
%wb = icmp sle i32 %a, %b
4848
br i1 %wb, label %t1, label %t2
@@ -57,11 +57,11 @@ exit:
5757
ret i32 %v
5858
}
5959

60-
; CHECK-LABEL: brcc4
60+
; CHECK-LABEL: brcc_ule
6161
; CHECK: bltu a3, a2, .LBB3_2
6262
; CHECK: addi a2, a2, 4
6363
; CHECK: .LBB3_2:
64-
define i32 @brcc4(i32 %a, i32 %b) nounwind {
64+
define i32 @brcc_ule(i32 %a, i32 %b) nounwind {
6565
entry:
6666
%wb = icmp ule i32 %a, %b
6767
br i1 %wb, label %t1, label %t2
@@ -75,3 +75,117 @@ exit:
7575
%v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
7676
ret i32 %v
7777
}
78+
79+
; CHECK-LABEL: brcc_eq:
80+
; CHECK: bne a2, a3, .LBB4_2
81+
; CHECK: addi a2, a2, 4
82+
; CHECK: .LBB4_2:
83+
define i32 @brcc_eq(i32 %a, i32 %b) nounwind {
84+
entry:
85+
%wb = icmp eq i32 %a, %b
86+
br i1 %wb, label %t1, label %t2
87+
t1:
88+
%t1v = add i32 %a, 4
89+
br label %exit
90+
t2:
91+
%t2v = add i32 %b, 8
92+
br label %exit
93+
exit:
94+
%v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
95+
ret i32 %v
96+
}
97+
98+
; CHECK-LABEL: brcc_ne:
99+
; CHECK: beq a2, a3, .LBB5_2
100+
; CHECK: addi a2, a2, 4
101+
; CHECK: .LBB5_2:
102+
define i32 @brcc_ne(i32 %a, i32 %b) nounwind {
103+
entry:
104+
%wb = icmp ne i32 %a, %b
105+
br i1 %wb, label %t1, label %t2
106+
t1:
107+
%t1v = add i32 %a, 4
108+
br label %exit
109+
t2:
110+
%t2v = add i32 %b, 8
111+
br label %exit
112+
exit:
113+
%v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
114+
ret i32 %v
115+
}
116+
117+
; CHECK-LABEL: brcc_ge:
118+
; CHECK: blt a2, a3, .LBB6_2
119+
; CHECK: addi a2, a2, 4
120+
; CHECK: .LBB6_2:
121+
define i32 @brcc_ge(i32 %a, i32 %b) nounwind {
122+
entry:
123+
%wb = icmp sge i32 %a, %b
124+
br i1 %wb, label %t1, label %t2
125+
t1:
126+
%t1v = add i32 %a, 4
127+
br label %exit
128+
t2:
129+
%t2v = add i32 %b, 8
130+
br label %exit
131+
exit:
132+
%v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
133+
ret i32 %v
134+
}
135+
136+
; CHECK-LABEL: brcc_lt:
137+
; CHECK: bge a2, a3, .LBB7_2
138+
; CHECK: addi a2, a2, 4
139+
; CHECK: .LBB7_2:
140+
define i32 @brcc_lt(i32 %a, i32 %b) nounwind {
141+
entry:
142+
%wb = icmp slt i32 %a, %b
143+
br i1 %wb, label %t1, label %t2
144+
t1:
145+
%t1v = add i32 %a, 4
146+
br label %exit
147+
t2:
148+
%t2v = add i32 %b, 8
149+
br label %exit
150+
exit:
151+
%v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
152+
ret i32 %v
153+
}
154+
155+
; CHECK-LABEL: brcc_uge:
156+
; CHECK: bltu a2, a3, .LBB8_2
157+
; CHECK: addi a2, a2, 4
158+
; CHECK: .LBB8_2:
159+
define i32 @brcc_uge(i32 %a, i32 %b) nounwind {
160+
entry:
161+
%wb = icmp uge i32 %a, %b
162+
br i1 %wb, label %t1, label %t2
163+
t1:
164+
%t1v = add i32 %a, 4
165+
br label %exit
166+
t2:
167+
%t2v = add i32 %b, 8
168+
br label %exit
169+
exit:
170+
%v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
171+
ret i32 %v
172+
}
173+
174+
; CHECK-LABEL: brcc_ult:
175+
; CHECK: bgeu a2, a3, .LBB9_2
176+
; CHECK: addi a2, a2, 4
177+
; CHECK: .LBB9_2:
178+
define i32 @brcc_ult(i32 %a, i32 %b) nounwind {
179+
entry:
180+
%wb = icmp ult i32 %a, %b
181+
br i1 %wb, label %t1, label %t2
182+
t1:
183+
%t1v = add i32 %a, 4
184+
br label %exit
185+
t2:
186+
%t2v = add i32 %b, 8
187+
br label %exit
188+
exit:
189+
%v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
190+
ret i32 %v
191+
}

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