Skip to content

Commit f2464ca

Browse files
CarolineConcattoCarolineConcatto
authored
[SVE2.1][Clang][LLVM]Int/FP reduce builtin in Clang and LLVM intrinsic (#69926)
This patch implements the builtins in Clang and the LLVM-IR intrinsic for the following: // Variants are also available for: // _s8, _s16, _u16, _s32, _u32, _s64, _u64, // _f16, _f32, _f64uint8x16_t svaddqv[_u8](svbool_t pg, svuint8_t zn); // Variants are also available for: // _s8, _u16, _s16, _u32, _s32, _u64, _s64 uint8x16_t svandqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t sveorqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t svorqv[_u8](svbool_t pg, svuint8_t zn); // Variants are also available for: // _s8, _u16, _s16, _u32, _s32, _u64, _s64; uint8x16_t svmaxqv[_u8](svbool_t pg, svuint8_t zn); uint8x16_t svminqv[_u8](svbool_t pg, svuint8_t zn); // Variants are also available for _f32, _f64 float16x8_t svmaxnmqv[_f16](svbool_t pg, svfloat16_t zn); float16x8_t svminnmqv[_f16](svbool_t pg, svfloat16_t zn); According to the PR#257[1] The reduction instruction uses scalable vectors as input and fixed vectors as output, therefore we changed SVEEmitter to emit fixed vector types in case the neon header(arm_neon.h) is not present. [1]ARM-software/acle#257 Co-author: Dinar Temirbulatov <[email protected]>
1 parent 6892c17 commit f2464ca

File tree

12 files changed

+1691
-18
lines changed

12 files changed

+1691
-18
lines changed

‎clang/include/clang/Basic/TargetBuiltins.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -309,7 +309,7 @@ namespace clang {
309309
bool isTupleSet() const { return Flags & IsTupleSet; }
310310
bool isReadZA() const { return Flags & IsReadZA; }
311311
bool isWriteZA() const { return Flags & IsWriteZA; }
312-
312+
bool isReductionQV() const { return Flags & IsReductionQV; }
313313
uint64_t getBits() const { return Flags; }
314314
bool isFlagSet(uint64_t Flag) const { return Flags & Flag; }
315315
};

‎clang/include/clang/Basic/arm_sve.td

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1946,6 +1946,23 @@ def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, "",
19461946
def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, "", [IsStreamingCompatible], []>;
19471947
}
19481948

1949+
// Standalone sve2.1 builtins
1950+
let TargetGuard = "sve2p1" in {
1951+
def SVORQV : SInst<"svorqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_orqv", [IsReductionQV]>;
1952+
def SVEORQV : SInst<"sveorqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_eorqv", [IsReductionQV]>;
1953+
def SVADDQV : SInst<"svaddqv[_{d}]", "{Pd", "hfdcsilUcUsUiUl", MergeNone, "aarch64_sve_addqv", [IsReductionQV]>;
1954+
def SVANDQV : SInst<"svandqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_andqv", [IsReductionQV]>;
1955+
def SVSMAXQV : SInst<"svmaxqv[_{d}]", "{Pd", "csil", MergeNone, "aarch64_sve_smaxqv", [IsReductionQV]>;
1956+
def SVUMAXQV : SInst<"svmaxqv[_{d}]", "{Pd", "UcUsUiUl", MergeNone, "aarch64_sve_umaxqv", [IsReductionQV]>;
1957+
def SVSMINQV : SInst<"svminqv[_{d}]", "{Pd", "csil", MergeNone, "aarch64_sve_sminqv", [IsReductionQV]>;
1958+
def SVUMINQV : SInst<"svminqv[_{d}]", "{Pd", "UcUsUiUl", MergeNone, "aarch64_sve_uminqv", [IsReductionQV]>;
1959+
1960+
def SVFMAXNMQV: SInst<"svmaxnmqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fmaxnmqv", [IsReductionQV]>;
1961+
def SVFMINNMQV: SInst<"svminnmqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fminnmqv", [IsReductionQV]>;
1962+
def SVFMAXQV: SInst<"svmaxqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fmaxqv", [IsReductionQV]>;
1963+
def SVFMINQV: SInst<"svminqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fminqv", [IsReductionQV]>;
1964+
}
1965+
19491966
let TargetGuard = "sve2p1|sme2" in {
19501967
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when available
19511968
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>;

‎clang/include/clang/Basic/arm_sve_sme_incl.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,7 @@
129129
// Z: const pointer to uint64_t
130130

131131
// Prototype modifiers added for SVE2p1
132+
// {: 128b vector
132133
// }: svcount_t
133134

134135
class MergeType<int val, string suffix=""> {
@@ -225,6 +226,7 @@ def IsSharedZA : FlagType<0x8000000000>;
225226
def IsPreservesZA : FlagType<0x10000000000>;
226227
def IsReadZA : FlagType<0x20000000000>;
227228
def IsWriteZA : FlagType<0x40000000000>;
229+
def IsReductionQV : FlagType<0x80000000000>;
228230

229231
// These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
230232
class ImmCheckType<int val> {

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9985,6 +9985,10 @@ CodeGenFunction::getSVEOverloadTypes(const SVETypeFlags &TypeFlags,
99859985
if (TypeFlags.isOverloadCvt())
99869986
return {Ops[0]->getType(), Ops.back()->getType()};
99879987

9988+
if (TypeFlags.isReductionQV() && !ResultType->isScalableTy() &&
9989+
ResultType->isVectorTy())
9990+
return {ResultType, Ops[1]->getType()};
9991+
99889992
assert(TypeFlags.isOverloadDefault() && "Unexpected value for overloads");
99899993
return {DefaultType};
99909994
}

‎clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c

Lines changed: 285 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,285 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2+
// REQUIRES: aarch64-registered-target
3+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
4+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
5+
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
6+
// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
7+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
8+
#include <arm_neon.h>
9+
#include <arm_sve.h>
10+
11+
#ifdef SVE_OVERLOADED_FORMS
12+
// A simple used,unused... macro, long enough to represent any SVE builtin.
13+
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
14+
#else
15+
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
16+
#endif
17+
18+
// FADDQV
19+
20+
// CHECK-LABEL: @test_svaddqv_f16(
21+
// CHECK-NEXT: entry:
22+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
23+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
24+
// CHECK-NEXT: ret <8 x half> [[TMP1]]
25+
//
26+
// CPP-CHECK-LABEL: @_Z16test_svaddqv_f16u10__SVBool_tu13__SVFloat16_t(
27+
// CPP-CHECK-NEXT: entry:
28+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
29+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
30+
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]]
31+
//
32+
float16x8_t test_svaddqv_f16(svbool_t pg, svfloat16_t op)
33+
{
34+
return SVE_ACLE_FUNC(svaddqv,,_f16,)(pg, op);
35+
}
36+
37+
// CHECK-LABEL: @test_svaddqv_f32(
38+
// CHECK-NEXT: entry:
39+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
40+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
41+
// CHECK-NEXT: ret <4 x float> [[TMP1]]
42+
//
43+
// CPP-CHECK-LABEL: @_Z16test_svaddqv_f32u10__SVBool_tu13__SVFloat32_t(
44+
// CPP-CHECK-NEXT: entry:
45+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
46+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
47+
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]]
48+
//
49+
float32x4_t test_svaddqv_f32(svbool_t pg, svfloat32_t op)
50+
{
51+
return SVE_ACLE_FUNC(svaddqv,,_f32,)(pg, op);
52+
}
53+
54+
// CHECK-LABEL: @test_svaddqv_f64(
55+
// CHECK-NEXT: entry:
56+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
57+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
58+
// CHECK-NEXT: ret <2 x double> [[TMP1]]
59+
//
60+
// CPP-CHECK-LABEL: @_Z16test_svaddqv_f64u10__SVBool_tu13__SVFloat64_t(
61+
// CPP-CHECK-NEXT: entry:
62+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
63+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
64+
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]]
65+
//
66+
float64x2_t test_svaddqv_f64(svbool_t pg, svfloat64_t op)
67+
{
68+
return SVE_ACLE_FUNC(svaddqv,,_f64,)(pg, op);
69+
}
70+
71+
72+
// FMAXQV
73+
74+
// CHECK-LABEL: @test_svmaxqv_f16(
75+
// CHECK-NEXT: entry:
76+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
77+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
78+
// CHECK-NEXT: ret <8 x half> [[TMP1]]
79+
//
80+
// CPP-CHECK-LABEL: @_Z16test_svmaxqv_f16u10__SVBool_tu13__SVFloat16_t(
81+
// CPP-CHECK-NEXT: entry:
82+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
83+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
84+
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]]
85+
//
86+
float16x8_t test_svmaxqv_f16(svbool_t pg, svfloat16_t op)
87+
{
88+
return SVE_ACLE_FUNC(svmaxqv,,_f16,)(pg, op);
89+
}
90+
91+
// CHECK-LABEL: @test_svmaxqv_f32(
92+
// CHECK-NEXT: entry:
93+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
94+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
95+
// CHECK-NEXT: ret <4 x float> [[TMP1]]
96+
//
97+
// CPP-CHECK-LABEL: @_Z16test_svmaxqv_f32u10__SVBool_tu13__SVFloat32_t(
98+
// CPP-CHECK-NEXT: entry:
99+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
100+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
101+
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]]
102+
//
103+
float32x4_t test_svmaxqv_f32(svbool_t pg, svfloat32_t op)
104+
{
105+
return SVE_ACLE_FUNC(svmaxqv,,_f32,)(pg, op);
106+
}
107+
108+
// CHECK-LABEL: @test_svmaxqv_f64(
109+
// CHECK-NEXT: entry:
110+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
111+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
112+
// CHECK-NEXT: ret <2 x double> [[TMP1]]
113+
//
114+
// CPP-CHECK-LABEL: @_Z16test_svmaxqv_f64u10__SVBool_tu13__SVFloat64_t(
115+
// CPP-CHECK-NEXT: entry:
116+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
117+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
118+
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]]
119+
//
120+
float64x2_t test_svmaxqv_f64(svbool_t pg, svfloat64_t op)
121+
{
122+
return SVE_ACLE_FUNC(svmaxqv,,_f64,)(pg, op);
123+
}
124+
125+
126+
// FMINQV
127+
128+
// CHECK-LABEL: @test_svminqv_f16(
129+
// CHECK-NEXT: entry:
130+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
131+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
132+
// CHECK-NEXT: ret <8 x half> [[TMP1]]
133+
//
134+
// CPP-CHECK-LABEL: @_Z16test_svminqv_f16u10__SVBool_tu13__SVFloat16_t(
135+
// CPP-CHECK-NEXT: entry:
136+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
137+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
138+
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]]
139+
//
140+
float16x8_t test_svminqv_f16(svbool_t pg, svfloat16_t op)
141+
{
142+
return SVE_ACLE_FUNC(svminqv,,_f16,)(pg, op);
143+
}
144+
145+
// CHECK-LABEL: @test_svminqv_f32(
146+
// CHECK-NEXT: entry:
147+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
148+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
149+
// CHECK-NEXT: ret <4 x float> [[TMP1]]
150+
//
151+
// CPP-CHECK-LABEL: @_Z16test_svminqv_f32u10__SVBool_tu13__SVFloat32_t(
152+
// CPP-CHECK-NEXT: entry:
153+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
154+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
155+
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]]
156+
//
157+
float32x4_t test_svminqv_f32(svbool_t pg, svfloat32_t op)
158+
{
159+
return SVE_ACLE_FUNC(svminqv,,_f32,)(pg, op);
160+
}
161+
162+
// CHECK-LABEL: @test_svminqv_f64(
163+
// CHECK-NEXT: entry:
164+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
165+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
166+
// CHECK-NEXT: ret <2 x double> [[TMP1]]
167+
//
168+
// CPP-CHECK-LABEL: @_Z16test_svminqv_f64u10__SVBool_tu13__SVFloat64_t(
169+
// CPP-CHECK-NEXT: entry:
170+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
171+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
172+
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]]
173+
//
174+
float64x2_t test_svminqv_f64(svbool_t pg, svfloat64_t op)
175+
{
176+
return SVE_ACLE_FUNC(svminqv,,_f64,)(pg, op);
177+
}
178+
179+
180+
// FMAXNMQV
181+
182+
// CHECK-LABEL: @test_svmaxnmqv_f16(
183+
// CHECK-NEXT: entry:
184+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
185+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
186+
// CHECK-NEXT: ret <8 x half> [[TMP1]]
187+
//
188+
// CPP-CHECK-LABEL: @_Z18test_svmaxnmqv_f16u10__SVBool_tu13__SVFloat16_t(
189+
// CPP-CHECK-NEXT: entry:
190+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
191+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
192+
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]]
193+
//
194+
float16x8_t test_svmaxnmqv_f16(svbool_t pg, svfloat16_t op)
195+
{
196+
return SVE_ACLE_FUNC(svmaxnmqv,,_f16,)(pg, op);
197+
}
198+
199+
// CHECK-LABEL: @test_svmaxnmqv_f32(
200+
// CHECK-NEXT: entry:
201+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
202+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
203+
// CHECK-NEXT: ret <4 x float> [[TMP1]]
204+
//
205+
// CPP-CHECK-LABEL: @_Z18test_svmaxnmqv_f32u10__SVBool_tu13__SVFloat32_t(
206+
// CPP-CHECK-NEXT: entry:
207+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
208+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
209+
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]]
210+
//
211+
float32x4_t test_svmaxnmqv_f32(svbool_t pg, svfloat32_t op)
212+
{
213+
return SVE_ACLE_FUNC(svmaxnmqv,,_f32,)(pg, op);
214+
}
215+
216+
// CHECK-LABEL: @test_svmaxnmqv_f64(
217+
// CHECK-NEXT: entry:
218+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
219+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
220+
// CHECK-NEXT: ret <2 x double> [[TMP1]]
221+
//
222+
// CPP-CHECK-LABEL: @_Z18test_svmaxnmqv_f64u10__SVBool_tu13__SVFloat64_t(
223+
// CPP-CHECK-NEXT: entry:
224+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
225+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
226+
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]]
227+
//
228+
float64x2_t test_svmaxnmqv_f64(svbool_t pg, svfloat64_t op)
229+
{
230+
return SVE_ACLE_FUNC(svmaxnmqv,,_f64,)(pg, op);
231+
}
232+
233+
234+
// FMINNMQV
235+
236+
// CHECK-LABEL: @test_svminnmqv_f16(
237+
// CHECK-NEXT: entry:
238+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
239+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
240+
// CHECK-NEXT: ret <8 x half> [[TMP1]]
241+
//
242+
// CPP-CHECK-LABEL: @_Z18test_svminnmqv_f16u10__SVBool_tu13__SVFloat16_t(
243+
// CPP-CHECK-NEXT: entry:
244+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
245+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]])
246+
// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]]
247+
//
248+
float16x8_t test_svminnmqv_f16(svbool_t pg, svfloat16_t op)
249+
{
250+
return SVE_ACLE_FUNC(svminnmqv,,_f16,)(pg, op);
251+
}
252+
253+
// CHECK-LABEL: @test_svminnmqv_f32(
254+
// CHECK-NEXT: entry:
255+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
256+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
257+
// CHECK-NEXT: ret <4 x float> [[TMP1]]
258+
//
259+
// CPP-CHECK-LABEL: @_Z18test_svminnmqv_f32u10__SVBool_tu13__SVFloat32_t(
260+
// CPP-CHECK-NEXT: entry:
261+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
262+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]])
263+
// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]]
264+
//
265+
float32x4_t test_svminnmqv_f32(svbool_t pg, svfloat32_t op)
266+
{
267+
return SVE_ACLE_FUNC(svminnmqv,,_f32,)(pg, op);
268+
}
269+
270+
// CHECK-LABEL: @test_svminnmqv_f64(
271+
// CHECK-NEXT: entry:
272+
// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
273+
// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
274+
// CHECK-NEXT: ret <2 x double> [[TMP1]]
275+
//
276+
// CPP-CHECK-LABEL: @_Z18test_svminnmqv_f64u10__SVBool_tu13__SVFloat64_t(
277+
// CPP-CHECK-NEXT: entry:
278+
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
279+
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]])
280+
// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]]
281+
//
282+
float64x2_t test_svminnmqv_f64(svbool_t pg, svfloat64_t op)
283+
{
284+
return SVE_ACLE_FUNC(svminnmqv,,_f64,)(pg, op);
285+
}

0 commit comments

Comments
 (0)