[X86] Better scheduling/selection of the LEA instruction

[RKSimon]

Bugzilla Link	32326
Version	trunk
OS	Windows NT
Blocks	#31672
CC	@adibiagio,@chriselrod,@gchatelet,@hfinkel,@rotateright,@ZviRackover

Extended Description

Some basic forms of the LEA instruction (2 source operands, no scale etc.) can typically be performed on the cpu's generic ALUs whilst the complex forms (3 source operands, scale + offset etc.) can only be performed on a cpus's AGUs.

We need to better tag the different LEA instructions so that we can discriminate in the scheduler model and compare them against other memory address instructions.

We should then be able to improve LEA pattern selection in the machine combiner (balance ALU/AGU usage, use multi stage LEAs for simple integer multiplies etc.).

[RKSimon]

Ping - Hopefully llvm-mca + variants can help us sort this one out and llvm-exegesis can test it.

[adibiagio]

Ping - Hopefully llvm-mca + variants can help us sort this one out and
llvm-exegesis can test it.

This has been fixed for BtVer2 only, at revision 337469
http://llvm.org/viewvc/llvm-project?view=revision&revision=337469

It should be easy to use schedule 'write variant' definitions to model the latency/throughput of LEA on other X86 processors.