| | | | --- | --- | | Bugzilla Link | [35675](https://llvm.org/bz35675) | | Resolution | FIXED | | Resolved on | Feb 06, 2020 10:50 | | Version | trunk | | OS | All | | Depends On | llvm/llvm-project#36254 | | Blocks | llvm/llvm-project#31672 | | CC | @legrosbuffle,@gchatelet,@RKSimon | | Fixed by commit(s) | c6bdd8e73110e14dc54833137cecef9c07d2dc24 | ## Extended Description I have trouble believing that 0 microops and no port binding is correct for these. def SKXWriteResGroup214 : SchedWriteRes<[]> { let Latency = 20; let NumMicroOps = 0; } def: InstRW<[SKXWriteResGroup214], (instregex "VGATHERDPSZ128rm")>; def: InstRW<[SKXWriteResGroup214], (instregex "VGATHERQPSZrm")>; def: InstRW<[SKXWriteResGroup214], (instregex "VPGATHERDDZ128rm")>;