[RISCV] [Relax] J instr is not relaxed to auipc + jalr in RISCVAsmBackend which is not handled before in BranchRelax Pass

[zixuan-wu]

getInstSizeInBytes estimate the size of compressed instruction incorrectly because the instructions between the branchrelax source and target may be relaxed in assembler later. In such case, unconditional jump(J instr) would be kept to assembler without being handled in BranchRelax Pass. But in the end, target addresss of J instr is out of range.

unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {

...

if (MI.getParent() && MI.getParent()->getParent()) {
    if (isCompressibleInst(MI, STI))
      return 2;
 }
...

So it also needs to relax J/JAL in assembler to fix up the output of branchrelax process.

[llvmbot]

@llvm/issue-subscribers-bug

Author: Zi Xuan Wu (Zeson) (zixuan-wu)

```

if (MI.getParent() && MI.getParent()->getParent()) {
if (isCompressibleInst(MI, STI))
return 2;
}

Because the compressed instruction can be relaxed in assembler later, so is this right to estimate the size of compressed instruction?
</details>

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Zi Xuan Wu (Zeson) (zixuan-wu)

```

if (MI.getParent() && MI.getParent()->getParent()) {
if (isCompressibleInst(MI, STI))
return 2;
}

Because the compressed instruction can be relaxed in assembler later, so is this right to estimate the size of compressed instruction?
</details>

[topperc]

This ticket #56448 says we over estimate the size of branch instructions in getInstSizeInBytes.

[topperc]

So it also needs to relax J/JAL in assembler to fix up the output of branchrelax process.

This isn't possible because its need a temporary register.

[zixuan-wu]

This ticket #56448 says we over estimate the size of branch instructions in getInstSizeInBytes.

What do you mean? Is it a known issue which has't been fixed?

[topperc]

This ticket #56448 says we over estimate the size of branch instructions in getInstSizeInBytes.

What do you mean? Is it a known issue which has't been fixed?

According to #56448, isCompressibleInst returns false for compressed branches in getInstSizeInBytes. So we should be counting branched instructions as 4 bytes during branch relaxation.

The only instructions that should be relaxed during assembler should be compressed branches/jumps to uncompressed branches/jumpes. Everything else should be relaxed by BranchRelaxation.

So the bug in this ticket shouldn't be possible.

[zixuan-wu]

Is it the order that compressing instruction to compressed instruction before relaxing the compressed instruction to uncompressed instruction?

J DstJ (1)
...
BEQ DstBEQ (2)
...
DstJ:
...
DstBEQ:

For example, In BranchRelaxtion Pass, (2) is predicated as compressed instruction, but it's uncompressed in assembler phase. So it influences the offset calculation of (1). In the end, (1) would be out of range in linker phase.