diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index 194ce7c10bfd3..bf4d974329de3 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -102,6 +102,7 @@ class SPIRVPassConfig : public TargetPassConfig { SPIRVTargetMachine &getSPIRVTargetMachine() const { return getTM(); } + void addMachineSSAOptimization() override; void addIRPasses() override; void addISelPrepare() override; @@ -129,6 +130,16 @@ FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) { return nullptr; } +// Disable passes that may break CFG. +void SPIRVPassConfig::addMachineSSAOptimization() { + // Some standard passes that optimize machine instructions in SSA form uses + // MI.isPHI() that doesn't account for OpPhi in SPIR-V and so are able to + // break the CFG (e.g., MachineSink). + disablePass(&MachineSinkingID); + + TargetPassConfig::addMachineSSAOptimization(); +} + // Disable passes that break from assuming no virtual registers exist. void SPIRVPassConfig::addPostRegAlloc() { // Do not work with vregs instead of physical regs.