From ab5ed10733ba527350621a88068e958a72c04f1b Mon Sep 17 00:00:00 2001 From: easyonaadit Date: Fri, 13 Dec 2024 18:28:18 +0530 Subject: [PATCH 1/2] assert if stack grows upwards --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 4 ++-- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 8 +++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index e5baffc0f064b..72c3e4a64c18b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -1181,8 +1181,8 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc( // Guard in case the stack growth direction ever changes with scratch // instructions. - if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown) - return false; + assert(TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp && + "Stack grows upwards for AMDGPU\n"); Register Dst = MI.getOperand(0).getReg(); Register AllocSize = MI.getOperand(1).getReg(); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 8dfebd36a962e..9366cb31640f9 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -4041,17 +4041,15 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op, Chain = SP.getValue(1); MaybeAlign Alignment = cast(Tmp3)->getMaybeAlignValue(); const TargetFrameLowering *TFL = Subtarget->getFrameLowering(); - unsigned Opc = - TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp - ? ISD::ADD - : ISD::SUB; + assert(TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp && + "Stack grows upwards for AMDGPU\n"); SDValue ScaledSize = DAG.getNode( ISD::SHL, dl, VT, Size, DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32)); Align StackAlign = TFL->getStackAlign(); - Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value + Tmp1 = DAG.getNode(ISD::ADD, dl, VT, SP, ScaledSize); // Value if (Alignment && *Alignment > StackAlign) { Tmp1 = DAG.getNode( ISD::AND, dl, VT, Tmp1, From f7f11a82a91aa7110287b3a646ce83a7560bf90e Mon Sep 17 00:00:00 2001 From: easyonaadit Date: Sat, 14 Dec 2024 11:40:56 +0530 Subject: [PATCH 2/2] review comments --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 72c3e4a64c18b..6e1f188bb3d3d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -1182,7 +1182,7 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc( // Guard in case the stack growth direction ever changes with scratch // instructions. assert(TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp && - "Stack grows upwards for AMDGPU\n"); + "Stack grows upwards for AMDGPU"); Register Dst = MI.getOperand(0).getReg(); Register AllocSize = MI.getOperand(1).getReg(); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 9366cb31640f9..7da93f90341d2 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -4042,7 +4042,7 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op, MaybeAlign Alignment = cast(Tmp3)->getMaybeAlignValue(); const TargetFrameLowering *TFL = Subtarget->getFrameLowering(); assert(TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp && - "Stack grows upwards for AMDGPU\n"); + "Stack grows upwards for AMDGPU"); SDValue ScaledSize = DAG.getNode( ISD::SHL, dl, VT, Size,