diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index 9a3b82fe57c12..6aff0ad899421 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -1505,24 +1505,23 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) { CInst->getDebugLoc()); }) .Case( - [&](VPWidenCastRecipe *CInst) -> VPRecipeBase * { - auto *CI = dyn_cast(CInst->getUnderlyingInstr()); + [&](VPWidenCastRecipe *CastR) -> VPRecipeBase * { Intrinsic::ID VPID = - VPIntrinsic::getForOpcode(CI->getOpcode()); + VPIntrinsic::getForOpcode(CastR->getOpcode()); assert(VPID != Intrinsic::not_intrinsic && "Expected vp.casts Instrinsic"); - SmallVector Ops(CInst->operands()); + SmallVector Ops(CastR->operands()); assert(VPIntrinsic::getMaskParamPos(VPID) && VPIntrinsic::getVectorLengthParamPos(VPID) && "Expected VP intrinsic"); - VPValue *Mask = Plan.getOrAddLiveIn(ConstantInt::getTrue( - IntegerType::getInt1Ty(CI->getContext()))); + VPValue *Mask = + Plan.getOrAddLiveIn(ConstantInt::getTrue(Ctx)); Ops.push_back(Mask); Ops.push_back(&EVL); return new VPWidenIntrinsicRecipe( - VPID, Ops, TypeInfo.inferScalarType(CInst), - CInst->getDebugLoc()); + VPID, Ops, TypeInfo.inferScalarType(CastR), + CastR->getDebugLoc()); }) .Case([&](VPWidenSelectRecipe *Sel) { SmallVector Ops(Sel->operands()); diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll new file mode 100644 index 0000000000000..68b36f23de4b0 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll @@ -0,0 +1,84 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -passes=loop-vectorize -force-tail-folding-style=data-with-evl -prefer-predicate-over-epilogue=predicate-dont-vectorize -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s + +; Make sure we don't crash when transforming a VPWidenCastRecipe created without +; an underlying value to an EVL recipe. This occurs in this test via +; VPlanTransforms::truncateToMinimalBitwidths + +define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr %src) { +; CHECK-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe( +; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], 1 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 2, [[TMP1]] +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP0]] +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[AVL:%.*]] = sub i64 2, [[EVL_BASED_IV]] +; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 1, i1 true) +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[EVL_BASED_IV]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i32 0 +; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call @llvm.vp.load.nxv1i8.p0(ptr align 1 [[TMP6]], splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[TMP7:%.*]] = call @llvm.vp.zext.nxv1i16.nxv1i8( [[VP_OP_LOAD]], splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[VP_OP:%.*]] = call @llvm.vp.mul.nxv1i16( zeroinitializer, [[TMP7]], splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[VP_OP1:%.*]] = call @llvm.vp.lshr.nxv1i16( [[VP_OP]], trunc ( splat (i32 1) to ), splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[TMP8:%.*]] = call @llvm.vp.trunc.nxv1i8.nxv1i16( [[VP_OP1]], splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: call void @llvm.vp.scatter.nxv1i8.nxv1p0( [[TMP8]], align 1 zeroinitializer, splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP3]] to i64 +; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP9]], [[EVL_BASED_IV]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP2]] +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]] +; CHECK: [[SCALAR_PH]]: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]] +; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[GEP_SRC]], align 1 +; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP11]] to i32 +; CHECK-NEXT: [[MUL16:%.*]] = mul i32 0, [[CONV]] +; CHECK-NEXT: [[SHR35:%.*]] = lshr i32 [[MUL16]], 1 +; CHECK-NEXT: [[CONV36:%.*]] = trunc i32 [[SHR35]] to i8 +; CHECK-NEXT: store i8 [[CONV36]], ptr null, align 1 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1 +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: ; preds = %loop, %entry + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.src = getelementptr i8, ptr %src, i64 %iv + %0 = load i8, ptr %gep.src, align 1 + %conv = zext i8 %0 to i32 + %mul16 = mul i32 0, %conv + %shr35 = lshr i32 %mul16, 1 + %conv36 = trunc i32 %shr35 to i8 + store i8 %conv36, ptr null, align 1 + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, 1 + br i1 %ec, label %exit, label %loop + +exit: ; preds = %loop + ret void +} +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +;.