From 1634aaf401c82eb738091c59496cb290b741c154 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 17 Dec 2024 15:15:33 +0800 Subject: [PATCH 1/6] [VPlan] Handle VPWidenCastRecipe without underlying value in EVL transform This fixes a crash that shows up when building SPEC CPU 2017 with EVL tail folding on RISC-V. A VPWidenCastRecipe doesn't always have an underlying value, and in the case of this crash this happens whenever a widened cast is created via truncateToMinimalBitwidths. Fix this by just using the opcode stored in the recipe itself. I think a similar issue exists with VPWidenIntrinsicRecipe and how it's widened, but I haven't run into any crashes with it just yet. --- .../Transforms/Vectorize/VPlanTransforms.cpp | 7 +- ...ize-force-tail-with-evl-cast-intrinsics.ll | 121 ++++++++++++++++++ 2 files changed, 124 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index 9a3b82fe57c12..066232775e46a 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -1506,9 +1506,8 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) { }) .Case( [&](VPWidenCastRecipe *CInst) -> VPRecipeBase * { - auto *CI = dyn_cast(CInst->getUnderlyingInstr()); Intrinsic::ID VPID = - VPIntrinsic::getForOpcode(CI->getOpcode()); + VPIntrinsic::getForOpcode(CInst->getOpcode()); assert(VPID != Intrinsic::not_intrinsic && "Expected vp.casts Instrinsic"); @@ -1516,8 +1515,8 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) { assert(VPIntrinsic::getMaskParamPos(VPID) && VPIntrinsic::getVectorLengthParamPos(VPID) && "Expected VP intrinsic"); - VPValue *Mask = Plan.getOrAddLiveIn(ConstantInt::getTrue( - IntegerType::getInt1Ty(CI->getContext()))); + VPValue *Mask = Plan.getOrAddLiveIn( + ConstantInt::getTrue(IntegerType::getInt1Ty(Ctx))); Ops.push_back(Mask); Ops.push_back(&EVL); return new VPWidenIntrinsicRecipe( diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll index 4557e95f1e1b6..48f9cec34d974 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll @@ -1058,6 +1058,125 @@ loop: exit: ret void } + +define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr noalias %dst, ptr noalias %src, i32 %mvx) { +; IF-EVL-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe( +; IF-EVL-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i32 [[MVX:%.*]]) #[[ATTR0]] { +; IF-EVL-NEXT: [[ENTRY:.*:]] +; IF-EVL-NEXT: [[CMP111:%.*]] = icmp sgt i32 [[MVX]], 0 +; IF-EVL-NEXT: br i1 [[CMP111]], label %[[FOR_BODY13_PREHEADER:.*]], label %[[FOR_COND_CLEANUP12:.*]] +; IF-EVL: [[FOR_BODY13_PREHEADER]]: +; IF-EVL-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[MVX]] to i64 +; IF-EVL-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; IF-EVL: [[VECTOR_PH]]: +; IF-EVL-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; IF-EVL-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 16 +; IF-EVL-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], 1 +; IF-EVL-NEXT: [[N_RND_UP:%.*]] = add i64 [[WIDE_TRIP_COUNT]], [[TMP2]] +; IF-EVL-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP1]] +; IF-EVL-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; IF-EVL-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() +; IF-EVL-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 16 +; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i32 [[MVX]], i64 0 +; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer +; IF-EVL-NEXT: [[TMP5:%.*]] = trunc [[BROADCAST_SPLAT]] to +; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement poison, ptr [[DST]], i64 0 +; IF-EVL-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector [[BROADCAST_SPLATINSERT2]], poison, zeroinitializer +; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]] +; IF-EVL: [[VECTOR_BODY]]: +; IF-EVL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ] +; IF-EVL-NEXT: [[AVL:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[EVL_BASED_IV]] +; IF-EVL-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 16, i1 true) +; IF-EVL-NEXT: [[TMP7:%.*]] = add i64 [[EVL_BASED_IV]], 0 +; IF-EVL-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP7]] +; IF-EVL-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP8]], i32 0 +; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call @llvm.vp.load.nxv16i8.p0(ptr align 1 [[TMP9]], splat (i1 true), i32 [[TMP6]]) +; IF-EVL-NEXT: [[TMP10:%.*]] = call @llvm.vp.zext.nxv16i16.nxv16i8( [[VP_OP_LOAD]], splat (i1 true), i32 [[TMP6]]) +; IF-EVL-NEXT: [[VP_OP:%.*]] = call @llvm.vp.mul.nxv16i16( [[TMP5]], [[TMP10]], splat (i1 true), i32 [[TMP6]]) +; IF-EVL-NEXT: [[VP_OP1:%.*]] = call @llvm.vp.lshr.nxv16i16( [[VP_OP]], trunc ( splat (i32 1) to ), splat (i1 true), i32 [[TMP6]]) +; IF-EVL-NEXT: [[TMP11:%.*]] = call @llvm.vp.trunc.nxv16i8.nxv16i16( [[VP_OP1]], splat (i1 true), i32 [[TMP6]]) +; IF-EVL-NEXT: call void @llvm.vp.scatter.nxv16i8.nxv16p0( [[TMP11]], align 1 [[BROADCAST_SPLAT3]], splat (i1 true), i32 [[TMP6]]) +; IF-EVL-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i64 +; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP12]], [[EVL_BASED_IV]] +; IF-EVL-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP4]] +; IF-EVL-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; IF-EVL-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP47:![0-9]+]] +; IF-EVL: [[MIDDLE_BLOCK]]: +; IF-EVL-NEXT: br i1 true, label %[[FOR_COND_CLEANUP12_LOOPEXIT:.*]], label %[[SCALAR_PH]] +; IF-EVL: [[SCALAR_PH]]: +; IF-EVL-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY13_PREHEADER]] ] +; IF-EVL-NEXT: br label %[[FOR_BODY13:.*]] +; IF-EVL: [[FOR_COND_CLEANUP12_LOOPEXIT]]: +; IF-EVL-NEXT: br label %[[FOR_COND_CLEANUP12]] +; IF-EVL: [[FOR_COND_CLEANUP12]]: +; IF-EVL-NEXT: ret void +; IF-EVL: [[FOR_BODY13]]: +; IF-EVL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY13]] ] +; IF-EVL-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDVARS_IV]] +; IF-EVL-NEXT: [[TMP14:%.*]] = load i8, ptr [[ARRAYIDX15]], align 1 +; IF-EVL-NEXT: [[CONV:%.*]] = zext i8 [[TMP14]] to i32 +; IF-EVL-NEXT: [[MUL16:%.*]] = mul i32 [[MVX]], [[CONV]] +; IF-EVL-NEXT: [[SHR35:%.*]] = lshr i32 [[MUL16]], 1 +; IF-EVL-NEXT: [[CONV36:%.*]] = trunc i32 [[SHR35]] to i8 +; IF-EVL-NEXT: store i8 [[CONV36]], ptr [[DST]], align 1 +; IF-EVL-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 +; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] +; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP12_LOOPEXIT]], label %[[FOR_BODY13]], !llvm.loop [[LOOP48:![0-9]+]] +; +; NO-VP-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe( +; NO-VP-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i32 [[MVX:%.*]]) #[[ATTR0]] { +; NO-VP-NEXT: [[ENTRY:.*:]] +; NO-VP-NEXT: [[CMP111:%.*]] = icmp sgt i32 [[MVX]], 0 +; NO-VP-NEXT: br i1 [[CMP111]], label %[[FOR_BODY13_PREHEADER:.*]], label %[[FOR_COND_CLEANUP12:.*]] +; NO-VP: [[FOR_BODY13_PREHEADER]]: +; NO-VP-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[MVX]] to i64 +; NO-VP-NEXT: br label %[[FOR_BODY13:.*]] +; NO-VP: [[FOR_COND_CLEANUP12_LOOPEXIT:.*]]: +; NO-VP-NEXT: br label %[[FOR_COND_CLEANUP12]] +; NO-VP: [[FOR_COND_CLEANUP12]]: +; NO-VP-NEXT: ret void +; NO-VP: [[FOR_BODY13]]: +; NO-VP-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[FOR_BODY13_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY13]] ] +; NO-VP-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDVARS_IV]] +; NO-VP-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX15]], align 1 +; NO-VP-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 +; NO-VP-NEXT: [[MUL16:%.*]] = mul i32 [[MVX]], [[CONV]] +; NO-VP-NEXT: [[SHR35:%.*]] = lshr i32 [[MUL16]], 1 +; NO-VP-NEXT: [[CONV36:%.*]] = trunc i32 [[SHR35]] to i8 +; NO-VP-NEXT: store i8 [[CONV36]], ptr [[DST]], align 1 +; NO-VP-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 +; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] +; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP12_LOOPEXIT]], label %[[FOR_BODY13]] +; +entry: + %cmp111 = icmp sgt i32 %mvx, 0 + br i1 %cmp111, label %for.body13.preheader, label %for.cond.cleanup12 + +for.body13.preheader: ; preds = %entry + %wide.trip.count = zext nneg i32 %mvx to i64 + br label %for.body13 + +for.cond.cleanup12.loopexit: ; preds = %for.body13 + br label %for.cond.cleanup12 + +for.cond.cleanup12: ; preds = %for.cond.cleanup12.loopexit, %entry + ret void + +for.body13: ; preds = %for.body13.preheader, %for.body13 + %indvars.iv = phi i64 [ 0, %for.body13.preheader ], [ %indvars.iv.next, %for.body13 ] + %arrayidx15 = getelementptr i8, ptr %src, i64 %indvars.iv + %0 = load i8, ptr %arrayidx15, align 1 + %conv = zext i8 %0 to i32 + %mul16 = mul i32 %mvx, %conv + %shr35 = lshr i32 %mul16, 1 + %conv36 = trunc i32 %shr35 to i8 + store i8 %conv36, ptr %dst, align 1 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count + br i1 %exitcond.not, label %for.cond.cleanup12.loopexit, label %for.body13 +} + ;. ; IF-EVL: [[META0]] = !{[[META1:![0-9]+]]} ; IF-EVL: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]} @@ -1106,4 +1225,6 @@ exit: ; IF-EVL: [[LOOP44]] = distinct !{[[LOOP44]], [[META6]]} ; IF-EVL: [[LOOP45]] = distinct !{[[LOOP45]], [[META6]], [[META7]]} ; IF-EVL: [[LOOP46]] = distinct !{[[LOOP46]], [[META6]]} +; IF-EVL: [[LOOP47]] = distinct !{[[LOOP47]], [[META6]], [[META7]]} +; IF-EVL: [[LOOP48]] = distinct !{[[LOOP48]], [[META7]], [[META6]]} ;. From 6dd9322f3b7865e46e0b1cdaf5d9b97c2e0b09d6 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 17 Dec 2024 16:00:00 +0800 Subject: [PATCH 2/6] Remove redundant IntegerType::get, remove redundant block in tests --- .../Transforms/Vectorize/VPlanTransforms.cpp | 4 +-- ...ize-force-tail-with-evl-cast-intrinsics.ll | 29 +++++++++---------- 2 files changed, 15 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index 066232775e46a..85931a9d95a85 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -1515,8 +1515,8 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) { assert(VPIntrinsic::getMaskParamPos(VPID) && VPIntrinsic::getVectorLengthParamPos(VPID) && "Expected VP intrinsic"); - VPValue *Mask = Plan.getOrAddLiveIn( - ConstantInt::getTrue(IntegerType::getInt1Ty(Ctx))); + VPValue *Mask = + Plan.getOrAddLiveIn(ConstantInt::getTrue(Ctx)); Ops.push_back(Mask); Ops.push_back(&EVL); return new VPWidenIntrinsicRecipe( diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll index 48f9cec34d974..3f4f8b60d45d6 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll @@ -1107,10 +1107,6 @@ define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr noalias %dst, p ; IF-EVL: [[SCALAR_PH]]: ; IF-EVL-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY13_PREHEADER]] ] ; IF-EVL-NEXT: br label %[[FOR_BODY13:.*]] -; IF-EVL: [[FOR_COND_CLEANUP12_LOOPEXIT]]: -; IF-EVL-NEXT: br label %[[FOR_COND_CLEANUP12]] -; IF-EVL: [[FOR_COND_CLEANUP12]]: -; IF-EVL-NEXT: ret void ; IF-EVL: [[FOR_BODY13]]: ; IF-EVL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY13]] ] ; IF-EVL-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDVARS_IV]] @@ -1123,6 +1119,10 @@ define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr noalias %dst, p ; IF-EVL-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] ; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP12_LOOPEXIT]], label %[[FOR_BODY13]], !llvm.loop [[LOOP48:![0-9]+]] +; IF-EVL: [[FOR_COND_CLEANUP12_LOOPEXIT]]: +; IF-EVL-NEXT: br label %[[FOR_COND_CLEANUP12]] +; IF-EVL: [[FOR_COND_CLEANUP12]]: +; IF-EVL-NEXT: ret void ; ; NO-VP-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe( ; NO-VP-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i32 [[MVX:%.*]]) #[[ATTR0]] { @@ -1132,10 +1132,6 @@ define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr noalias %dst, p ; NO-VP: [[FOR_BODY13_PREHEADER]]: ; NO-VP-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[MVX]] to i64 ; NO-VP-NEXT: br label %[[FOR_BODY13:.*]] -; NO-VP: [[FOR_COND_CLEANUP12_LOOPEXIT:.*]]: -; NO-VP-NEXT: br label %[[FOR_COND_CLEANUP12]] -; NO-VP: [[FOR_COND_CLEANUP12]]: -; NO-VP-NEXT: ret void ; NO-VP: [[FOR_BODY13]]: ; NO-VP-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[FOR_BODY13_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY13]] ] ; NO-VP-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDVARS_IV]] @@ -1147,7 +1143,11 @@ define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr noalias %dst, p ; NO-VP-NEXT: store i8 [[CONV36]], ptr [[DST]], align 1 ; NO-VP-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] -; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP12_LOOPEXIT]], label %[[FOR_BODY13]] +; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP12_LOOPEXIT:.*]], label %[[FOR_BODY13]] +; NO-VP: [[FOR_COND_CLEANUP12_LOOPEXIT]]: +; NO-VP-NEXT: br label %[[FOR_COND_CLEANUP12]] +; NO-VP: [[FOR_COND_CLEANUP12]]: +; NO-VP-NEXT: ret void ; entry: %cmp111 = icmp sgt i32 %mvx, 0 @@ -1157,12 +1157,6 @@ for.body13.preheader: ; preds = %entry %wide.trip.count = zext nneg i32 %mvx to i64 br label %for.body13 -for.cond.cleanup12.loopexit: ; preds = %for.body13 - br label %for.cond.cleanup12 - -for.cond.cleanup12: ; preds = %for.cond.cleanup12.loopexit, %entry - ret void - for.body13: ; preds = %for.body13.preheader, %for.body13 %indvars.iv = phi i64 [ 0, %for.body13.preheader ], [ %indvars.iv.next, %for.body13 ] %arrayidx15 = getelementptr i8, ptr %src, i64 %indvars.iv @@ -1174,7 +1168,10 @@ for.body13: ; preds = %for.body13.preheade store i8 %conv36, ptr %dst, align 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count - br i1 %exitcond.not, label %for.cond.cleanup12.loopexit, label %for.body13 + br i1 %exitcond.not, label %for.cond.cleanup12, label %for.body13 + +for.cond.cleanup12: ; preds = %for.body13, %entry + ret void } ;. From b61144631a222f5ee303aab9e747820c80de2b1a Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 17 Dec 2024 16:08:36 +0800 Subject: [PATCH 3/6] Move to new test without FileCheck/UTC --- .../truncate-to-minimal-bitwidth-evl-crash.ll | 31 +++++ ...ize-force-tail-with-evl-cast-intrinsics.ll | 118 ------------------ 2 files changed, 31 insertions(+), 118 deletions(-) create mode 100644 llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll new file mode 100644 index 0000000000000..b0a3968a7ca2f --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll @@ -0,0 +1,31 @@ +; RUN: opt -passes=loop-vectorize -force-tail-folding-style=data-with-evl -prefer-predicate-over-epilogue=predicate-dont-vectorize -mtriple=riscv64 -mattr=+v -S %s + +; Make sure we don't crash when transforming a VPWidenCastRecipe is created +; without an underlying value. This occurs in this test via +; VPlanTransforms::truncateToMinimalBitwidths + +define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr %dst, ptr %src, i32 %mvx) { +entry: + %cmp111 = icmp sgt i32 %mvx, 0 + br i1 %cmp111, label %for.body13.preheader, label %for.cond.cleanup12 + +for.body13.preheader: ; preds = %entry + %wide.trip.count = zext nneg i32 %mvx to i64 + br label %for.body13 + +for.body13: ; preds = %for.body13.preheader, %for.body13 + %indvars.iv = phi i64 [ 0, %for.body13.preheader ], [ %indvars.iv.next, %for.body13 ] + %arrayidx15 = getelementptr i8, ptr %src, i64 %indvars.iv + %0 = load i8, ptr %arrayidx15, align 1 + %conv = zext i8 %0 to i32 + %mul16 = mul i32 %mvx, %conv + %shr35 = lshr i32 %mul16, 1 + %conv36 = trunc i32 %shr35 to i8 + store i8 %conv36, ptr %dst, align 1 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count + br i1 %exitcond.not, label %for.cond.cleanup12, label %for.body13 + +for.cond.cleanup12: ; preds = %for.body13, %entry + ret void +} diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll index 3f4f8b60d45d6..4557e95f1e1b6 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll @@ -1058,122 +1058,6 @@ loop: exit: ret void } - -define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr noalias %dst, ptr noalias %src, i32 %mvx) { -; IF-EVL-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe( -; IF-EVL-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i32 [[MVX:%.*]]) #[[ATTR0]] { -; IF-EVL-NEXT: [[ENTRY:.*:]] -; IF-EVL-NEXT: [[CMP111:%.*]] = icmp sgt i32 [[MVX]], 0 -; IF-EVL-NEXT: br i1 [[CMP111]], label %[[FOR_BODY13_PREHEADER:.*]], label %[[FOR_COND_CLEANUP12:.*]] -; IF-EVL: [[FOR_BODY13_PREHEADER]]: -; IF-EVL-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[MVX]] to i64 -; IF-EVL-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] -; IF-EVL: [[VECTOR_PH]]: -; IF-EVL-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() -; IF-EVL-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 16 -; IF-EVL-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], 1 -; IF-EVL-NEXT: [[N_RND_UP:%.*]] = add i64 [[WIDE_TRIP_COUNT]], [[TMP2]] -; IF-EVL-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP1]] -; IF-EVL-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] -; IF-EVL-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() -; IF-EVL-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 16 -; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i32 [[MVX]], i64 0 -; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer -; IF-EVL-NEXT: [[TMP5:%.*]] = trunc [[BROADCAST_SPLAT]] to -; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement poison, ptr [[DST]], i64 0 -; IF-EVL-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector [[BROADCAST_SPLATINSERT2]], poison, zeroinitializer -; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]] -; IF-EVL: [[VECTOR_BODY]]: -; IF-EVL-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ] -; IF-EVL-NEXT: [[AVL:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[EVL_BASED_IV]] -; IF-EVL-NEXT: [[TMP6:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 16, i1 true) -; IF-EVL-NEXT: [[TMP7:%.*]] = add i64 [[EVL_BASED_IV]], 0 -; IF-EVL-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP7]] -; IF-EVL-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP8]], i32 0 -; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call @llvm.vp.load.nxv16i8.p0(ptr align 1 [[TMP9]], splat (i1 true), i32 [[TMP6]]) -; IF-EVL-NEXT: [[TMP10:%.*]] = call @llvm.vp.zext.nxv16i16.nxv16i8( [[VP_OP_LOAD]], splat (i1 true), i32 [[TMP6]]) -; IF-EVL-NEXT: [[VP_OP:%.*]] = call @llvm.vp.mul.nxv16i16( [[TMP5]], [[TMP10]], splat (i1 true), i32 [[TMP6]]) -; IF-EVL-NEXT: [[VP_OP1:%.*]] = call @llvm.vp.lshr.nxv16i16( [[VP_OP]], trunc ( splat (i32 1) to ), splat (i1 true), i32 [[TMP6]]) -; IF-EVL-NEXT: [[TMP11:%.*]] = call @llvm.vp.trunc.nxv16i8.nxv16i16( [[VP_OP1]], splat (i1 true), i32 [[TMP6]]) -; IF-EVL-NEXT: call void @llvm.vp.scatter.nxv16i8.nxv16p0( [[TMP11]], align 1 [[BROADCAST_SPLAT3]], splat (i1 true), i32 [[TMP6]]) -; IF-EVL-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i64 -; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP12]], [[EVL_BASED_IV]] -; IF-EVL-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP4]] -; IF-EVL-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; IF-EVL-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP47:![0-9]+]] -; IF-EVL: [[MIDDLE_BLOCK]]: -; IF-EVL-NEXT: br i1 true, label %[[FOR_COND_CLEANUP12_LOOPEXIT:.*]], label %[[SCALAR_PH]] -; IF-EVL: [[SCALAR_PH]]: -; IF-EVL-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY13_PREHEADER]] ] -; IF-EVL-NEXT: br label %[[FOR_BODY13:.*]] -; IF-EVL: [[FOR_BODY13]]: -; IF-EVL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY13]] ] -; IF-EVL-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDVARS_IV]] -; IF-EVL-NEXT: [[TMP14:%.*]] = load i8, ptr [[ARRAYIDX15]], align 1 -; IF-EVL-NEXT: [[CONV:%.*]] = zext i8 [[TMP14]] to i32 -; IF-EVL-NEXT: [[MUL16:%.*]] = mul i32 [[MVX]], [[CONV]] -; IF-EVL-NEXT: [[SHR35:%.*]] = lshr i32 [[MUL16]], 1 -; IF-EVL-NEXT: [[CONV36:%.*]] = trunc i32 [[SHR35]] to i8 -; IF-EVL-NEXT: store i8 [[CONV36]], ptr [[DST]], align 1 -; IF-EVL-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 -; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] -; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP12_LOOPEXIT]], label %[[FOR_BODY13]], !llvm.loop [[LOOP48:![0-9]+]] -; IF-EVL: [[FOR_COND_CLEANUP12_LOOPEXIT]]: -; IF-EVL-NEXT: br label %[[FOR_COND_CLEANUP12]] -; IF-EVL: [[FOR_COND_CLEANUP12]]: -; IF-EVL-NEXT: ret void -; -; NO-VP-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe( -; NO-VP-SAME: ptr noalias [[DST:%.*]], ptr noalias [[SRC:%.*]], i32 [[MVX:%.*]]) #[[ATTR0]] { -; NO-VP-NEXT: [[ENTRY:.*:]] -; NO-VP-NEXT: [[CMP111:%.*]] = icmp sgt i32 [[MVX]], 0 -; NO-VP-NEXT: br i1 [[CMP111]], label %[[FOR_BODY13_PREHEADER:.*]], label %[[FOR_COND_CLEANUP12:.*]] -; NO-VP: [[FOR_BODY13_PREHEADER]]: -; NO-VP-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[MVX]] to i64 -; NO-VP-NEXT: br label %[[FOR_BODY13:.*]] -; NO-VP: [[FOR_BODY13]]: -; NO-VP-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[FOR_BODY13_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY13]] ] -; NO-VP-NEXT: [[ARRAYIDX15:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[INDVARS_IV]] -; NO-VP-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX15]], align 1 -; NO-VP-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 -; NO-VP-NEXT: [[MUL16:%.*]] = mul i32 [[MVX]], [[CONV]] -; NO-VP-NEXT: [[SHR35:%.*]] = lshr i32 [[MUL16]], 1 -; NO-VP-NEXT: [[CONV36:%.*]] = trunc i32 [[SHR35]] to i8 -; NO-VP-NEXT: store i8 [[CONV36]], ptr [[DST]], align 1 -; NO-VP-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 -; NO-VP-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] -; NO-VP-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP12_LOOPEXIT:.*]], label %[[FOR_BODY13]] -; NO-VP: [[FOR_COND_CLEANUP12_LOOPEXIT]]: -; NO-VP-NEXT: br label %[[FOR_COND_CLEANUP12]] -; NO-VP: [[FOR_COND_CLEANUP12]]: -; NO-VP-NEXT: ret void -; -entry: - %cmp111 = icmp sgt i32 %mvx, 0 - br i1 %cmp111, label %for.body13.preheader, label %for.cond.cleanup12 - -for.body13.preheader: ; preds = %entry - %wide.trip.count = zext nneg i32 %mvx to i64 - br label %for.body13 - -for.body13: ; preds = %for.body13.preheader, %for.body13 - %indvars.iv = phi i64 [ 0, %for.body13.preheader ], [ %indvars.iv.next, %for.body13 ] - %arrayidx15 = getelementptr i8, ptr %src, i64 %indvars.iv - %0 = load i8, ptr %arrayidx15, align 1 - %conv = zext i8 %0 to i32 - %mul16 = mul i32 %mvx, %conv - %shr35 = lshr i32 %mul16, 1 - %conv36 = trunc i32 %shr35 to i8 - store i8 %conv36, ptr %dst, align 1 - %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 - %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count - br i1 %exitcond.not, label %for.cond.cleanup12, label %for.body13 - -for.cond.cleanup12: ; preds = %for.body13, %entry - ret void -} - ;. ; IF-EVL: [[META0]] = !{[[META1:![0-9]+]]} ; IF-EVL: [[META1]] = distinct !{[[META1]], [[META2:![0-9]+]]} @@ -1222,6 +1106,4 @@ for.cond.cleanup12: ; preds = %for.body13, %entry ; IF-EVL: [[LOOP44]] = distinct !{[[LOOP44]], [[META6]]} ; IF-EVL: [[LOOP45]] = distinct !{[[LOOP45]], [[META6]], [[META7]]} ; IF-EVL: [[LOOP46]] = distinct !{[[LOOP46]], [[META6]]} -; IF-EVL: [[LOOP47]] = distinct !{[[LOOP47]], [[META6]], [[META7]]} -; IF-EVL: [[LOOP48]] = distinct !{[[LOOP48]], [[META7]], [[META6]]} ;. From f57e06afe0ac9e86e55f16f464754ab5231e0524 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 17 Dec 2024 16:17:24 +0800 Subject: [PATCH 4/6] Fix comment --- .../RISCV/truncate-to-minimal-bitwidth-evl-crash.ll | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll index b0a3968a7ca2f..ade23538e9750 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll @@ -1,7 +1,7 @@ ; RUN: opt -passes=loop-vectorize -force-tail-folding-style=data-with-evl -prefer-predicate-over-epilogue=predicate-dont-vectorize -mtriple=riscv64 -mattr=+v -S %s -; Make sure we don't crash when transforming a VPWidenCastRecipe is created -; without an underlying value. This occurs in this test via +; Make sure we don't crash when transforming a VPWidenCastRecipe created without +; an underlying value to an EVL recipe. This occurs in this test via ; VPlanTransforms::truncateToMinimalBitwidths define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr %dst, ptr %src, i32 %mvx) { From 4335c21adedb4ab1b621c76c38bf80c475b1467f Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 17 Dec 2024 18:19:30 +0800 Subject: [PATCH 5/6] Tidy up test --- .../truncate-to-minimal-bitwidth-evl-crash.ll | 89 +++++++++++++++---- 1 file changed, 71 insertions(+), 18 deletions(-) diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll index ade23538e9750..68b36f23de4b0 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/truncate-to-minimal-bitwidth-evl-crash.ll @@ -1,31 +1,84 @@ -; RUN: opt -passes=loop-vectorize -force-tail-folding-style=data-with-evl -prefer-predicate-over-epilogue=predicate-dont-vectorize -mtriple=riscv64 -mattr=+v -S %s +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -passes=loop-vectorize -force-tail-folding-style=data-with-evl -prefer-predicate-over-epilogue=predicate-dont-vectorize -mtriple=riscv64 -mattr=+v -S %s | FileCheck %s ; Make sure we don't crash when transforming a VPWidenCastRecipe created without ; an underlying value to an EVL recipe. This occurs in this test via ; VPlanTransforms::truncateToMinimalBitwidths -define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr %dst, ptr %src, i32 %mvx) { +define void @truncate_to_minimal_bitwidths_widen_cast_recipe(ptr %src) { +; CHECK-LABEL: define void @truncate_to_minimal_bitwidths_widen_cast_recipe( +; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], 1 +; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 2, [[TMP1]] +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP0]] +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[AVL:%.*]] = sub i64 2, [[EVL_BASED_IV]] +; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 1, i1 true) +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[EVL_BASED_IV]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i32 0 +; CHECK-NEXT: [[VP_OP_LOAD:%.*]] = call @llvm.vp.load.nxv1i8.p0(ptr align 1 [[TMP6]], splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[TMP7:%.*]] = call @llvm.vp.zext.nxv1i16.nxv1i8( [[VP_OP_LOAD]], splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[VP_OP:%.*]] = call @llvm.vp.mul.nxv1i16( zeroinitializer, [[TMP7]], splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[VP_OP1:%.*]] = call @llvm.vp.lshr.nxv1i16( [[VP_OP]], trunc ( splat (i32 1) to ), splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[TMP8:%.*]] = call @llvm.vp.trunc.nxv1i8.nxv1i16( [[VP_OP1]], splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: call void @llvm.vp.scatter.nxv1i8.nxv1p0( [[TMP8]], align 1 zeroinitializer, splat (i1 true), i32 [[TMP3]]) +; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP3]] to i64 +; CHECK-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP9]], [[EVL_BASED_IV]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP2]] +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]] +; CHECK: [[SCALAR_PH]]: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]] +; CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[GEP_SRC]], align 1 +; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP11]] to i32 +; CHECK-NEXT: [[MUL16:%.*]] = mul i32 0, [[CONV]] +; CHECK-NEXT: [[SHR35:%.*]] = lshr i32 [[MUL16]], 1 +; CHECK-NEXT: [[CONV36:%.*]] = trunc i32 [[SHR35]] to i8 +; CHECK-NEXT: store i8 [[CONV36]], ptr null, align 1 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1 +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; entry: - %cmp111 = icmp sgt i32 %mvx, 0 - br i1 %cmp111, label %for.body13.preheader, label %for.cond.cleanup12 + br label %loop -for.body13.preheader: ; preds = %entry - %wide.trip.count = zext nneg i32 %mvx to i64 - br label %for.body13 - -for.body13: ; preds = %for.body13.preheader, %for.body13 - %indvars.iv = phi i64 [ 0, %for.body13.preheader ], [ %indvars.iv.next, %for.body13 ] - %arrayidx15 = getelementptr i8, ptr %src, i64 %indvars.iv - %0 = load i8, ptr %arrayidx15, align 1 +loop: ; preds = %loop, %entry + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.src = getelementptr i8, ptr %src, i64 %iv + %0 = load i8, ptr %gep.src, align 1 %conv = zext i8 %0 to i32 - %mul16 = mul i32 %mvx, %conv + %mul16 = mul i32 0, %conv %shr35 = lshr i32 %mul16, 1 %conv36 = trunc i32 %shr35 to i8 - store i8 %conv36, ptr %dst, align 1 - %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 - %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count - br i1 %exitcond.not, label %for.cond.cleanup12, label %for.body13 + store i8 %conv36, ptr null, align 1 + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, 1 + br i1 %ec, label %exit, label %loop -for.cond.cleanup12: ; preds = %for.body13, %entry +exit: ; preds = %loop ret void } +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +;. From cf73213227cd198a86f0c1c095bf26c2dea962a0 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 17 Dec 2024 18:20:14 +0800 Subject: [PATCH 6/6] Rename CInst -> CastR --- llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index 85931a9d95a85..6aff0ad899421 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -1505,13 +1505,13 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) { CInst->getDebugLoc()); }) .Case( - [&](VPWidenCastRecipe *CInst) -> VPRecipeBase * { + [&](VPWidenCastRecipe *CastR) -> VPRecipeBase * { Intrinsic::ID VPID = - VPIntrinsic::getForOpcode(CInst->getOpcode()); + VPIntrinsic::getForOpcode(CastR->getOpcode()); assert(VPID != Intrinsic::not_intrinsic && "Expected vp.casts Instrinsic"); - SmallVector Ops(CInst->operands()); + SmallVector Ops(CastR->operands()); assert(VPIntrinsic::getMaskParamPos(VPID) && VPIntrinsic::getVectorLengthParamPos(VPID) && "Expected VP intrinsic"); @@ -1520,8 +1520,8 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) { Ops.push_back(Mask); Ops.push_back(&EVL); return new VPWidenIntrinsicRecipe( - VPID, Ops, TypeInfo.inferScalarType(CInst), - CInst->getDebugLoc()); + VPID, Ops, TypeInfo.inferScalarType(CastR), + CastR->getDebugLoc()); }) .Case([&](VPWidenSelectRecipe *Sel) { SmallVector Ops(Sel->operands());