From 0ce089bcce26c70d931175e9b8d63fd083cde769 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 18 Dec 2024 15:18:19 +0800 Subject: [PATCH 1/3] [InstCombine] Add pre-commit tests. NFC. --- .../Transforms/InstCombine/icmp-logical.ll | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/icmp-logical.ll b/llvm/test/Transforms/InstCombine/icmp-logical.ll index 50feb51092fd9..f2cfa78a40034 100644 --- a/llvm/test/Transforms/InstCombine/icmp-logical.ll +++ b/llvm/test/Transforms/InstCombine/icmp-logical.ll @@ -1900,3 +1900,28 @@ define i1 @masked_icmps_bmask_notmixed_not_subset_notoptimized(i32 %A) { %res = and i1 %tst1, %tst2 ret i1 %res } + +define i1 @pr120361(i8 %x, i8 %y) { +; CHECK-LABEL: @pr120361( +; CHECK-NEXT: [[CMP1:%.*]] = icmp samesign eq i8 [[X:%.*]], -1 +; CHECK-NEXT: ret i1 [[CMP1]] +; + %cmp1 = icmp samesign eq i8 %x, -1 + %cmp2 = icmp ne i8 %x, 0 + %result = select i1 %cmp2, i1 %cmp1, i1 false + ret i1 %result +} + +define i1 @pr120361_v2(i32 %x) { +; CHECK-LABEL: @pr120361_v2( +; CHECK-NEXT: [[AND2:%.*]] = and i32 [[X:%.*]], -113 +; CHECK-NEXT: [[CMP2:%.*]] = icmp samesign eq i32 [[AND2]], 15 +; CHECK-NEXT: ret i1 [[CMP2]] +; + %and1 = and i32 %x, 15 + %cmp1 = icmp ne i32 %and1, 0 + %and2 = and i32 %x, -113 + %cmp2 = icmp samesign eq i32 %and2, 15 + %and = select i1 %cmp1, i1 %cmp2, i1 false + ret i1 %and +} From 05d929e89b6276d2f0c981d8b7032ca6f5147967 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 18 Dec 2024 15:19:55 +0800 Subject: [PATCH 2/3] [InstCombine] Drop samesign flags in `foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed` --- llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 5 ++++- llvm/test/Transforms/InstCombine/icmp-logical.ll | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index dff9304be64dd..82dc82c640eaa 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -455,8 +455,11 @@ static Value *foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed( // RHS. For example, // (icmp ne (A & 255), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8). // (icmp ne (A & 15), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8). - if (IsSuperSetOrEqual(BCst, DCst)) + if (IsSuperSetOrEqual(BCst, DCst)) { + // We can't guarantee that samesign hold after this fold. + RHS->setSameSign(false); return RHS; + } // Otherwise, B is a subset of D. If B and E have a common bit set, // ie. (B & E) != 0, then LHS is subsumed by RHS. For example. // (icmp ne (A & 12), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8). diff --git a/llvm/test/Transforms/InstCombine/icmp-logical.ll b/llvm/test/Transforms/InstCombine/icmp-logical.ll index f2cfa78a40034..07b657b8e3e57 100644 --- a/llvm/test/Transforms/InstCombine/icmp-logical.ll +++ b/llvm/test/Transforms/InstCombine/icmp-logical.ll @@ -1903,7 +1903,7 @@ define i1 @masked_icmps_bmask_notmixed_not_subset_notoptimized(i32 %A) { define i1 @pr120361(i8 %x, i8 %y) { ; CHECK-LABEL: @pr120361( -; CHECK-NEXT: [[CMP1:%.*]] = icmp samesign eq i8 [[X:%.*]], -1 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], -1 ; CHECK-NEXT: ret i1 [[CMP1]] ; %cmp1 = icmp samesign eq i8 %x, -1 From 32ef1af8c7c3b324d5c4fe42b9f45927bebaa3f0 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Wed, 18 Dec 2024 15:20:36 +0800 Subject: [PATCH 3/3] [InstCombine] Drop samesign flags in `foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed` --- llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 5 ++++- llvm/test/Transforms/InstCombine/icmp-logical.ll | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 82dc82c640eaa..e576eea4ca36a 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -464,8 +464,11 @@ static Value *foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed( // ie. (B & E) != 0, then LHS is subsumed by RHS. For example. // (icmp ne (A & 12), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8). assert(IsSubSetOrEqual(BCst, DCst) && "Precondition due to above code"); - if ((*BCst & ECst) != 0) + if ((*BCst & ECst) != 0) { + // We can't guarantee that samesign hold after this fold. + RHS->setSameSign(false); return RHS; + } // Otherwise, LHS and RHS contradict and the whole expression becomes false // (or true if negated.) For example, // (icmp ne (A & 7), 0) & (icmp eq (A & 15), 8) -> false. diff --git a/llvm/test/Transforms/InstCombine/icmp-logical.ll b/llvm/test/Transforms/InstCombine/icmp-logical.ll index 07b657b8e3e57..df8442e069b78 100644 --- a/llvm/test/Transforms/InstCombine/icmp-logical.ll +++ b/llvm/test/Transforms/InstCombine/icmp-logical.ll @@ -1915,7 +1915,7 @@ define i1 @pr120361(i8 %x, i8 %y) { define i1 @pr120361_v2(i32 %x) { ; CHECK-LABEL: @pr120361_v2( ; CHECK-NEXT: [[AND2:%.*]] = and i32 [[X:%.*]], -113 -; CHECK-NEXT: [[CMP2:%.*]] = icmp samesign eq i32 [[AND2]], 15 +; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 15 ; CHECK-NEXT: ret i1 [[CMP2]] ; %and1 = and i32 %x, 15