From a8d8ad88620481ec5cbf588d8be9221bdd25e495 Mon Sep 17 00:00:00 2001 From: Hiroshi Yamauchi Date: Tue, 21 Jan 2025 10:25:04 -0800 Subject: [PATCH] [AArch64][WinCFI] Fix a crash due to missing seh directives https://github.com/llvm/llvm-project/issues/123808 --- .../Target/AArch64/AArch64FrameLowering.cpp | 22 +++-- .../CodeGen/AArch64/stack-hazard-windows.ll | 4 + .../AArch64/wincfi-missing-seh-directives.ll | 86 +++++++++++++++++++ 3 files changed, 103 insertions(+), 9 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/wincfi-missing-seh-directives.ll diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index eabe64361938b..a082a1ebe95bf 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1491,13 +1491,6 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec( NewOpc = AArch64::LDRQpost; break; } - // Get rid of the SEH code associated with the old instruction. - if (NeedsWinCFI) { - auto SEH = std::next(MBBI); - if (AArch64InstrInfo::isSEHInstruction(*SEH)) - SEH->eraseFromParent(); - } - TypeSize Scale = TypeSize::getFixed(1), Width = TypeSize::getFixed(0); int64_t MinOffset, MaxOffset; bool Success = static_cast(TII)->getMemOpInfo( @@ -1512,16 +1505,27 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec( CSStackSizeInc > MaxOffset * (int64_t)Scale.getFixedValue()) { // If we are destroying the frame, make sure we add the increment after the // last frame operation. - if (FrameFlag == MachineInstr::FrameDestroy) + if (FrameFlag == MachineInstr::FrameDestroy) { ++MBBI; + // Also skip the SEH instruction, if needed + if (NeedsWinCFI && AArch64InstrInfo::isSEHInstruction(*MBBI)) + ++MBBI; + } emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, StackOffset::getFixed(CSStackSizeInc), TII, FrameFlag, - false, false, nullptr, EmitCFI, + false, NeedsWinCFI, HasWinCFI, EmitCFI, StackOffset::getFixed(CFAOffset)); return std::prev(MBBI); } + // Get rid of the SEH code associated with the old instruction. + if (NeedsWinCFI) { + auto SEH = std::next(MBBI); + if (AArch64InstrInfo::isSEHInstruction(*SEH)) + SEH->eraseFromParent(); + } + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)); MIB.addReg(AArch64::SP, RegState::Define); diff --git a/llvm/test/CodeGen/AArch64/stack-hazard-windows.ll b/llvm/test/CodeGen/AArch64/stack-hazard-windows.ll index 2a034fe5e5290..927d8b68c46be 100644 --- a/llvm/test/CodeGen/AArch64/stack-hazard-windows.ll +++ b/llvm/test/CodeGen/AArch64/stack-hazard-windows.ll @@ -76,7 +76,9 @@ define i32 @fpr_csr_stackobj(double %x) "aarch64_pstate_sm_compatible" "frame-po ; CHECK1024: .seh_proc fpr_csr_stackobj ; CHECK1024-NEXT: // %bb.0: // %entry ; CHECK1024-NEXT: sub sp, sp, #1072 +; CHECK1024-NEXT: .seh_stackalloc 1072 ; CHECK1024-NEXT: str x23, [sp] // 8-byte Folded Spill +; CHECK1024-NEXT: .seh_save_reg x23, 0 ; CHECK1024-NEXT: str x29, [sp, #8] // 8-byte Folded Spill ; CHECK1024-NEXT: .seh_save_reg x29, 8 ; CHECK1024-NEXT: str x30, [sp, #16] // 8-byte Folded Spill @@ -105,7 +107,9 @@ define i32 @fpr_csr_stackobj(double %x) "aarch64_pstate_sm_compatible" "frame-po ; CHECK1024-NEXT: ldr x29, [sp, #8] // 8-byte Folded Reload ; CHECK1024-NEXT: .seh_save_reg x29, 8 ; CHECK1024-NEXT: ldr x23, [sp] // 8-byte Folded Reload +; CHECK1024-NEXT: .seh_save_reg x23, 0 ; CHECK1024-NEXT: add sp, sp, #1072 +; CHECK1024-NEXT: .seh_stackalloc 1072 ; CHECK1024-NEXT: .seh_endepilogue ; CHECK1024-NEXT: ret ; CHECK1024-NEXT: .seh_endfunclet diff --git a/llvm/test/CodeGen/AArch64/wincfi-missing-seh-directives.ll b/llvm/test/CodeGen/AArch64/wincfi-missing-seh-directives.ll new file mode 100644 index 0000000000000..2002c37cb2528 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/wincfi-missing-seh-directives.ll @@ -0,0 +1,86 @@ +; RUN: llc -mtriple=aarch64-windows %s --filetype obj -o /dev/null +; RUN: llc -mtriple=aarch64-windows %s --filetype asm -o - | FileCheck %s + +; Check that it doesn't crash and that each instruction in the +; prologue has a corresponding seh directive. +; +; CHECK-NOT: error: Incorrect size for +; CHECK: foo: +; CHECK: .seh_proc foo +; CHECK: sub sp, sp, #288 +; CHECK: .seh_stackalloc 288 +; CHECK: str x19, [sp] // 8-byte Folded Spill +; CHECK: .seh_save_reg x19, 0 +; CHECK: str x21, [sp, #8] // 8-byte Folded Spill +; CHECK: .seh_save_reg x21, 8 +; CHECK: stp x23, x24, [sp, #16] // 16-byte Folded Spill +; CHECK: .seh_save_regp x23, 16 +; CHECK: stp x25, x26, [sp, #32] // 16-byte Folded Spill +; CHECK: .seh_save_regp x25, 32 +; CHECK: stp x27, x28, [sp, #48] // 16-byte Folded Spill +; CHECK: .seh_save_regp x27, 48 +; CHECK: stp x29, x30, [sp, #64] // 16-byte Folded Spill +; CHECK: .seh_save_fplr 64 +; CHECK: sub sp, sp, #224 +; CHECK: .seh_stackalloc 224 +; CHECK: .seh_endprologue + +target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128-Fn32" +target triple = "aarch64-unknown-windows-msvc19.42.34436" + +%swift.refcounted = type { ptr, i64 } +%TScA_pSg = type <{ [16 x i8] }> +%T5repro4TestVSg = type <{ [32 x i8] }> +%T5repro4TestV = type <{ %TSS, %TSS }> +%TSS = type <{ %Ts11_StringGutsV }> +%Ts11_StringGutsV = type <{ %Ts13_StringObjectV }> +%Ts13_StringObjectV = type <{ %Ts6UInt64V, ptr }> +%Ts6UInt64V = type <{ i64 }> + +declare swiftcc ptr @swift_task_alloc() + +declare swifttailcc void @bar(ptr, ptr, i64, i64, i64, ptr, i64, i64, i64, i64, i64, ptr, i64, ptr, i64, ptr, i64, ptr, i64, ptr, i64, ptr, i64, ptr, i64, ptr, i64, ptr, i64, ptr, i64, ptr, i64, ptr, i64, ptr) + +define swifttailcc void @foo(ptr %0, ptr swiftasync %1, ptr swiftself %2, ptr %3, ptr %._guts2._object._object, ptr %.rid4._guts._object._object, ptr %4, ptr %.idx8, ptr %.idx8._guts._object._object, ptr %5, ptr %.rid9._guts._object._object, ptr %6) { +entry: + %7 = load i64, ptr null, align 8 + %8 = load i64, ptr %3, align 8 + %9 = getelementptr <{ %swift.refcounted, %TScA_pSg, %TSS, %T5repro4TestVSg, %T5repro4TestV, %TSS, %TSS, %TSS, %T5repro4TestV, %TSS, %T5repro4TestV, %T5repro4TestV, %TSS }>, ptr %2, i32 0, i32 2 + %10 = load i64, ptr %9, align 8 + %11 = load ptr, ptr %1, align 8 + %12 = getelementptr <{ %swift.refcounted, %TScA_pSg, %TSS, %T5repro4TestVSg, %T5repro4TestV, %TSS, %TSS, %TSS, %T5repro4TestV, %TSS, %T5repro4TestV, %T5repro4TestV, %TSS }>, ptr %2, i32 0, i32 3 + %13 = load i64, ptr %.rid9._guts._object._object, align 8 + %14 = load i64, ptr %.idx8._guts._object._object, align 8 + %15 = load i64, ptr %5, align 8 + %16 = getelementptr { i64, i64, i64, i64 }, ptr %12, i32 0, i32 3 + %17 = load i64, ptr %16, align 8 + %18 = getelementptr <{ %swift.refcounted, %TScA_pSg, %TSS, %T5repro4TestVSg, %T5repro4TestV, %TSS, %TSS, %TSS, %T5repro4TestV, %TSS, %T5repro4TestV, %T5repro4TestV, %TSS }>, ptr %2, i32 0, i32 4 + %19 = load i64, ptr %18, align 8 + %.rid._guts._object._object = getelementptr %Ts13_StringObjectV, ptr %18, i32 0, i32 1 + %20 = load ptr, ptr %.rid._guts._object._object, align 8 + %21 = load i64, ptr %.rid4._guts._object._object, align 8 + %22 = load i64, ptr %0, align 8 + %23 = load ptr, ptr %6, align 8 + %24 = load i64, ptr %2, align 8 + %25 = load ptr, ptr %._guts2._object._object, align 8 + %26 = getelementptr <{ %swift.refcounted, %TScA_pSg, %TSS, %T5repro4TestVSg, %T5repro4TestV, %TSS, %TSS, %TSS, %T5repro4TestV, %TSS, %T5repro4TestV, %T5repro4TestV, %TSS }>, ptr %2, i32 0, i32 7 + %27 = load i64, ptr %26, align 8 + %._guts3._object._object = getelementptr %Ts13_StringObjectV, ptr %26, i32 0, i32 1 + %28 = load ptr, ptr %._guts3._object._object, align 8 + %29 = getelementptr <{ %swift.refcounted, %TScA_pSg, %TSS, %T5repro4TestVSg, %T5repro4TestV, %TSS, %TSS, %TSS, %T5repro4TestV, %TSS, %T5repro4TestV, %T5repro4TestV, %TSS }>, ptr %2, i32 0, i32 8 + %30 = load i64, ptr %29, align 8 + %.idx5 = getelementptr %T5repro4TestV, ptr %29, i32 0, i32 1 + %31 = load i64, ptr %.idx5, align 8 + %.idx5._guts._object._object = getelementptr %Ts13_StringObjectV, ptr %.idx5, i32 0, i32 1 + %32 = load ptr, ptr %.idx5._guts._object._object, align 8 + %33 = getelementptr <{ %swift.refcounted, %TScA_pSg, %TSS, %T5repro4TestVSg, %T5repro4TestV, %TSS, %TSS, %TSS, %T5repro4TestV, %TSS, %T5repro4TestV, %T5repro4TestV, %TSS }>, ptr %2, i32 0, i32 9 + %34 = load i64, ptr %33, align 8 + %35 = load i64, ptr %4, align 8 + %36 = load i64, ptr %.idx8, align 8 + %37 = load i64, ptr %1, align 8 + %38 = call swiftcc ptr @swift_task_alloc() + store ptr null, ptr %3, align 8 + store ptr null, ptr %4, align 8 + musttail call swifttailcc void @bar(ptr null, ptr swiftasync %.rid4._guts._object._object, i64 %7, i64 %8, i64 %10, ptr %5, i64 %13, i64 %14, i64 %15, i64 %17, i64 %19, ptr %20, i64 %21, ptr %.idx8, i64 %22, ptr %23, i64 %24, ptr %25, i64 %27, ptr %28, i64 %30, ptr %.idx8._guts._object._object, i64 %31, ptr %32, i64 %34, ptr %._guts2._object._object, i64 %35, ptr %2, i64 %36, ptr %1, i64 %37, ptr %0, i64 0, ptr null, i64 0, ptr null) + ret void +}