From 32056369be2d764b2c71245cade09e60c858c3db Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 10 Mar 2025 20:51:46 -0700 Subject: [PATCH 1/2] [RISCV] Sink hasSideEffects, mayLoad, mayStore from defs to classes in RISCVInstrInfo.td. NFC This is consistent with how RISCVInstrInfo.td is generally structured. --- llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td | 61 +++++++++++----------- 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td index 4cf0bb94af347..11670380e705a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td @@ -10,7 +10,8 @@ // //===----------------------------------------------------------------------===// -let DecoderNamespace = "XCV" in { +let DecoderNamespace = "XCV", + hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class CVInstBitManipRII funct2, bits<3> funct3, dag outs, dag ins, string opcodestr, string argstr> : RVInstIBase { @@ -36,10 +37,9 @@ let DecoderNamespace = "XCV" in { (ins GPR:$rs1), opcodestr, "$rd, $rs1"> { let rs2 = 0b00000; } -} +} // DecoderNamespace = "XCV", hasSideEffects = 0, mayLoad = 0, mayStore = 0 -let Predicates = [HasVendorXCVbitmanip, IsRV32], - hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +let Predicates = [HasVendorXCVbitmanip, IsRV32] in { def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">; def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">; @@ -54,7 +54,8 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32], def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2), "cv.insert", "$rd, $rs1, $is3, $is2">; - let DecoderNamespace = "XCV" in + let DecoderNamespace = "XCV", + hasSideEffects = 0, mayLoad = 0, mayStore = 0 in def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2), "cv.insertr", "$rd, $rs1, $rs2">; @@ -70,6 +71,7 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32], def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">; } +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class CVInstMac funct7, bits<3> funct3, string opcodestr> : RVInstR funct2, bits<3> funct3, dag outs, dag ins, let DecoderNamespace = "XCV"; } +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class CVInstMacN funct2, bits<3> funct3, string opcodestr> : CVInstMacMulN { @@ -98,9 +101,9 @@ class CVInstMacN funct2, bits<3> funct3, string opcodestr> class CVInstMulN funct2, bits<3> funct3, string opcodestr> : CVInstMacMulN; +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 -let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, - mayStore = 0 in { +let Predicates = [HasVendorXCVmac, IsRV32] in { // 32x32 bit macs def CV_MAC : CVInstMac<0b1001000, 0b011, "cv.mac">, Sched<[]>; @@ -126,9 +129,7 @@ let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, Sched<[]>; def CV_MACHHURN : CVInstMacN<0b11, 0b111, "cv.machhurn">, Sched<[]>; -} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0... -let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { // Signed 16x16 bit muls with imm def CV_MULSN : CVInstMulN<0b00, 0b100, "cv.mulsn">, Sched<[]>; @@ -148,9 +149,7 @@ let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, may Sched<[]>; def CV_MULHHURN : CVInstMulN<0b11, 0b101, "cv.mulhhurn">, Sched<[]>; -} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0... -let Predicates = [HasVendorXCVmac, IsRV32] in { // Xcvmac Pseudo Instructions // Signed 16x16 bit muls def : InstAlias<"cv.muls $rd1, $rs1, $rs2", @@ -165,7 +164,8 @@ let Predicates = [HasVendorXCVmac, IsRV32] in { (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>; } // Predicates = [HasVendorXCVmac, IsRV32] -let DecoderNamespace = "XCV" in { +let DecoderNamespace = "XCV", + hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class CVInstAluRRI funct2, bits<3> funct3, string opcodestr> : RVInstRBase, Sched<[]>; @@ -255,11 +254,7 @@ let Predicates = [HasVendorXCValu, IsRV32], Sched<[]>; def CV_SUBURN : CVInstAluRRI<0b11, 0b011, "cv.suburn">, Sched<[]>; -} // Predicates = [HasVendorXCValu, IsRV32], - // hasSideEffects = 0, mayLoad = 0, mayStore = 0 -let Predicates = [HasVendorXCValu, IsRV32], - hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { def CV_ADDNR : CVInstAluRRNR<0b1000000, 0b011, "cv.addnr">, Sched<[]>; def CV_ADDUNR : CVInstAluRRNR<0b1000001, 0b011, "cv.addunr">, @@ -277,8 +272,7 @@ let Predicates = [HasVendorXCValu, IsRV32], def CV_SUBURNR : CVInstAluRRNR<0b1000111, 0b011, "cv.suburnr">, Sched<[]>; -} // Predicates = [HasVendorXCValu, IsRV32], - // hasSideEffects = 0, mayLoad = 0, mayStore = 0, +} // Predicates = [HasVendorXCValu, IsRV32] let Predicates = [HasVendorXCValu, IsRV32] in { def : MnemonicAlias<"cv.slet", "cv.sle">; @@ -307,6 +301,7 @@ class CVInstSIMDRI funct5, bit F, bits<3> funct3, RISCVOpcode opcode, let DecoderNamespace = "XCV"; } +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class CVSIMDRR funct5, bit F, bit funct1, bits<3> funct3, string opcodestr> : CVInstSIMDRR funct5, bit F, bit funct1, bits<3> funct3, (ins GPR:$rs1), opcodestr, "$rd, $rs1"> { let rs2 = 0b00000; } +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 multiclass CVSIMDBinarySigned funct5, bit F, bit funct1, string mnemonic> { def CV_ # NAME # _H : CVSIMDRR; @@ -397,8 +393,7 @@ multiclass CVSIMDBinaryUnsignedWb funct5, bit F, bit funct1, string mnem } -let Predicates = [HasVendorXCVsimd, IsRV32], - hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +let Predicates = [HasVendorXCVsimd, IsRV32] in { defm ADD : CVSIMDBinarySigned<0b00000, 0, 0, "add">; defm SUB : CVSIMDBinarySigned<0b00001, 0, 0, "sub">; defm AVG : CVSIMDBinarySigned<0b00010, 0, 0, "avg">; @@ -495,16 +490,18 @@ let Predicates = [HasVendorXCVsimd, IsRV32], def CV_SUB_DIV8 : CVSIMDRR<0b01110, 1, 0, 0b110, "cv.sub.div8">; } +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class CVInstImmBranch funct3, dag outs, dag ins, string opcodestr, string argstr> : RVInstB { bits<5> imm5; let rs2 = imm5; + let isBranch = 1; + let isTerminator = 1; let DecoderNamespace = "XCV"; } -let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0, - mayStore = 0, isBranch = 1, isTerminator = 1 in { +let Predicates = [HasVendorXCVbi, IsRV32] in { // Immediate branching operations def CV_BEQIMM : CVInstImmBranch<0b110, (outs), (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12), @@ -530,15 +527,18 @@ def CVrr : Operand, let MIOperandInfo = (ops GPR:$base, GPR:$offset); } +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { class CVLoad_ri_inc funct3, string opcodestr> - : RVInstI { let Constraints = "$rs1_wb = $rs1"; let DecoderNamespace = "XCV"; } class CVLoad_rr_inc funct7, bits<3> funct3, string opcodestr> - : RVInstR { let Constraints = "$rs1_wb = $rs1"; let DecoderNamespace = "XCV"; @@ -557,9 +557,9 @@ class CVLoad_rr funct7, bits<3> funct3, string opcodestr> let Inst{11-7} = rd; let DecoderNamespace = "XCV"; } +} // hasSideEffects = 0, mayLoad = 1, mayStore = 0 -let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, mayLoad = 1, - mayStore = 0 in { +let Predicates = [HasVendorXCVmem, IsRV32] in { // Register-Immediate load with post-increment def CV_LB_ri_inc : CVLoad_ri_inc<0b000, "cv.lb">; def CV_LBU_ri_inc : CVLoad_ri_inc<0b100, "cv.lbu">; @@ -582,6 +582,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, mayLoad = 1, def CV_LW_rr : CVLoad_rr<0b0000110, 0b011, "cv.lw">; } +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { class CVStore_ri_inc funct3, string opcodestr> : RVInstS funct3, bits<7> funct7, string opcodestr> let Inst{6-0} = OPC_CUSTOM_1.Value; let DecoderNamespace = "XCV"; } +} // hasSideEffects = 0, mayLoad = 0, mayStore = 1 -let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0, mayLoad = 0, - mayStore = 1 in { +let Predicates = [HasVendorXCVmem, IsRV32] in { // Register-Immediate store with post-increment def CV_SB_ri_inc : CVStore_ri_inc<0b000, "cv.sb">; def CV_SH_ri_inc : CVStore_ri_inc<0b001, "cv.sh">; From 61031d4a70810dd34351866c3319ec5cb0966dfc Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 10 Mar 2025 23:25:15 -0700 Subject: [PATCH 2/2] fixup! Address review comments --- llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td index 11670380e705a..f9ceba18f87f8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td @@ -71,12 +71,14 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32] in { def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">; } -let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class CVInstMac funct7, bits<3> funct3, string opcodestr> : RVInstR { let Constraints = "$rd = $rd_wb"; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; let DecoderNamespace = "XCV"; } @@ -88,10 +90,14 @@ class CVInstMacMulN funct2, bits<3> funct3, dag outs, dag ins, let Inst{31-30} = funct2; let Inst{29-25} = imm5; + + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; + let DecoderNamespace = "XCV"; } -let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class CVInstMacN funct2, bits<3> funct3, string opcodestr> : CVInstMacMulN { @@ -101,7 +107,6 @@ class CVInstMacN funct2, bits<3> funct3, string opcodestr> class CVInstMulN funct2, bits<3> funct3, string opcodestr> : CVInstMacMulN; -} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 let Predicates = [HasVendorXCVmac, IsRV32] in { // 32x32 bit macs @@ -490,7 +495,6 @@ let Predicates = [HasVendorXCVsimd, IsRV32] in { def CV_SUB_DIV8 : CVSIMDRR<0b01110, 1, 0, 0b110, "cv.sub.div8">; } -let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class CVInstImmBranch funct3, dag outs, dag ins, string opcodestr, string argstr> : RVInstB { @@ -498,6 +502,9 @@ class CVInstImmBranch funct3, dag outs, dag ins, let rs2 = imm5; let isBranch = 1; let isTerminator = 1; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; let DecoderNamespace = "XCV"; }