diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 6511c197fcb5a..82bafa39a805d 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -2512,20 +2512,25 @@ struct MemorySanitizerVisitor : public InstVisitor { // S = S | (V1 & V2) Value *S1 = getShadow(&I, 0); Value *S2 = getShadow(&I, 1); - Value *V1 = IRB.CreateNot(I.getOperand(0)); - Value *V2 = IRB.CreateNot(I.getOperand(1)); + Value *V1 = I.getOperand(0); + Value *V2 = I.getOperand(1); if (V1->getType() != S1->getType()) { V1 = IRB.CreateIntCast(V1, S1->getType(), false); V2 = IRB.CreateIntCast(V2, S2->getType(), false); } + + Value *NotV1 = IRB.CreateNot(V1); + Value *NotV2 = IRB.CreateNot(V2); + Value *S1S2 = IRB.CreateAnd(S1, S2); - Value *V1S2 = IRB.CreateAnd(V1, S2); - Value *S1V2 = IRB.CreateAnd(S1, V2); + Value *S2NotV1 = IRB.CreateAnd(NotV1, S2); + Value *S1NotV2 = IRB.CreateAnd(S1, NotV2); + + Value *S = IRB.CreateOr({S1S2, S2NotV1, S1NotV2}); - Value *S = IRB.CreateOr({S1S2, V1S2, S1V2}); if (ClPreciseDisjointOr && cast(&I)->isDisjoint()) { Value *V1V2 = IRB.CreateAnd(V1, V2); - S = IRB.CreateOr({S, V1V2}); + S = IRB.CreateOr(S, V1V2, "_ms_disjoint"); } setShadow(&I, S); diff --git a/llvm/test/Instrumentation/MemorySanitizer/or.ll b/llvm/test/Instrumentation/MemorySanitizer/or.ll index 2d51de13a8ebb..27a1800aa495b 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/or.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/or.ll @@ -45,7 +45,7 @@ define i8 @test_disjoint_or(i8 %a, i8 %b) sanitize_memory { ; CHECK-IMPRECISE: [[C:%.*]] = or disjoint i8 [[A]], [[B]] ; CHECK-IMPRECISE-NEXT: store i8 [[TMP11]], ptr @__msan_retval_tls, align 8 ; -; CHECK-PRECISE: [[TMP10:%.*]] = and i8 [[TMP3]], [[TMP4]] +; CHECK-PRECISE: [[TMP10:%.*]] = and i8 [[A]], [[B]] ; CHECK-PRECISE-NEXT: [[TMP12:%.*]] = or i8 [[TMP11]], [[TMP10]] ; CHECK-PRECISE-NEXT: [[C:%.*]] = or disjoint i8 [[A]], [[B]] ; CHECK-PRECISE-NEXT: store i8 [[TMP12]], ptr @__msan_retval_tls, align 8