diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index ea7c2203662bd..d4991bcba76f3 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -124,8 +124,6 @@ def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", [FeatureFPU]>; def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", "Enable the isel instruction">; -def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", - "Enable the bpermd instruction">; def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", "Enable extended divide instructions">; def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", @@ -394,7 +392,6 @@ def ProcessorFeatures { FeatureLDBRX, Feature64Bit, /* Feature64BitRegs, */ - FeatureBPERMD, FeatureExtDiv, FeatureMFTB, DeprecatedDST, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 99ef89a7fdc0c..0ce6079e2636d 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -739,7 +739,7 @@ def NoNaNsFPMath : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; def NaNsFPMath : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; -def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; +def HasBPERMD : Predicate<"Subtarget->getCPUDirective() >= PPC::DIR_PWR7">; def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;