diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 291f0c8c5d991..5d56a32be4958 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -26544,3 +26544,7 @@ bool AArch64TargetLowering::preferScalarizeSplat(SDNode *N) const { } return true; } + +unsigned AArch64TargetLowering::getMinimumJumpTableEntries() const { + return Subtarget->getMinimumJumpTableEntries(); +} diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 7332a95615a4d..f7d004fa3cbcc 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -1250,6 +1250,8 @@ class AArch64TargetLowering : public TargetLowering { SDLoc DL, EVT VT) const; bool preferScalarizeSplat(SDNode *N) const override; + + unsigned getMinimumJumpTableEntries() const override; }; namespace AArch64 { diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index e3c3bff8e3298..ff14fcf5dfcc0 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -77,6 +77,10 @@ static cl::opt "to authenticated LR during tail call"), cl::values(AUTH_CHECK_METHOD_CL_VALUES_LR)); +static cl::opt AArch64MinimumJumpTableEntries( + "aarch64-min-jump-table-entries", cl::init(13), cl::Hidden, + cl::desc("Set minimum number of entries to use a jump table on AArch64")); + unsigned AArch64Subtarget::getVectorInsertExtractBaseCost() const { if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0) return OverrideVectorInsertExtractBaseCost; @@ -84,7 +88,8 @@ unsigned AArch64Subtarget::getVectorInsertExtractBaseCost() const { } AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies( - StringRef FS, StringRef CPUString, StringRef TuneCPUString) { + StringRef FS, StringRef CPUString, StringRef TuneCPUString, + bool HasMinSize) { // Determine default and user-specified characteristics if (CPUString.empty()) @@ -94,12 +99,12 @@ AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies( TuneCPUString = CPUString; ParseSubtargetFeatures(CPUString, TuneCPUString, FS); - initializeProperties(); + initializeProperties(HasMinSize); return *this; } -void AArch64Subtarget::initializeProperties() { +void AArch64Subtarget::initializeProperties(bool HasMinSize) { // Initialize CPU specific properties. We should add a tablegen feature for // this in the future so we can specify it together with the subtarget // features. @@ -292,6 +297,9 @@ void AArch64Subtarget::initializeProperties() { MaxInterleaveFactor = 4; break; } + + if (AArch64MinimumJumpTableEntries.getNumOccurrences() > 0 || !HasMinSize) + MinimumJumpTableEntries = AArch64MinimumJumpTableEntries; } AArch64Subtarget::AArch64Subtarget(const Triple &TT, StringRef CPU, @@ -300,17 +308,17 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, StringRef CPU, unsigned MinSVEVectorSizeInBitsOverride, unsigned MaxSVEVectorSizeInBitsOverride, bool StreamingSVEMode, - bool StreamingCompatibleSVEMode) + bool StreamingCompatibleSVEMode, + bool HasMinSize) : AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS), ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()), ReserveXRegisterForRA(AArch64::GPR64commonRegClass.getNumRegs()), CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()), - IsLittle(LittleEndian), - StreamingSVEMode(StreamingSVEMode), + IsLittle(LittleEndian), StreamingSVEMode(StreamingSVEMode), StreamingCompatibleSVEMode(StreamingCompatibleSVEMode), MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride), MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT), - InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)), + InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU, HasMinSize)), TLInfo(TM, *this) { if (AArch64::isX18ReservedByDefault(TT)) ReserveXRegister.set(18); diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index b91c5c81ed4d2..b2ee2e76d0e8e 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -112,6 +112,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { Align PrefFunctionAlignment; Align PrefLoopAlignment; unsigned MaxBytesForLoopAlignment = 0; + unsigned MinimumJumpTableEntries = 4; unsigned MaxJumpTableSize = 0; // ReserveXRegister[i] - X#i is not available as a general purpose register. @@ -153,10 +154,11 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { /// subtarget initialization. AArch64Subtarget &initializeSubtargetDependencies(StringRef FS, StringRef CPUString, - StringRef TuneCPUString); + StringRef TuneCPUString, + bool HasMinSize); /// Initialize properties based on the selected processor family. - void initializeProperties(); + void initializeProperties(bool HasMinSize); public: /// This constructor initializes the data members to match that @@ -166,7 +168,8 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { unsigned MinSVEVectorSizeInBitsOverride = 0, unsigned MaxSVEVectorSizeInBitsOverride = 0, bool StreamingSVEMode = false, - bool StreamingCompatibleSVEMode = false); + bool StreamingCompatibleSVEMode = false, + bool HasMinSize = false); // Getters for SubtargetFeatures defined in tablegen #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ @@ -274,6 +277,9 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { } unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; } + unsigned getMinimumJumpTableEntries() const { + return MinimumJumpTableEntries; + } /// CPU has TBI (top byte of addresses is ignored during HW address /// translation) and OS enables it. diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 3d818c76bd4b7..d418a297218eb 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -397,6 +397,7 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const { StringRef CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString() : TargetCPU; StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString() : CPU; StringRef FS = FSAttr.isValid() ? FSAttr.getValueAsString() : TargetFS; + bool HasMinSize = F.hasMinSize(); bool StreamingSVEMode = F.hasFnAttribute("aarch64_pstate_sm_enabled") || F.hasFnAttribute("aarch64_pstate_sm_body"); @@ -432,8 +433,8 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const { << MaxSVEVectorSize << "StreamingSVEMode=" << StreamingSVEMode << "StreamingCompatibleSVEMode=" - << StreamingCompatibleSVEMode << CPU << TuneCPU - << FS; + << StreamingCompatibleSVEMode << CPU << TuneCPU << FS + << "HasMinSize=" << HasMinSize; auto &I = SubtargetMap[Key]; if (!I) { @@ -443,7 +444,8 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const { resetTargetOptions(F); I = std::make_unique( TargetTriple, CPU, TuneCPU, FS, *this, isLittle, MinSVEVectorSize, - MaxSVEVectorSize, StreamingSVEMode, StreamingCompatibleSVEMode); + MaxSVEVectorSize, StreamingSVEMode, StreamingCompatibleSVEMode, + HasMinSize); } assert((!StreamingSVEMode || I->hasSME()) && diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll index 4e4297b7a5e22..9371edd439fe4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple aarch64 -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -simplify-mir -verify-machineinstrs %s -o - 2>&1 | FileCheck %s +; RUN: llc -global-isel -mtriple aarch64 -aarch64-min-jump-table-entries=4 -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -simplify-mir -verify-machineinstrs %s -o - 2>&1 | FileCheck %s define i32 @switch(i32 %argc) { ; CHECK-LABEL: name: switch diff --git a/llvm/test/CodeGen/AArch64/arm64-jumptable.ll b/llvm/test/CodeGen/AArch64/arm64-jumptable.ll index d4ac9e72b28ff..7d9adf92a6a95 100644 --- a/llvm/test/CodeGen/AArch64/arm64-jumptable.ll +++ b/llvm/test/CodeGen/AArch64/arm64-jumptable.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s -; RUN: llc -mtriple=arm64-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-LINUX +; RUN: llc -mtriple=arm64-apple-ios -aarch64-min-jump-table-entries=4 < %s | FileCheck %s +; RUN: llc -mtriple=arm64-linux-gnu -aarch64-min-jump-table-entries=4 < %s | FileCheck %s --check-prefix=CHECK-LINUX ; define void @sum(i32 %a, ptr %to, i32 %c) { diff --git a/llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll b/llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll index d9ed54fb86bf1..e3e7f42526f78 100644 --- a/llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll +++ b/llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -o - | FileCheck %s +; RUN: llc %s -aarch64-min-jump-table-entries=4 -o - | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64" diff --git a/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll b/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll index 73b180dc4ae76..0f208f8ed9052 100644 --- a/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll +++ b/llvm/test/CodeGen/AArch64/implicit-def-subreg-to-reg-regression.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s +; RUN: llc -aarch64-min-jump-table-entries=4 -mtriple=arm64-apple-ios < %s | FileCheck %s ; Check there's no assert in spilling from implicit-def operands on an ; IMPLICIT_DEF. diff --git a/llvm/test/CodeGen/AArch64/jump-table-32.ll b/llvm/test/CodeGen/AArch64/jump-table-32.ll index d8572e901af29..e65813de8943e 100644 --- a/llvm/test/CodeGen/AArch64/jump-table-32.ll +++ b/llvm/test/CodeGen/AArch64/jump-table-32.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64_32-apple-ios7.0 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s +; RUN: llc -verify-machineinstrs -o - %s -aarch64-min-jump-table-entries=4 -mtriple=arm64_32-apple-ios7.0 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s define i32 @test_jumptable(i32 %in) { ; CHECK: test_jumptable diff --git a/llvm/test/CodeGen/AArch64/jump-table-exynos.ll b/llvm/test/CodeGen/AArch64/jump-table-exynos.ll index b5b400ecfbffc..61b0df5de2af3 100644 --- a/llvm/test/CodeGen/AArch64/jump-table-exynos.ll +++ b/llvm/test/CodeGen/AArch64/jump-table-exynos.ll @@ -1,5 +1,5 @@ -; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mattr=+force-32bit-jump-tables -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s -; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s +; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mattr=+force-32bit-jump-tables -aarch64-min-jump-table-entries=4 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s +; RUN: llc -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -aarch64-min-jump-table-entries=4 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s ; Exynos doesn't want jump tables to be compressed for now. diff --git a/llvm/test/CodeGen/AArch64/jump-table.ll b/llvm/test/CodeGen/AArch64/jump-table.ll index 6c32444657542..bb6c74b3b9df6 100644 --- a/llvm/test/CodeGen/AArch64/jump-table.ll +++ b/llvm/test/CodeGen/AArch64/jump-table.ll @@ -1,9 +1,9 @@ -; RUN: llc -no-integrated-as -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s -; RUN: llc -no-integrated-as -code-model=large -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-LARGE %s -; RUN: llc -no-integrated-as -code-model=large -relocation-model=pic -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-PIC %s -; RUN: llc -no-integrated-as -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic -aarch64-enable-atomic-cfg-tidy=0 -o - %s | FileCheck --check-prefix=CHECK-PIC %s -; RUN: llc -no-integrated-as -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-IOS %s -; RUN: llc -no-integrated-as -code-model=tiny -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-TINY %s +; RUN: llc -no-integrated-as -verify-machineinstrs -o - %s -aarch64-min-jump-table-entries=4 -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s +; RUN: llc -no-integrated-as -code-model=large -verify-machineinstrs -o - %s -aarch64-min-jump-table-entries=4 -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-LARGE %s +; RUN: llc -no-integrated-as -code-model=large -relocation-model=pic -o - %s -aarch64-min-jump-table-entries=4 -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-PIC %s +; RUN: llc -no-integrated-as -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic -aarch64-min-jump-table-entries=4 -aarch64-enable-atomic-cfg-tidy=0 -o - %s | FileCheck --check-prefix=CHECK-PIC %s +; RUN: llc -no-integrated-as -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios -aarch64-min-jump-table-entries=4 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-IOS %s +; RUN: llc -no-integrated-as -code-model=tiny -verify-machineinstrs -o - %s -aarch64-min-jump-table-entries=4 -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-TINY %s define i32 @test_jumptable(i32 %in) { ; CHECK: test_jumptable diff --git a/llvm/test/CodeGen/AArch64/max-jump-table.ll b/llvm/test/CodeGen/AArch64/max-jump-table.ll index d01924a9a5427..1268f5e6167ad 100644 --- a/llvm/test/CodeGen/AArch64/max-jump-table.ll +++ b/llvm/test/CodeGen/AArch64/max-jump-table.ll @@ -1,8 +1,8 @@ -; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t -; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t -; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t -; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=16 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK16 < %t -; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -mcpu=exynos-m3 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM3 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -aarch64-min-jump-table-entries=4 -jump-table-density=40 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -aarch64-min-jump-table-entries=4 -jump-table-density=40 -max-jump-table-size=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -aarch64-min-jump-table-entries=4 -jump-table-density=40 -max-jump-table-size=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -aarch64-min-jump-table-entries=4 -jump-table-density=40 -max-jump-table-size=16 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK16 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -aarch64-min-jump-table-entries=4 -jump-table-density=40 -mcpu=exynos-m3 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM3 < %t declare void @ext(i32, i32) diff --git a/llvm/test/CodeGen/AArch64/min-jump-table.ll b/llvm/test/CodeGen/AArch64/min-jump-table.ll index bf6bddf7b9c4f..98b89210f5a05 100644 --- a/llvm/test/CodeGen/AArch64/min-jump-table.ll +++ b/llvm/test/CodeGen/AArch64/min-jump-table.ll @@ -1,7 +1,9 @@ -; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=0 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t -; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=2 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK2 < %t -; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t -; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -aarch64-min-jump-table-entries=0 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -aarch64-min-jump-table-entries=2 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK2 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -aarch64-min-jump-table-entries=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -aarch64-min-jump-table-entries=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -aarch64-min-jump-table-entries=12 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK12 < %t +; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK-DEFAULT < %t declare void @ext(i32, i32) @@ -16,6 +18,8 @@ entry: ; CHECK2-NEXT: Jump Tables: ; CHECK4-NOT: {{^}}Jump Tables: ; CHECK8-NOT: {{^}}Jump Tables: +; CHECK12-NOT: {{^}}Jump Tables: +; CHECK-DEFAULT-NOT: {{^}}Jump Tables: bb1: tail call void @ext(i32 1, i32 0) br label %return bb2: tail call void @ext(i32 2, i32 2) br label %return @@ -36,6 +40,8 @@ entry: ; CHECK2-NEXT: Jump Tables: ; CHECK4-NEXT: Jump Tables: ; CHECK8-NOT: {{^}}Jump Tables: +; CHECK12-NOT: {{^}}Jump Tables: +; CHECK-DEFAULT-NOT: {{^}}Jump Tables: bb1: tail call void @ext(i32 1, i32 0) br label %return bb2: tail call void @ext(i32 3, i32 2) br label %return @@ -58,6 +64,123 @@ entry: i32 9, label %bb8 ] ; CHECK-LABEL: function jt8: +; CHECK0-NEXT: Jump Tables: +; CHECK2-NEXT: Jump Tables: +; CHECK4-NEXT: Jump Tables: +; CHECK8-NEXT: Jump Tables: +; CHECK12-NOT: Jump Tables: +; CHECK-DEFAULT-NOT: {{^}}Jump Tables: + +bb1: tail call void @ext(i32 1, i32 0) br label %return +bb2: tail call void @ext(i32 2, i32 2) br label %return +bb3: tail call void @ext(i32 3, i32 4) br label %return +bb4: tail call void @ext(i32 4, i32 6) br label %return +bb5: tail call void @ext(i32 5, i32 8) br label %return +bb6: tail call void @ext(i32 6, i32 10) br label %return +bb7: tail call void @ext(i32 7, i32 12) br label %return +bb8: tail call void @ext(i32 8, i32 14) br label %return + +return: ret i32 %b +} + +define i32 @jt12(i32 %a, i32 %b) { +entry: + switch i32 %a, label %return [ + i32 1, label %bb1 + i32 2, label %bb2 + i32 3, label %bb3 + i32 4, label %bb4 + i32 5, label %bb5 + i32 6, label %bb6 + i32 7, label %bb7 + i32 8, label %bb8 + i32 9, label %bb9 + i32 10, label %bb10 + i32 11, label %bb11 + i32 12, label %bb12 + ] +; CHECK-LABEL: function jt12: +; CHECK0-NEXT: Jump Tables: +; CHECK2-NEXT: Jump Tables: +; CHECK4-NEXT: Jump Tables: +; CHECK8-NEXT: Jump Tables: +; CHECK12-NEXT: Jump Tables: +; CHECK-DEFAULT-NOT: {{^}}Jump Tables: + +bb1: tail call void @ext(i32 1, i32 0) br label %return +bb2: tail call void @ext(i32 2, i32 2) br label %return +bb3: tail call void @ext(i32 3, i32 4) br label %return +bb4: tail call void @ext(i32 4, i32 6) br label %return +bb5: tail call void @ext(i32 5, i32 8) br label %return +bb6: tail call void @ext(i32 6, i32 10) br label %return +bb7: tail call void @ext(i32 7, i32 12) br label %return +bb8: tail call void @ext(i32 8, i32 14) br label %return +bb9: tail call void @ext(i32 9, i32 16) br label %return +bb10: tail call void @ext(i32 10, i32 18) br label %return +bb11: tail call void @ext(i32 11, i32 20) br label %return +bb12: tail call void @ext(i32 12, i32 22) br label %return + +return: ret i32 %b +} + +define i32 @jt12_min_size(i32 %a, i32 %b) minsize { +entry: + switch i32 %a, label %return [ + i32 1, label %bb1 + i32 2, label %bb2 + i32 3, label %bb3 + i32 4, label %bb4 + i32 5, label %bb5 + i32 6, label %bb6 + i32 7, label %bb7 + i32 8, label %bb8 + i32 9, label %bb9 + i32 10, label %bb10 + i32 11, label %bb11 + i32 12, label %bb12 + ] +; CHECK-LABEL: function jt12_min_size: +; CHECK0-NEXT: Jump Tables: +; CHECK2-NEXT: Jump Tables: +; CHECK4-NEXT: Jump Tables: +; CHECK8-NEXT: Jump Tables: +; CHECK12-NEXT: Jump Tables: +; CHECK-DEFAULT: Jump Tables: + +bb1: tail call void @ext(i32 1, i32 0) br label %return +bb2: tail call void @ext(i32 2, i32 2) br label %return +bb3: tail call void @ext(i32 3, i32 4) br label %return +bb4: tail call void @ext(i32 4, i32 6) br label %return +bb5: tail call void @ext(i32 5, i32 8) br label %return +bb6: tail call void @ext(i32 6, i32 10) br label %return +bb7: tail call void @ext(i32 7, i32 12) br label %return +bb8: tail call void @ext(i32 8, i32 14) br label %return +bb9: tail call void @ext(i32 9, i32 16) br label %return +bb10: tail call void @ext(i32 10, i32 18) br label %return +bb11: tail call void @ext(i32 11, i32 20) br label %return +bb12: tail call void @ext(i32 12, i32 22) br label %return + +return: ret i32 %b +} + +define i32 @jt13(i32 %a, i32 %b) { +entry: + switch i32 %a, label %return [ + i32 1, label %bb1 + i32 2, label %bb2 + i32 3, label %bb3 + i32 4, label %bb4 + i32 5, label %bb5 + i32 6, label %bb6 + i32 7, label %bb7 + i32 8, label %bb8 + i32 9, label %bb9 + i32 10, label %bb10 + i32 11, label %bb11 + i32 12, label %bb12 + i32 13, label %bb13 + ] +; CHECK-LABEL: function jt13: ; CHECK-NEXT: Jump Tables: bb1: tail call void @ext(i32 1, i32 0) br label %return @@ -68,6 +191,11 @@ bb5: tail call void @ext(i32 5, i32 8) br label %return bb6: tail call void @ext(i32 6, i32 10) br label %return bb7: tail call void @ext(i32 7, i32 12) br label %return bb8: tail call void @ext(i32 8, i32 14) br label %return +bb9: tail call void @ext(i32 9, i32 16) br label %return +bb10: tail call void @ext(i32 10, i32 18) br label %return +bb11: tail call void @ext(i32 11, i32 20) br label %return +bb12: tail call void @ext(i32 12, i32 22) br label %return +bb13: tail call void @ext(i32 13, i32 24) br label %return return: ret i32 %b } diff --git a/llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll b/llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll index 15657730c2cdc..106f6bb856b6b 100644 --- a/llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll +++ b/llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s +; RUN: llc -mtriple=aarch64 -aarch64-min-jump-table-entries=4 %s -o - | FileCheck %s define void @f0() "patchable-function-entry"="0" "branch-target-enforcement"="true" { ; CHECK-LABEL: f0: diff --git a/llvm/test/CodeGen/AArch64/redundant-mov-from-zero-extend.ll b/llvm/test/CodeGen/AArch64/redundant-mov-from-zero-extend.ll index c150cb889313a..caa28b31a6f65 100644 --- a/llvm/test/CodeGen/AArch64/redundant-mov-from-zero-extend.ll +++ b/llvm/test/CodeGen/AArch64/redundant-mov-from-zero-extend.ll @@ -11,33 +11,37 @@ define i32 @test(i32 %input, i32 %n, i32 %a) { ; CHECK-NEXT: .LBB0_2: // %bb.0 ; CHECK-NEXT: add w8, w0, w1 ; CHECK-NEXT: mov w0, #100 // =0x64 -; CHECK-NEXT: cmp w8, #4 -; CHECK-NEXT: b.hi .LBB0_5 +; CHECK-NEXT: cmp w8, #1 +; CHECK-NEXT: b.le .LBB0_7 ; CHECK-NEXT: // %bb.3: // %bb.0 -; CHECK-NEXT: adrp x9, .LJTI0_0 -; CHECK-NEXT: add x9, x9, :lo12:.LJTI0_0 -; CHECK-NEXT: adr x10, .LBB0_4 -; CHECK-NEXT: ldrb w11, [x9, x8] -; CHECK-NEXT: add x10, x10, x11, lsl #2 -; CHECK-NEXT: br x10 -; CHECK-NEXT: .LBB0_4: // %sw.bb -; CHECK-NEXT: add w0, w2, #1 -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB0_5: // %bb.0 +; CHECK-NEXT: cmp w8, #2 +; CHECK-NEXT: b.eq .LBB0_10 +; CHECK-NEXT: // %bb.4: // %bb.0 +; CHECK-NEXT: cmp w8, #4 +; CHECK-NEXT: b.eq .LBB0_11 +; CHECK-NEXT: // %bb.5: // %bb.0 ; CHECK-NEXT: cmp w8, #200 -; CHECK-NEXT: b.ne .LBB0_9 +; CHECK-NEXT: b.ne .LBB0_12 ; CHECK-NEXT: // %bb.6: // %sw.bb7 ; CHECK-NEXT: add w0, w2, #7 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB0_7: // %sw.bb3 +; CHECK-NEXT: .LBB0_7: // %bb.0 +; CHECK-NEXT: cbz w8, .LBB0_13 +; CHECK-NEXT: // %bb.8: // %bb.0 +; CHECK-NEXT: cmp w8, #1 +; CHECK-NEXT: b.ne .LBB0_12 +; CHECK-NEXT: // %bb.9: // %sw.bb1 +; CHECK-NEXT: add w0, w2, #3 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB0_10: // %sw.bb3 ; CHECK-NEXT: add w0, w2, #4 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB0_8: // %sw.bb5 +; CHECK-NEXT: .LBB0_11: // %sw.bb5 ; CHECK-NEXT: add w0, w2, #5 -; CHECK-NEXT: .LBB0_9: // %return +; CHECK-NEXT: .LBB0_12: // %return ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB0_10: // %sw.bb1 -; CHECK-NEXT: add w0, w2, #3 +; CHECK-NEXT: .LBB0_13: // %sw.bb +; CHECK-NEXT: add w0, w2, #1 ; CHECK-NEXT: ret entry: %b = add nsw i32 %input, %n @@ -77,3 +81,4 @@ return: %retval.0 = phi i32 [ %add8, %sw.bb7 ], [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add2, %sw.bb1 ], [ %add, %sw.bb ], [ 100, %bb.0 ], [ 0, %entry ] ret i32 %retval.0 } + diff --git a/llvm/test/CodeGen/AArch64/switch-unreachable-default.ll b/llvm/test/CodeGen/AArch64/switch-unreachable-default.ll index 9acc5a150b630..949485bf52f2e 100644 --- a/llvm/test/CodeGen/AArch64/switch-unreachable-default.ll +++ b/llvm/test/CodeGen/AArch64/switch-unreachable-default.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -o - %s | FileCheck %s +; RUN: llc -O3 -aarch64-min-jump-table-entries=4 -o - %s | FileCheck %s ; Test that the output in the presence of an unreachable default does not have ; a compare and branch at the top of the switch to handle the default case. diff --git a/llvm/test/CodeGen/AArch64/win64-jumptable.ll b/llvm/test/CodeGen/AArch64/win64-jumptable.ll index 0b9b7deceae11..f9f2b0bf0ca5c 100644 --- a/llvm/test/CodeGen/AArch64/win64-jumptable.ll +++ b/llvm/test/CodeGen/AArch64/win64-jumptable.ll @@ -1,5 +1,5 @@ -; RUN: llc -o - %s -mtriple=aarch64-windows -aarch64-enable-compress-jump-tables=0 | FileCheck %s -; RUN: llc -o - %s -mtriple=aarch64-windows -aarch64-enable-compress-jump-tables=0 -filetype=obj | llvm-readobj --unwind - | FileCheck %s -check-prefix=UNWIND +; RUN: llc -o - %s -mtriple=aarch64-windows -aarch64-min-jump-table-entries=4 -aarch64-enable-compress-jump-tables=0 | FileCheck %s +; RUN: llc -o - %s -mtriple=aarch64-windows -aarch64-min-jump-table-entries=4 -aarch64-enable-compress-jump-tables=0 -filetype=obj | llvm-readobj --unwind - | FileCheck %s -check-prefix=UNWIND define void @f(i32 %x) { entry: diff --git a/llvm/test/CodeGen/AArch64/wineh-bti.ll b/llvm/test/CodeGen/AArch64/wineh-bti.ll index edf3699d52fd2..a73f4d219bc31 100644 --- a/llvm/test/CodeGen/AArch64/wineh-bti.ll +++ b/llvm/test/CodeGen/AArch64/wineh-bti.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=aarch64-windows | FileCheck %s +; RUN: llc < %s -mtriple=aarch64-windows -aarch64-min-jump-table-entries=4 | FileCheck %s define dso_local i32 @func(i32 %in) { entry: diff --git a/llvm/test/CodeGen/Generic/machine-function-splitter.ll b/llvm/test/CodeGen/Generic/machine-function-splitter.ll index 364eadd64c755..a236f201eaafc 100644 --- a/llvm/test/CodeGen/Generic/machine-function-splitter.ll +++ b/llvm/test/CodeGen/Generic/machine-function-splitter.ll @@ -8,10 +8,10 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -split-machine-functions -mfs-split-ehcode | FileCheck %s -check-prefixes=MFS-EH-SPLIT,MFS-EH-SPLIT-X86 ; RUN: llc < %s -mtriple=x86_64 -split-machine-functions -O0 -mfs-psi-cutoff=0 -mfs-count-threshold=10000 | FileCheck %s -check-prefixes=MFS-O0,MFS-O0-X86 -; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -enable-split-machine-functions | FileCheck %s -check-prefixes=MFS-DEFAULTS,MFS-DEFAULTS-AARCH64 -; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -enable-split-machine-functions -mfs-psi-cutoff=0 -mfs-count-threshold=2000 | FileCheck %s --dump-input=always -check-prefixes=MFS-OPTS1,MFS-OPTS1-AARCH64 -; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -enable-split-machine-functions -mfs-psi-cutoff=950000 | FileCheck %s -check-prefixes=MFS-OPTS2,MFS-OPTS2-AARCH64 -; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -enable-split-machine-functions -mfs-split-ehcode | FileCheck %s -check-prefixes=MFS-EH-SPLIT,MFS-EH-SPLIT-AARCH64 +; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -aarch64-min-jump-table-entries=4 -enable-split-machine-functions | FileCheck %s -check-prefixes=MFS-DEFAULTS,MFS-DEFAULTS-AARCH64 +; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -aarch64-min-jump-table-entries=4 -enable-split-machine-functions -mfs-psi-cutoff=0 -mfs-count-threshold=2000 | FileCheck %s --dump-input=always -check-prefixes=MFS-OPTS1,MFS-OPTS1-AARCH64 +; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -aarch64-min-jump-table-entries=4 -enable-split-machine-functions -mfs-psi-cutoff=950000 | FileCheck %s -check-prefixes=MFS-OPTS2,MFS-OPTS2-AARCH64 +; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -aarch64-min-jump-table-entries=4 -enable-split-machine-functions -mfs-split-ehcode | FileCheck %s -check-prefixes=MFS-EH-SPLIT,MFS-EH-SPLIT-AARCH64 ; RUN: llc < %s -mtriple=aarch64 -enable-split-machine-functions -aarch64-redzone | FileCheck %s -check-prefixes=MFS-REDZONE-AARCH64 ; COM: Machine function splitting with AFDO profiles diff --git a/llvm/test/DebugInfo/COFF/jump-table.ll b/llvm/test/DebugInfo/COFF/jump-table.ll index a1f16f48962f9..4d16c78c97882 100644 --- a/llvm/test/DebugInfo/COFF/jump-table.ll +++ b/llvm/test/DebugInfo/COFF/jump-table.ll @@ -3,7 +3,7 @@ ; REQUIRES: x86-registered-target ; RUN: llc -mtriple=i686-windows < %s | FileCheck %s --check-prefixes=CHECK,I686,NOTA32 ; RUN: llc -mtriple=x86_64-windows < %s | FileCheck %s --check-prefixes=CHECK,X64,NOTA32 -; RUN: llc -mtriple=aarch64-windows < %s | FileCheck %s --check-prefixes=CHECK,A64,NOTA32 +; RUN: llc -mtriple=aarch64-windows -aarch64-min-jump-table-entries=4 < %s | FileCheck %s --check-prefixes=CHECK,A64,NOTA32 ; RUN: llc -mtriple=thumbv7a-windows < %s | FileCheck %s --check-prefixes=CHECK,A32 ; RUN: llc -mtriple=x86_64-windows -filetype=obj < %s | llvm-readobj - --codeview | FileCheck %s --check-prefixes=CV