From 65fc6f3b626b78f2d8a377384f2befb92b187d3c Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Fri, 5 Jan 2024 01:46:33 -0500 Subject: [PATCH 1/4] [RISCV][GlobalISel] Zbkb support for G_BSWAP This instructions is legal in the presence of Zbkb extension. --- .../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 2 +- .../instruction-select/bswap-rv32.mir | 3 + .../instruction-select/bswap-rv64.mir | 3 + .../legalizer/legalize-bswap-rv32.mir | 58 ++++++++++--------- .../legalizer/legalize-bswap-rv64.mir | 58 ++++++++++--------- 5 files changed, 67 insertions(+), 57 deletions(-) diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp index 61bae58649258..ab8070772fe54 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp @@ -113,7 +113,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower(); auto &BSWAPActions = getActionDefinitionsBuilder(G_BSWAP); - if (ST.hasStdExtZbb()) + if (ST.hasStdExtZbb() || ST.hasStdExtZbkb()) BSWAPActions.legalFor({sXLen}).clampScalar(0, sXLen, sXLen); else BSWAPActions.maxScalar(0, sXLen).lower(); diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir index 733fd128282e0..fd6d7b4163524 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir @@ -2,6 +2,9 @@ # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ # RUN: -simplify-mir -verify-machineinstrs %s -o - \ # RUN: | FileCheck -check-prefix=RV32I %s +# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV32I %s --- name: bswap_s32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir index 053abef93a3a1..334d728b64c7b 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir @@ -2,6 +2,9 @@ # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ # RUN: -simplify-mir -verify-machineinstrs %s -o - \ # RUN: | FileCheck -check-prefix=RV64I %s +# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \ +# RUN: -simplify-mir -verify-machineinstrs %s -o - \ +# RUN: | FileCheck -check-prefix=RV64I %s --- name: bswap_s64 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir index e66dbfa4c8210..d6598c89b39af 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir @@ -2,7 +2,9 @@ # RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \ # RUN: | FileCheck %s --check-prefix=RV32I # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \ -# RUN: | FileCheck %s --check-prefix=RV32ZBB +# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB +# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB --- name: bswap_i16 @@ -23,16 +25,16 @@ body: | ; RV32I-NEXT: $x10 = COPY [[AND]](s32) ; RV32I-NEXT: PseudoRET implicit $x10 ; - ; RV32ZBB-LABEL: name: bswap_i16 - ; RV32ZBB: liveins: $x10 - ; RV32ZBB-NEXT: {{ $}} - ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 - ; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16 - ; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]] - ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; RV32ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32) - ; RV32ZBB-NEXT: $x10 = COPY [[LSHR]](s32) - ; RV32ZBB-NEXT: PseudoRET implicit $x10 + ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i16 + ; RV32ZBB_OR_RV32ZBKB: liveins: $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}} + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]] + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[LSHR]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10 %0:_(s32) = COPY $x10 %1:_(s32) = G_ASSERT_ZEXT %0, 16 %2:_(s16) = G_TRUNC %1(s32) @@ -65,13 +67,13 @@ body: | ; RV32I-NEXT: $x10 = COPY [[OR2]](s32) ; RV32I-NEXT: PseudoRET implicit $x10 ; - ; RV32ZBB-LABEL: name: bswap_i32 - ; RV32ZBB: liveins: $x10 - ; RV32ZBB-NEXT: {{ $}} - ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 - ; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]] - ; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32) - ; RV32ZBB-NEXT: PseudoRET implicit $x10 + ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i32 + ; RV32ZBB_OR_RV32ZBKB: liveins: $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}} + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]] + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10 %0:_(s32) = COPY $x10 %1:_(s32) = G_BSWAP %0 $x10 = COPY %1(s32) @@ -115,16 +117,16 @@ body: | ; RV32I-NEXT: $x11 = COPY [[OR5]](s32) ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11 ; - ; RV32ZBB-LABEL: name: bswap_i64 - ; RV32ZBB: liveins: $x10, $x11 - ; RV32ZBB-NEXT: {{ $}} - ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 - ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 - ; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]] - ; RV32ZBB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]] - ; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32) - ; RV32ZBB-NEXT: $x11 = COPY [[BSWAP1]](s32) - ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11 + ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i64 + ; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11 + ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}} + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]] + ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]] + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: $x11 = COPY [[BSWAP1]](s32) + ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10, implicit $x11 %0:_(s32) = COPY $x10 %1:_(s32) = COPY $x11 %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir index b73a22c1a07ea..61a0de9739842 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir @@ -2,7 +2,9 @@ # RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ # RUN: | FileCheck %s --check-prefix=RV64I # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \ -# RUN: | FileCheck %s --check-prefix=RV64ZBB +# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB +# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB --- name: bswap_i16 @@ -27,16 +29,16 @@ body: | ; RV64I-NEXT: $x10 = COPY [[AND]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; - ; RV64ZBB-LABEL: name: bswap_i16 - ; RV64ZBB: liveins: $x10 - ; RV64ZBB-NEXT: {{ $}} - ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16 - ; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]] - ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 - ; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64) - ; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64) - ; RV64ZBB-NEXT: PseudoRET implicit $x10 + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i16 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]] + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = G_ASSERT_ZEXT %0, 16 %2:_(s16) = G_TRUNC %1(s64) @@ -74,16 +76,16 @@ body: | ; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; - ; RV64ZBB-LABEL: name: bswap_i32 - ; RV64ZBB: liveins: $x10 - ; RV64ZBB-NEXT: {{ $}} - ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32 - ; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]] - ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 - ; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64) - ; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64) - ; RV64ZBB-NEXT: PseudoRET implicit $x10 + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i32 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]] + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = G_ASSERT_ZEXT %0, 32 %2:_(s32) = G_TRUNC %1(s64) @@ -132,13 +134,13 @@ body: | ; RV64I-NEXT: $x10 = COPY [[OR6]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; - ; RV64ZBB-LABEL: name: bswap_i64 - ; RV64ZBB: liveins: $x10 - ; RV64ZBB-NEXT: {{ $}} - ; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]] - ; RV64ZBB-NEXT: $x10 = COPY [[BSWAP]](s64) - ; RV64ZBB-NEXT: PseudoRET implicit $x10 + ; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i64 + ; RV64ZBB_OR_RV64ZBKB: liveins: $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}} + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]] + ; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[BSWAP]](s64) + ; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = G_BSWAP %0 $x10 = COPY %1(s64) From a5dc534689e22dd92b30745bb9a9e220689e7ba1 Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Fri, 5 Jan 2024 16:19:08 -0500 Subject: [PATCH 2/4] Changed some filckeck prefixes to default "CHECK". --- .../GlobalISel/instruction-select/bswap-rv32.mir | 14 +++++++------- .../GlobalISel/instruction-select/bswap-rv64.mir | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir index fd6d7b4163524..898362e7336b0 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir @@ -1,10 +1,10 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ # RUN: -simplify-mir -verify-machineinstrs %s -o - \ -# RUN: | FileCheck -check-prefix=RV32I %s +# RUN: | FileCheck %s # RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \ # RUN: -simplify-mir -verify-machineinstrs %s -o - \ -# RUN: | FileCheck -check-prefix=RV32I %s +# RUN: | FileCheck %s --- name: bswap_s32 @@ -12,11 +12,11 @@ legalized: true regBankSelected: true body: | bb.0.entry: - ; RV32I-LABEL: name: bswap_s32 - ; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10 - ; RV32I-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]] - ; RV32I-NEXT: $x10 = COPY [[REV8_RV32_]] - ; RV32I-NEXT: PseudoRET implicit $x10 + ; CHECK-LABEL: name: bswap_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[REV8_RV32_]] + ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(s32) = COPY $x10 %1:gprb(s32) = G_BSWAP %0 $x10 = COPY %1(s32) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir index 334d728b64c7b..ac3065ee12bb1 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir @@ -1,10 +1,10 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ # RUN: -simplify-mir -verify-machineinstrs %s -o - \ -# RUN: | FileCheck -check-prefix=RV64I %s +# RUN: | FileCheck %s # RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \ # RUN: -simplify-mir -verify-machineinstrs %s -o - \ -# RUN: | FileCheck -check-prefix=RV64I %s +# RUN: | FileCheck %s --- name: bswap_s64 @@ -12,11 +12,11 @@ legalized: true regBankSelected: true body: | bb.0.entry: - ; RV64I-LABEL: name: bswap_s64 - ; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10 - ; RV64I-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]] - ; RV64I-NEXT: $x10 = COPY [[REV8_RV64_]] - ; RV64I-NEXT: PseudoRET implicit $x10 + ; CHECK-LABEL: name: bswap_s64 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]] + ; CHECK-NEXT: $x10 = COPY [[REV8_RV64_]] + ; CHECK-NEXT: PseudoRET implicit $x10 %0:gprb(s64) = COPY $x10 %1:gprb(s64) = G_BSWAP %0 $x10 = COPY %1(s64) From 283702d6768e6d112338c256ef43a4d0d89f2526 Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Fri, 5 Jan 2024 16:58:18 -0500 Subject: [PATCH 3/4] Put run commands on the same line. --- .../RISCV/GlobalISel/instruction-select/bswap-rv32.mir | 6 ++---- .../RISCV/GlobalISel/instruction-select/bswap-rv64.mir | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir index 898362e7336b0..721721cf361ea 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir @@ -1,10 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \ -# RUN: -simplify-mir -verify-machineinstrs %s -o - \ -# RUN: | FileCheck %s +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \ -# RUN: -simplify-mir -verify-machineinstrs %s -o - \ -# RUN: | FileCheck %s +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --- name: bswap_s32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir index ac3065ee12bb1..6cdfb76f0b47d 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir @@ -1,10 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \ -# RUN: -simplify-mir -verify-machineinstrs %s -o - \ -# RUN: | FileCheck %s +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \ -# RUN: -simplify-mir -verify-machineinstrs %s -o - \ -# RUN: | FileCheck %s +# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --- name: bswap_s64 From 32b6b536a8ef9604283f9bc1d146deab3c98ec24 Mon Sep 17 00:00:00 2001 From: Mikhail Gudim Date: Fri, 5 Jan 2024 22:16:43 -0500 Subject: [PATCH 4/4] Empty commit to restart CI.