From ca41da40571fe19153a891ab1eeab427d9271da2 Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Sun, 14 Jan 2024 22:29:10 -0500 Subject: [PATCH 1/9] GISel support is in progress for G_LOAD --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index c3d1416ed518d..4bfd4d0386a86 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -20909,7 +20909,7 @@ bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const { if (Op == Instruction::Add || Op == Instruction::Sub || Op == Instruction::And || Op == Instruction::Or || Op == Instruction::Xor || Op == Instruction::InsertElement || - Op == Instruction::Xor || Op == Instruction::ShuffleVector) + Op == Instruction::ShuffleVector || Op == Instruction::Load) return false; if (Inst.getType()->isScalableTy()) From 5fb8065d6d1fb244fe11b319632fc821a5b1ea05 Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Mon, 29 Jan 2024 20:40:01 -0500 Subject: [PATCH 2/9] change the type of StoreSize to be TypeSize --- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 47ee2ee507137..938dc3b8bc638 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1363,9 +1363,8 @@ static bool isSwiftError(const Value *V) { bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) { const LoadInst &LI = cast(U); - - unsigned StoreSize = DL->getTypeStoreSize(LI.getType()); - if (StoreSize == 0) + TypeSize StoreSize = DL->getTypeStoreSize(LI.getType()); + if (StoreSize.isZero()) return true; ArrayRef Regs = getOrCreateVRegs(LI); From ba22af9d1ced8139f57f218abe5bb7ca4a96d9e0 Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Tue, 30 Jan 2024 08:57:38 -0500 Subject: [PATCH 3/9] simple test case for scalable vector load --- llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll new file mode 100644 index 0000000000000..5f98c6a7066c7 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll @@ -0,0 +1,7 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32I %s + +define void @vload_vint8m1(ptr %pa) { + %va = load , ptr %pa + ret void +} From c39ba13ebae72a06ea26ae1e3b5c168da6027b70 Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Tue, 30 Jan 2024 10:42:03 -0500 Subject: [PATCH 4/9] add test check for this simplest test case --- .../CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll index 5f98c6a7066c7..faf360a5a97db 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll @@ -2,6 +2,13 @@ ; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32I %s define void @vload_vint8m1(ptr %pa) { - %va = load , ptr %pa - ret void + ; RV32I-LABEL: name: vload_vint8m1 + ; RV32I: bb.1 (%ir-block.0): + ; RV32I-NEXT: liveins: $x10 + ; RV32I-NEXT: {{ $}} + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32I-NEXT: PseudoRET + %va = load , ptr %pa, align 8 + ret void } From 20f55a5abdd125c0e4de48a98fda31033d8a599d Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Tue, 30 Jan 2024 10:42:49 -0500 Subject: [PATCH 5/9] have comprehensive test for all vector types and both rv32/64 --- .../RISCV/GlobalISel/irtranslator/vec-ld.ll | 498 +++++++++++++++++- 1 file changed, 486 insertions(+), 12 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll index faf360a5a97db..c90572d04e30c 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll @@ -1,14 +1,488 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32I %s - -define void @vload_vint8m1(ptr %pa) { - ; RV32I-LABEL: name: vload_vint8m1 - ; RV32I: bb.1 (%ir-block.0): - ; RV32I-NEXT: liveins: $x10 - ; RV32I-NEXT: {{ $}} - ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) - ; RV32I-NEXT: PseudoRET - %va = load , ptr %pa, align 8 - ret void +; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s +; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s + +define @vload_nx1i8(ptr %pa) { + ; RV32-LABEL: name: vload_nx1i8 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx1i8 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx2i8(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i8 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx2i8 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx4i8(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i8 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx4i8 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx8i8(ptr %pa) { + ; RV32-LABEL: name: vload_nx8i8 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx8i8 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx16i8(ptr %pa) { + ; RV32-LABEL: name: vload_nx16i8 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx16i8 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa + ret %va +} + +define @vload_nx32i8(ptr %pa) { + ; RV32-LABEL: name: vload_nx32i8 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8m4 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: vload_nx32i8 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %va = load , ptr %pa + ret %va +} + +define @vload_nx64i8(ptr %pa) { + ; RV32-LABEL: name: vload_nx64i8 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8m8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: vload_nx64i8 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx1i16(ptr %pa) { + ; RV32-LABEL: name: vload_nx1i16 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx1i16 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx2i16(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i16 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx2i16 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx4i16(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx4i16 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx8i16(ptr %pa) { + ; RV32-LABEL: name: vload_nx8i16 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx8i16 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa + ret %va +} + +define @vload_nx16i16(ptr %pa) { + ; RV32-LABEL: name: vload_nx16i16 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: $v8m4 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: vload_nx16i16 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %va = load , ptr %pa + ret %va +} + +define @vload_nx32i16(ptr %pa) { + ; RV32-LABEL: name: vload_nx32i16 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: $v8m8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: vload_nx32i16 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx1i32(ptr %pa) { + ; RV32-LABEL: name: vload_nx1i32 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx1i32 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx2i32(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i32 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx2i32 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx4i32(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i32 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx4i32 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa + ret %va +} + +define @vload_nx8i32(ptr %pa) { + ; RV32-LABEL: name: vload_nx8i32 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: $v8m4 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: vload_nx8i32 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %va = load , ptr %pa + ret %va } + +define @vload_nx16i32(ptr %pa) { + ; RV32-LABEL: name: vload_nx16i32 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: $v8m8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: vload_nx16i32 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx1i64(ptr %pa) { + ; RV32-LABEL: name: vload_nx1i64 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx1i64 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx2i64(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i64 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx2i64 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa + ret %va +} + +define @vload_nx4i64(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i64 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: $v8m4 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: vload_nx4i64 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m4 + %va = load , ptr %pa + ret %va +} + +define @vload_nx8i64(ptr %pa) { + ; RV32-LABEL: name: vload_nx8i64 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: $v8m8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m8 + ; + ; RV64-LABEL: name: vload_nx8i64 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %va = load , ptr %pa + ret %va +} + From 5b7d82683150592a4d2dacc70c46b8d6ff72074c Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Wed, 28 Feb 2024 13:41:44 -0500 Subject: [PATCH 6/9] update test cases --- .../RISCV/GlobalISel/irtranslator/vec-ld.ll | 60 +++++++++---------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll index c90572d04e30c..84e747f8957b2 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll @@ -162,7 +162,7 @@ define @vload_nx1i16(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; @@ -171,7 +171,7 @@ define @vload_nx1i16(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa @@ -184,7 +184,7 @@ define @vload_nx2i16(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; @@ -193,7 +193,7 @@ define @vload_nx2i16(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa @@ -206,7 +206,7 @@ define @vload_nx4i16(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; @@ -215,7 +215,7 @@ define @vload_nx4i16(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa @@ -228,7 +228,7 @@ define @vload_nx8i16(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m2 ; @@ -237,7 +237,7 @@ define @vload_nx8i16(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %va = load , ptr %pa @@ -250,7 +250,7 @@ define @vload_nx16i16(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m4 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m4 ; @@ -259,7 +259,7 @@ define @vload_nx16i16(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %va = load , ptr %pa @@ -272,7 +272,7 @@ define @vload_nx32i16(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m8 ; @@ -281,7 +281,7 @@ define @vload_nx32i16(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %va = load , ptr %pa @@ -294,7 +294,7 @@ define @vload_nx1i32(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; @@ -303,7 +303,7 @@ define @vload_nx1i32(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa @@ -316,7 +316,7 @@ define @vload_nx2i32(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; @@ -325,7 +325,7 @@ define @vload_nx2i32(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa @@ -338,7 +338,7 @@ define @vload_nx4i32(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m2 ; @@ -347,7 +347,7 @@ define @vload_nx4i32(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %va = load , ptr %pa @@ -360,7 +360,7 @@ define @vload_nx8i32(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m4 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m4 ; @@ -369,7 +369,7 @@ define @vload_nx8i32(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %va = load , ptr %pa @@ -382,7 +382,7 @@ define @vload_nx16i32(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m8 ; @@ -391,7 +391,7 @@ define @vload_nx16i32(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %va = load , ptr %pa @@ -404,7 +404,7 @@ define @vload_nx1i64(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; @@ -413,7 +413,7 @@ define @vload_nx1i64(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa @@ -426,7 +426,7 @@ define @vload_nx2i64(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m2 ; @@ -435,7 +435,7 @@ define @vload_nx2i64(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %va = load , ptr %pa @@ -448,7 +448,7 @@ define @vload_nx4i64(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m4 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m4 ; @@ -457,7 +457,7 @@ define @vload_nx4i64(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %va = load , ptr %pa @@ -470,7 +470,7 @@ define @vload_nx8i64(ptr %pa) { ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m8 ; @@ -479,7 +479,7 @@ define @vload_nx8i64(ptr %pa) { ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %va = load , ptr %pa From 27ccfbe240811ed159f86bdcab0d972e5e4aff85 Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Wed, 28 Feb 2024 14:37:59 -0500 Subject: [PATCH 7/9] add align argument --- .../RISCV/GlobalISel/irtranslator/vec-ld.ll | 374 ++++++++++++++++-- 1 file changed, 352 insertions(+), 22 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll index 84e747f8957b2..f9a9ed9ae4499 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll @@ -21,7 +21,7 @@ define @vload_nx1i8(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx2i8(ptr %pa) { @@ -43,7 +43,7 @@ define @vload_nx2i8(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx4i8(ptr %pa) { @@ -65,7 +65,7 @@ define @vload_nx4i8(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx8i8(ptr %pa) { @@ -87,7 +87,7 @@ define @vload_nx8i8(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx16i8(ptr %pa) { @@ -109,7 +109,7 @@ define @vload_nx16i8(ptr %pa) { ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx32i8(ptr %pa) { @@ -131,7 +131,7 @@ define @vload_nx32i8(ptr %pa) { ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx64i8(ptr %pa) { @@ -153,7 +153,7 @@ define @vload_nx64i8(ptr %pa) { ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx1i16(ptr %pa) { @@ -175,7 +175,7 @@ define @vload_nx1i16(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx2i16(ptr %pa) { @@ -197,7 +197,7 @@ define @vload_nx2i16(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx4i16(ptr %pa) { @@ -219,7 +219,7 @@ define @vload_nx4i16(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx8i16(ptr %pa) { @@ -241,7 +241,7 @@ define @vload_nx8i16(ptr %pa) { ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx16i16(ptr %pa) { @@ -263,7 +263,7 @@ define @vload_nx16i16(ptr %pa) { ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx32i16(ptr %pa) { @@ -285,7 +285,7 @@ define @vload_nx32i16(ptr %pa) { ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx1i32(ptr %pa) { @@ -307,7 +307,7 @@ define @vload_nx1i32(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx2i32(ptr %pa) { @@ -329,7 +329,7 @@ define @vload_nx2i32(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx4i32(ptr %pa) { @@ -351,7 +351,7 @@ define @vload_nx4i32(ptr %pa) { ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx8i32(ptr %pa) { @@ -373,7 +373,7 @@ define @vload_nx8i32(ptr %pa) { ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx16i32(ptr %pa) { @@ -395,7 +395,7 @@ define @vload_nx16i32(ptr %pa) { ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx1i64(ptr %pa) { @@ -417,7 +417,7 @@ define @vload_nx1i64(ptr %pa) { ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx2i64(ptr %pa) { @@ -439,7 +439,7 @@ define @vload_nx2i64(ptr %pa) { ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx4i64(ptr %pa) { @@ -461,7 +461,7 @@ define @vload_nx4i64(ptr %pa) { ; RV64-NEXT: $v8m4 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %va = load , ptr %pa - ret %va + ret %va } define @vload_nx8i64(ptr %pa) { @@ -483,6 +483,336 @@ define @vload_nx8i64(ptr %pa) { ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %va = load , ptr %pa - ret %va + ret %va +} + +define @vload_nx1i8_align2(ptr %pa) { + ; RV32-LABEL: name: vload_nx1i8_align2 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx1i8_align2 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 2 + ret %va +} + +define @vload_nx1i8_align8(ptr %pa) { + ; RV32-LABEL: name: vload_nx1i8_align8 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx1i8_align8 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 8 + ret %va +} + +define @vload_nx1i8_align32(ptr %pa) { + ; RV32-LABEL: name: vload_nx1i8_align32 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx1i8_align32 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 32 + ret %va +} + +define @vload_nx4i16_align8(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16_align8 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx4i16_align8 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 8 + ret %va +} + +define @vload_nx4i16_align16(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16_align16 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx4i16_align16 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 16 + ret %va +} + +define @vload_nx4i16_align64(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16_align64 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx4i16_align64 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 64 + ret %va +} + +define @vload_nx4i16_align128(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16_align128 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx4i16_align128 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 128 + ret %va +} + +define @vload_nx2i32_align4(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i32_align4 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx2i32_align4 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 4 + ret %va +} + +define @vload_nx2i32_align32(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i32_align32 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx2i32_align32 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 32 + ret %va +} + +define @vload_nx2i32_align64(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i32_align64 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx2i32_align64 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 64 + ret %va +} + +define @vload_nx2i32_align128(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i32_align128 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx2i32_align128 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 128 + ret %va +} + +define @vload_nx2i64_align32(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i64_align32 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx2i64_align32 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa, align 32 + ret %va +} + +define @vload_nx2i64_align64(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i64_align64 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx2i64_align64 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa, align 64 + ret %va +} + +define @vload_nx2i64_align128(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i64_align128 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx2i64_align128 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa, align 128 + ret %va +} + +define @vload_nx2i64_align256(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i64_align256 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 256) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx2i64_align256 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 256) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa, align 256 + ret %va } From 0c407eebd656d888e7924a1ddf6409ccc7096848 Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Tue, 5 Mar 2024 17:11:53 -0500 Subject: [PATCH 8/9] align can be smaller/equal/larger than individual element size and smaller/equal/larger than the total vector size --- .../RISCV/GlobalISel/irtranslator/vec-ld.ll | 262 +++++++++++------- 1 file changed, 163 insertions(+), 99 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll index f9a9ed9ae4499..5650e7422bec5 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll @@ -486,160 +486,225 @@ define @vload_nx8i64(ptr %pa) { ret %va } -define @vload_nx1i8_align2(ptr %pa) { - ; RV32-LABEL: name: vload_nx1i8_align2 +define @vload_nx16i8_align1(ptr %pa) { + ; RV32-LABEL: name: vload_nx16i8_align1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) - ; RV32-NEXT: $v8 = COPY [[LOAD]]() - ; RV32-NEXT: PseudoRET implicit $v8 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 1) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 ; - ; RV64-LABEL: name: vload_nx1i8_align2 + ; RV64-LABEL: name: vload_nx16i8_align1 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) - ; RV64-NEXT: $v8 = COPY [[LOAD]]() - ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 2 - ret %va + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 1) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa, align 1 + ret %va } -define @vload_nx1i8_align8(ptr %pa) { - ; RV32-LABEL: name: vload_nx1i8_align8 +define @vload_nx16i8_align2(ptr %pa) { + ; RV32-LABEL: name: vload_nx16i8_align2 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) - ; RV32-NEXT: $v8 = COPY [[LOAD]]() - ; RV32-NEXT: PseudoRET implicit $v8 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 ; - ; RV64-LABEL: name: vload_nx1i8_align8 + ; RV64-LABEL: name: vload_nx16i8_align2 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) - ; RV64-NEXT: $v8 = COPY [[LOAD]]() - ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 8 - ret %va + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa, align 2 + ret %va } -define @vload_nx1i8_align32(ptr %pa) { - ; RV32-LABEL: name: vload_nx1i8_align32 +define @vload_nx16i8_align16(ptr %pa) { + ; RV32-LABEL: name: vload_nx16i8_align16 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) - ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx16i8_align16 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa, align 16 + ret %va +} + +define @vload_nx16i8_align64(ptr %pa) { + ; RV32-LABEL: name: vload_nx16i8_align64 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m2 + ; + ; RV64-LABEL: name: vload_nx16i8_align64 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa, align 64 + ret %va +} + +define @vload_nx4i16_align1(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16_align1 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 1) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; - ; RV64-LABEL: name: vload_nx1i8_align32 + ; RV64-LABEL: name: vload_nx4i16_align1 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) - ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 1) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 32 - ret %va + %va = load , ptr %pa, align 1 + ret %va } -define @vload_nx4i16_align8(ptr %pa) { - ; RV32-LABEL: name: vload_nx4i16_align8 +define @vload_nx4i16_align2(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16_align2 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; - ; RV64-LABEL: name: vload_nx4i16_align8 + ; RV64-LABEL: name: vload_nx4i16_align2 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 8 + %va = load , ptr %pa, align 2 ret %va } -define @vload_nx4i16_align16(ptr %pa) { - ; RV32-LABEL: name: vload_nx4i16_align16 +define @vload_nx4i16_align4(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16_align4 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; - ; RV64-LABEL: name: vload_nx4i16_align16 + ; RV64-LABEL: name: vload_nx4i16_align4 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 16 + %va = load , ptr %pa, align 4 ret %va } - -define @vload_nx4i16_align64(ptr %pa) { - ; RV32-LABEL: name: vload_nx4i16_align64 +define @vload_nx4i16_align8(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16_align8 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; - ; RV64-LABEL: name: vload_nx4i16_align64 + ; RV64-LABEL: name: vload_nx4i16_align8 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 64 + %va = load , ptr %pa, align 8 ret %va } -define @vload_nx4i16_align128(ptr %pa) { - ; RV32-LABEL: name: vload_nx4i16_align128 +define @vload_nx4i16_align16(ptr %pa) { + ; RV32-LABEL: name: vload_nx4i16_align16 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; - ; RV64-LABEL: name: vload_nx4i16_align128 + ; RV64-LABEL: name: vload_nx4i16_align16 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 128 + %va = load , ptr %pa, align 16 ret %va } +define @vload_nx2i32_align2(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i32_align2 + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx2i32_align2 + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 2) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa, align 2 + ret %va +} + define @vload_nx2i32_align4(ptr %pa) { ; RV32-LABEL: name: vload_nx2i32_align4 ; RV32: bb.1 (%ir-block.0): @@ -662,157 +727,156 @@ define @vload_nx2i32_align4(ptr %pa) { ret %va } -define @vload_nx2i32_align32(ptr %pa) { - ; RV32-LABEL: name: vload_nx2i32_align32 +define @vload_nx2i32_align8(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i32_align8 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; - ; RV64-LABEL: name: vload_nx2i32_align32 + ; RV64-LABEL: name: vload_nx2i32_align8 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 32 + %va = load , ptr %pa, align 8 ret %va } -define @vload_nx2i32_align64(ptr %pa) { - ; RV32-LABEL: name: vload_nx2i32_align64 +define @vload_nx2i32_align16(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i32_align16 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; - ; RV64-LABEL: name: vload_nx2i32_align64 + ; RV64-LABEL: name: vload_nx2i32_align16 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 16) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 64 + %va = load , ptr %pa, align 16 ret %va } -define @vload_nx2i32_align128(ptr %pa) { - ; RV32-LABEL: name: vload_nx2i32_align128 +define @vload_nx2i32_align256(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i32_align256 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 256) ; RV32-NEXT: $v8 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8 ; - ; RV64-LABEL: name: vload_nx2i32_align128 + ; RV64-LABEL: name: vload_nx2i32_align256 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 256) ; RV64-NEXT: $v8 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8 - %va = load , ptr %pa, align 128 + %va = load , ptr %pa, align 256 ret %va } - -define @vload_nx2i64_align32(ptr %pa) { - ; RV32-LABEL: name: vload_nx2i64_align32 +define @vload_nx2i64_align4(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i64_align4 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m2 ; - ; RV64-LABEL: name: vload_nx2i64_align32 + ; RV64-LABEL: name: vload_nx2i64_align4 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 4) ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 - %va = load , ptr %pa, align 32 + %va = load , ptr %pa, align 4 ret %va } -define @vload_nx2i64_align64(ptr %pa) { - ; RV32-LABEL: name: vload_nx2i64_align64 +define @vload_nx2i64_align8(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i64_align8 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m2 ; - ; RV64-LABEL: name: vload_nx2i64_align64 + ; RV64-LABEL: name: vload_nx2i64_align8 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 64) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 8) ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 - %va = load , ptr %pa, align 64 + %va = load , ptr %pa, align 8 ret %va } -define @vload_nx2i64_align128(ptr %pa) { - ; RV32-LABEL: name: vload_nx2i64_align128 +define @vload_nx2i64_align16(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i64_align16 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m2 ; - ; RV64-LABEL: name: vload_nx2i64_align128 + ; RV64-LABEL: name: vload_nx2i64_align16 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 128) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 - %va = load , ptr %pa, align 128 + %va = load , ptr %pa, align 16 ret %va } -define @vload_nx2i64_align256(ptr %pa) { - ; RV32-LABEL: name: vload_nx2i64_align256 +define @vload_nx2i64_align32(ptr %pa) { + ; RV32-LABEL: name: vload_nx2i64_align32 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: liveins: $x10 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 256) + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) ; RV32-NEXT: $v8m2 = COPY [[LOAD]]() ; RV32-NEXT: PseudoRET implicit $v8m2 ; - ; RV64-LABEL: name: vload_nx2i64_align256 + ; RV64-LABEL: name: vload_nx2i64_align32 ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: liveins: $x10 ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 - ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 256) + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa, align 32) ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() ; RV64-NEXT: PseudoRET implicit $v8m2 - %va = load , ptr %pa, align 256 + %va = load , ptr %pa, align 32 ret %va } From 16dfb7b919e9ee6f7e42c7bc7714a35fab9996a3 Mon Sep 17 00:00:00 2001 From: jiahanxie353 Date: Tue, 5 Mar 2024 17:34:22 -0500 Subject: [PATCH 9/9] load a vector of pointers --- .../RISCV/GlobalISel/irtranslator/vec-ld.ll | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll index 5650e7422bec5..31b3c3fe3c5be 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ld.ll @@ -880,3 +880,69 @@ define @vload_nx2i64_align32(ptr %pa) { ret %va } +define @vload_nx1ptr(ptr %pa) { + ; RV32-LABEL: name: vload_nx1ptr + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx1ptr + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8 + %va = load , ptr %pa + ret %va +} + +define @vload_nx2ptr(ptr %pa) { + ; RV32-LABEL: name: vload_nx2ptr + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8 + ; + ; RV64-LABEL: name: vload_nx2ptr + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8m2 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m2 + %va = load , ptr %pa + ret %va +} + +define @vload_nx8ptr(ptr %pa) { + ; RV32-LABEL: name: vload_nx8ptr + ; RV32: bb.1 (%ir-block.0): + ; RV32-NEXT: liveins: $x10 + ; RV32-NEXT: {{ $}} + ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV32-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV32-NEXT: $v8m4 = COPY [[LOAD]]() + ; RV32-NEXT: PseudoRET implicit $v8m4 + ; + ; RV64-LABEL: name: vload_nx8ptr + ; RV64: bb.1 (%ir-block.0): + ; RV64-NEXT: liveins: $x10 + ; RV64-NEXT: {{ $}} + ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10 + ; RV64-NEXT: [[LOAD:%[0-9]+]]:_() = G_LOAD [[COPY]](p0) :: (load () from %ir.pa) + ; RV64-NEXT: $v8m8 = COPY [[LOAD]]() + ; RV64-NEXT: PseudoRET implicit $v8m8 + %va = load , ptr %pa + ret %va +} +