diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 8235b536c4e00..f72b9ad6e948f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -9671,13 +9671,10 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op, // size of the subvector. MVT InterSubVT = VecVT; SDValue AlignedExtract = Vec; - unsigned AlignedIdx = OrigIdx - RemIdx; if (VecVT.bitsGT(getLMUL1VT(VecVT))) { InterSubVT = getLMUL1VT(VecVT); - // Extract a subvector equal to the nearest full vector register type. This - // should resolve to a EXTRACT_SUBREG instruction. - AlignedExtract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InterSubVT, Vec, - DAG.getConstant(AlignedIdx, DL, XLenVT)); + // Extract a subvector equal to the nearest full vector register type. + AlignedExtract = DAG.getTargetExtractSubreg(SubRegIdx, DL, InterSubVT, Vec); } SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InterSubVT, @@ -9705,10 +9702,8 @@ SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op, } // If required, insert this subvector back into the correct vector register. - // This should resolve to an INSERT_SUBREG instruction. if (VecVT.bitsGT(InterSubVT)) - SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecVT, Vec, SubVec, - DAG.getConstant(AlignedIdx, DL, XLenVT)); + SubVec = DAG.getTargetInsertSubreg(SubRegIdx, DL, VecVT, Vec, SubVec); // We might have bitcast from a mask type: cast back to the original type if // required. diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index a14f9a2835473..0e8e040be99ba 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -190,18 +190,22 @@ static bool hasUndefinedMergeOp(const MachineInstr &MI, if (UseMO.getReg() == RISCV::NoRegister) return true; - if (MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg())) { - if (UseMI->isImplicitDef()) - return true; + Register SrcReg = + MRI.getTargetRegisterInfo()->lookThruCopyLike(UseMO.getReg(), &MRI); + if (SrcReg.isPhysical()) + return false; - if (UseMI->isRegSequence()) { - for (unsigned i = 1, e = UseMI->getNumOperands(); i < e; i += 2) { - MachineInstr *SourceMI = MRI.getVRegDef(UseMI->getOperand(i).getReg()); - if (!SourceMI || !SourceMI->isImplicitDef()) - return false; - } - return true; + MachineInstr *UseMI = MRI.getUniqueVRegDef(SrcReg); + if (UseMI->isImplicitDef()) + return true; + + if (UseMI->isRegSequence()) { + for (unsigned i = 1, e = UseMI->getNumOperands(); i < e; i += 2) { + MachineInstr *SourceMI = MRI.getVRegDef(UseMI->getOperand(i).getReg()); + if (!SourceMI || !SourceMI->isImplicitDef()) + return false; } + return true; } return false; } diff --git a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll index a2d02b6bb641b..77ea6c0b26d0a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll @@ -469,14 +469,13 @@ define @extract_nxv6f16_nxv12f16_6( %in) ; CHECK: # %bb.0: ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: vslidedown.vx v13, v10, a0 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma -; CHECK-NEXT: vslidedown.vx v12, v9, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma -; CHECK-NEXT: vslideup.vx v12, v10, a0 -; CHECK-NEXT: vmv2r.v v8, v12 +; CHECK-NEXT: vslideup.vx v8, v10, a0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma +; CHECK-NEXT: vslidedown.vx v9, v10, a0 ; CHECK-NEXT: ret %res = call @llvm.vector.extract.nxv6f16.nxv12f16( %in, i64 6) ret %res