The illegal_bins usage is a bit controversial, as some people may want to use it as a checker to ensure that a particular configuration didn't happened. The thing is that, this will be checked only when the coverage will be enabled and depending on the simulator used, the simulation can be seen as "passed".

• This comment gives an example and shows the current behaviour with VCS and Xcelium.
• And @hcallahan-lowrisc says: I tested the illegal_bins error generation in xcelium (on the ibex repo). If an illegal bin is hit, we see a print to the log (xmsim: *SE,EILLCT) each time at the timestamp it is hit, but the simulation is not killed. However, the simulation ends with retcode = 1, indicating an error occurred. Normally the retcode is 0. Note that we still see the fancy print “--- RISC-V UVM TEST PASSED ---” from our report server, but the server determines to print PASSED or FAILED based on summing up the total number of UVM warnings, errors and fatals. Since the illegal_bins error is a language feature, the simulator itself generates the error, and UVM does not know anything about it. If dvsim is ignoring the retcode of the simulator, I’m not sure if that is correct.

What comes after our talk during our DV meeting, all these points below are suggestions and should be discussed further:

• Don't use it for checking purpose
• Propose to use assertion or UVM check as an alternative
• Prefer ignore_bins instead
• Can be used for the default case
• Fix DVsim to spit out the correct error from Xcelium: *SE,EILLCT line