From d88b6c79694ef7b2033fede8d1a587d8ea86382d Mon Sep 17 00:00:00 2001 From: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> Date: Sun, 30 Aug 2020 17:29:14 +0900 Subject: [PATCH 1/2] describe a clock signal must be generated by blocking assignment Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> --- VerilogCodingStyle.md | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/VerilogCodingStyle.md b/VerilogCodingStyle.md index a9ff36e..2439cd9 100644 --- a/VerilogCodingStyle.md +++ b/VerilogCodingStyle.md @@ -1900,6 +1900,28 @@ separate combinational (`always_comb`) block. Ideally, sequential blocks should contain only a register instantiation, with perhaps a load enable or an increment. +***All clock signals should be generated using blocking assignment even +for clock dividers.*** + +See #44 for details. + +👍 +```systemverilog {.good} +// only for test bench code +logic clk; +initial begin + clk <= 1'b0; + forever #5 clk = ~clk; // blocking assignment +end + +// for both synthesizable and test bench code +logic clk_div2; +always_ff @(posedge clk or negedge rst_ni) begin + if (!rst_ni) clk_div2 = 1'b0; + else clk_div2 = ~clk_div2; // blocking assignment +end +``` + ### Don't Cares (`X`'s) ***The use of `X` literals in RTL code is strongly discouraged. RTL must not From 0e654ad68b69505069db09f4cf19be7b5bb4994b Mon Sep 17 00:00:00 2001 From: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> Date: Sun, 15 Sep 2024 22:35:37 +0900 Subject: [PATCH 2/2] make a section "clock generation" Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> --- VerilogCodingStyle.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/VerilogCodingStyle.md b/VerilogCodingStyle.md index 2439cd9..7de1b5e 100644 --- a/VerilogCodingStyle.md +++ b/VerilogCodingStyle.md @@ -1900,10 +1900,15 @@ separate combinational (`always_comb`) block. Ideally, sequential blocks should contain only a register instantiation, with perhaps a load enable or an increment. +Exception: Even in a sequential always block, use blocking assignments (`=`) for +clock dividers. See [Clock Generation](#clock-generation). + +### Clock Generation + ***All clock signals should be generated using blocking assignment even for clock dividers.*** -See #44 for details. +See #44 for more details. 👍 ```systemverilog {.good}