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blocking assignment must be used for a clock divider #44

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d88b6c7
describe a clock signal must be generated by blocking assignment
hirooih Aug 30, 2020
0e654ad
make a section "clock generation"
hirooih Sep 15, 2024
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27 changes: 27 additions & 0 deletions VerilogCodingStyle.md
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Expand Up @@ -1900,6 +1900,33 @@ separate combinational (`always_comb`) block. Ideally, sequential blocks should
contain only a register instantiation, with perhaps a load enable or an
increment.

Exception: Even in a sequential always block, use blocking assignments (`=`) for
clock dividers. See [Clock Generation](#clock-generation).

### Clock Generation

***All clock signals should be generated using blocking assignment even
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This should probably be a new section. It's currently written under Sequential Logic (Registers), but it is not about registers. Perhaps Sequential Logic (Clock Dividers) or some such?

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I agree with you.

On my first PR it was only for clock dividers. During the discussion on this PR @rich-ho suggested me applying this rule to clock generation in general.

... to add a style guide statement that all clocks should be generated using blocking assigns. I think that perhaps the wording needs to be clearer and the reason made explicit.

I agreed with him, too. But if we do that, we also need an example for clock generation other than clock divider, so I added it.

As you wrote this rule is not for the section "Sequential Logic (Registers)" now.

I have separated it into a section called “Generating Clock”.
This time I did not squash the commits so that the changes are visible.

How about this?

for clock dividers.***

See #44 for more details.

👍
```systemverilog {.good}
// only for test bench code
logic clk;
initial begin
clk <= 1'b0;
forever #5 clk = ~clk; // blocking assignment
end
Comment on lines +1915 to +1920
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@a-will a-will Sep 15, 2024 •
edited
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This portion of the code isn't really relevant for this section. Since this guidance is about how to construct the divider, we don't need to see how clk is generated. I'd recommend removing it.

Edit: Or am I misunderstanding and you also want to show how to generate clock source stimulus in a testbench?

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Edit: Or am I misunderstanding and you also want to show how to generate clock source stimulus in a testbench?

No, I don't.


// for both synthesizable and test bench code
logic clk_div2;
always_ff @(posedge clk or negedge rst_ni) begin
if (!rst_ni) clk_div2 = 1'b0;
else clk_div2 = ~clk_div2; // blocking assignment
end
```

### Don't Cares (`X`'s)

***The use of `X` literals in RTL code is strongly discouraged. RTL must not
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