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8309258: RISC-V: Add riscv_hwprobe syscall
Reviewed-by: fjiang, stuefe, fyang, luhenry
1 parent 4a9cc8a commit 31b6fd7

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5 files changed

+529
-109
lines changed

5 files changed

+529
-109
lines changed

‎src/hotspot/cpu/riscv/vm_version_riscv.cpp

Lines changed: 27 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
/*
22
* Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
33
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
4+
* Copyright (c) 2023, Rivos Inc. All rights reserved.
45
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
56
*
67
* This code is free software; you can redistribute it and/or modify it
@@ -30,24 +31,35 @@
3031
#include "utilities/formatBuffer.hpp"
3132
#include "utilities/macros.hpp"
3233

33-
const char* VM_Version::_uarch = "";
34-
const char* VM_Version::_vm_mode = "";
34+
#include <ctype.h>
35+
3536
uint32_t VM_Version::_initial_vector_length = 0;
3637

38+
#define DEF_RV_FEATURE(NAME, PRETTY, BIT, FSTRING, FLAGF) \
39+
VM_Version::NAME##RVFeatureValue VM_Version::NAME(PRETTY, BIT, FSTRING);
40+
RV_FEATURE_FLAGS(DEF_RV_FEATURE)
41+
42+
#define ADD_RV_FEATURE_IN_LIST(NAME, PRETTY, BIT, FSTRING, FLAGF) \
43+
&VM_Version::NAME,
44+
VM_Version::RVFeatureValue* VM_Version::_feature_list[] = {
45+
RV_FEATURE_FLAGS(ADD_RV_FEATURE_IN_LIST)
46+
nullptr};
47+
3748
void VM_Version::initialize() {
3849
_supports_cx8 = true;
3950
_supports_atomic_getset4 = true;
4051
_supports_atomic_getadd4 = true;
4152
_supports_atomic_getset8 = true;
4253
_supports_atomic_getadd8 = true;
4354

44-
get_os_cpu_info();
55+
setup_cpu_available_features();
4556

4657
// check if satp.mode is supported, currently supports up to SV48(RV64)
47-
if (get_satp_mode() > VM_SV48) {
58+
if (satp_mode.value() > VM_SV48 || satp_mode.value() < VM_MBARE) {
4859
vm_exit_during_initialization(
49-
err_msg("Unsupported satp mode: %s. Only satp modes up to sv48 are supported for now.",
50-
_vm_mode));
60+
err_msg(
61+
"Unsupported satp mode: SV%d. Only satp modes up to sv48 are supported for now.",
62+
(int)satp_mode.value()));
5163
}
5264

5365
// https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva20-profiles
@@ -165,16 +177,16 @@ void VM_Version::initialize() {
165177
}
166178

167179
if (UseRVV) {
168-
if (!(_features & CPU_V)) {
180+
if (!ext_V.enabled()) {
169181
warning("RVV is not supported on this CPU");
170182
FLAG_SET_DEFAULT(UseRVV, false);
171183
} else {
172184
// read vector length from vector CSR vlenb
173-
_initial_vector_length = get_current_vector_length();
185+
_initial_vector_length = cpu_vector_length();
174186
}
175187
}
176188

177-
if (UseRVC && !(_features & CPU_C)) {
189+
if (UseRVC && !ext_C.enabled()) {
178190
warning("RVC is not supported on this CPU");
179191
FLAG_SET_DEFAULT(UseRVC, false);
180192

@@ -185,7 +197,11 @@ void VM_Version::initialize() {
185197
}
186198

187199
if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
188-
FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
200+
if (unaligned_access.value() != MISALIGNED_FAST) {
201+
FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
202+
} else {
203+
FLAG_SET_DEFAULT(AvoidUnalignedAccesses, false);
204+
}
189205
}
190206

191207
if (UseZbb) {
@@ -208,16 +224,6 @@ void VM_Version::initialize() {
208224
FLAG_SET_DEFAULT(UseBlockZeroing, false);
209225
}
210226

211-
char buf[512];
212-
buf[0] = '\0';
213-
if (_uarch != nullptr && strcmp(_uarch, "") != 0) snprintf(buf, sizeof(buf), "%s,", _uarch);
214-
strcat(buf, "rv64");
215-
#define ADD_FEATURE_IF_SUPPORTED(id, name, bit) if (_features & CPU_##id) strcat(buf, name);
216-
CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
217-
#undef ADD_FEATURE_IF_SUPPORTED
218-
219-
_features_string = os::strdup(buf);
220-
221227
#ifdef COMPILER2
222228
c2_initialize();
223229
#endif // COMPILER2
@@ -333,6 +339,6 @@ void VM_Version::initialize_cpu_information(void) {
333339
_no_of_threads = _no_of_cores;
334340
_no_of_sockets = _no_of_cores;
335341
snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "RISCV64");
336-
snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "RISCV64 %s", _features_string);
342+
snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "RISCV64 %s", features_string());
337343
_initialized = true;
338344
}

‎src/hotspot/cpu/riscv/vm_version_riscv.hpp

Lines changed: 158 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
33
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
44
* Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
5+
* Copyright (c) 2023, Rivos Inc. All rights reserved.
56
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
67
*
78
* This code is free software; you can redistribute it and/or modify it
@@ -30,55 +31,176 @@
3031
#include "runtime/abstract_vm_version.hpp"
3132
#include "runtime/arguments.hpp"
3233
#include "runtime/globals_extension.hpp"
34+
#include "utilities/globalDefinitions.hpp"
35+
#include "utilities/growableArray.hpp"
3336
#include "utilities/sizes.hpp"
3437

38+
class RiscvHwprobe;
39+
3540
class VM_Version : public Abstract_VM_Version {
36-
#ifdef COMPILER2
37-
private:
38-
static void c2_initialize();
39-
#endif // COMPILER2
41+
friend RiscvHwprobe;
42+
private:
43+
class RVFeatureValue {
44+
const char* const _pretty;
45+
const bool _feature_string;
46+
const uint64_t _feature_bit;
47+
bool _enabled;
48+
int64_t _value;
49+
public:
50+
RVFeatureValue(const char* pretty, int bit_num, bool fstring) :
51+
_pretty(pretty), _feature_string(fstring), _feature_bit(nth_bit(bit_num)),
52+
_enabled(false), _value(-1) {
53+
}
54+
void enable_feature(int64_t value = 0) {
55+
_enabled = true;
56+
_value = value;
57+
}
58+
const char* const pretty() { return _pretty; }
59+
const uint64_t feature_bit() { return _feature_bit; }
60+
const bool feature_string() { return _feature_string; }
61+
bool enabled() { return _enabled; }
62+
int64_t value() { return _value; }
63+
virtual void update_flag() = 0;
64+
};
4065

41-
// VM modes (satp.mode) privileged ISA 1.10
42-
enum VM_MODE {
43-
VM_MBARE = 0,
44-
VM_SV39 = 8,
45-
VM_SV48 = 9,
46-
VM_SV57 = 10,
47-
VM_SV64 = 11
48-
};
66+
#define UPDATE_DEFAULT(flag) \
67+
void update_flag() { \
68+
assert(enabled(), "Must be."); \
69+
if (FLAG_IS_DEFAULT(flag)) { \
70+
FLAG_SET_DEFAULT(flag, true); \
71+
} \
72+
} \
73+
74+
#define NO_UPDATE_DEFAULT \
75+
void update_flag() {} \
76+
77+
// Frozen standard extensions
78+
// I RV64I
79+
// M Integer Multiplication and Division
80+
// A Atomic Instructions
81+
// F Single-Precision Floating-Point
82+
// D Single-Precision Floating-Point
83+
// (G = M + A + F + D)
84+
// Q Quad-Precision Floating-Point
85+
// C Compressed Instructions
86+
// H Hypervisor
87+
//
88+
// Others, open and non-standard
89+
// V Vector
90+
//
91+
// Cache Management Operations
92+
// Zicbom Cache Block Management Operations
93+
// Zicboz Cache Block Zero Operations
94+
// Zicbop Cache Block Prefetch Operations
95+
//
96+
// Bit-manipulation
97+
// Zba Address generation instructions
98+
// Zbb Basic bit-manipulation
99+
// Zbc Carry-less multiplication
100+
// Zbs Single-bit instructions
101+
//
102+
// Zicsr Control and Status Register (CSR) Instructions
103+
// Zifencei Instruction-Fetch Fence
104+
// Zic64b Cache blocks must be 64 bytes in size, naturally aligned in the address space.
105+
// Zihintpause Pause instruction HINT
106+
//
107+
// Other features and settings
108+
// mvendorid Manufactory JEDEC id encoded, ISA vol 2 3.1.2..
109+
// marchid Id for microarch. Mvendorid plus marchid uniquely identify the microarch.
110+
// mimpid A unique encoding of the version of the processor implementation.
111+
// unaligned_access Unaligned memory accesses (unknown, unspported, emulated, slow, firmware, fast)
112+
// satp mode SATP bits (number of virtual addr bits) mbare, sv39, sv48, sv57, sv64
113+
114+
#define RV_NO_FLAG_BIT (BitsPerWord+1) // nth_bit will return 0 on values larger than BitsPerWord
115+
116+
// declaration name , extension name, bit pos ,in str, mapped flag)
117+
#define RV_FEATURE_FLAGS(decl) \
118+
decl(ext_I , "i" , ('I' - 'A'), true , NO_UPDATE_DEFAULT) \
119+
decl(ext_M , "m" , ('M' - 'A'), true , NO_UPDATE_DEFAULT) \
120+
decl(ext_A , "a" , ('A' - 'A'), true , NO_UPDATE_DEFAULT) \
121+
decl(ext_F , "f" , ('F' - 'A'), true , NO_UPDATE_DEFAULT) \
122+
decl(ext_D , "d" , ('D' - 'A'), true , NO_UPDATE_DEFAULT) \
123+
decl(ext_C , "c" , ('C' - 'A'), true , UPDATE_DEFAULT(UseRVC)) \
124+
decl(ext_Q , "q" , ('Q' - 'A'), true , NO_UPDATE_DEFAULT) \
125+
decl(ext_H , "h" , ('H' - 'A'), true , NO_UPDATE_DEFAULT) \
126+
decl(ext_V , "v" , ('V' - 'A'), true , UPDATE_DEFAULT(UseRVV)) \
127+
decl(ext_Zicbom , "Zicbom" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZicbom)) \
128+
decl(ext_Zicboz , "Zicboz" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZicboz)) \
129+
decl(ext_Zicbop , "Zicbop" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZicbop)) \
130+
decl(ext_Zba , "Zba" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZba)) \
131+
decl(ext_Zbb , "Zbb" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbb)) \
132+
decl(ext_Zbc , "Zbc" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
133+
decl(ext_Zbs , "Zbs" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZbs)) \
134+
decl(ext_Zicsr , "Zicsr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
135+
decl(ext_Zifencei , "Zifencei" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
136+
decl(ext_Zic64b , "Zic64b" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZic64b)) \
137+
decl(ext_Zihintpause , "Zihintpause" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZihintpause)) \
138+
decl(mvendorid , "VendorId" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
139+
decl(marchid , "ArchId" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
140+
decl(mimpid , "ImpId" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
141+
decl(unaligned_access, "Unaligned" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
142+
decl(satp_mode , "SATP" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
143+
144+
#define DECLARE_RV_FEATURE(NAME, PRETTY, BIT, FSTRING, FLAGF) \
145+
struct NAME##RVFeatureValue : public RVFeatureValue { \
146+
NAME##RVFeatureValue(const char* pretty, int bit, bool fstring) : \
147+
RVFeatureValue(pretty, bit, fstring) {} \
148+
FLAGF; \
149+
}; \
150+
static NAME##RVFeatureValue NAME; \
151+
152+
RV_FEATURE_FLAGS(DECLARE_RV_FEATURE)
153+
#undef DECLARE_RV_FEATURE
154+
155+
// VM modes (satp.mode) privileged ISA 1.10
156+
enum VM_MODE : int {
157+
VM_NOTSET = -1,
158+
VM_MBARE = 0,
159+
VM_SV39 = 39,
160+
VM_SV48 = 48,
161+
VM_SV57 = 57,
162+
VM_SV64 = 64
163+
};
164+
165+
static VM_MODE parse_satp_mode(const char* vm_mode);
166+
167+
// Values from riscv_hwprobe()
168+
enum UNALIGNED_ACCESS : int {
169+
MISALIGNED_UNKNOWN = 0,
170+
MISALIGNED_EMULATED = 1,
171+
MISALIGNED_SLOW = 2,
172+
MISALIGNED_FAST = 3,
173+
MISALIGNED_UNSUPPORTED = 4
174+
};
49175

50-
protected:
51-
static const char* _uarch;
52-
static const char* _vm_mode;
176+
// Null terminated list
177+
static RVFeatureValue* _feature_list[];
178+
179+
// Enables features in _feature_list
180+
static void setup_cpu_available_features();
181+
// Helper for specific queries
182+
static void os_aux_features();
183+
static char* os_uarch_additional_features();
184+
static void vendor_features();
185+
// Vendors specific features
186+
static void rivos_features();
187+
188+
// Determine vector length iff ext_V/UseRVV
189+
static uint32_t cpu_vector_length();
53190
static uint32_t _initial_vector_length;
54-
static void get_os_cpu_info();
55-
static uint32_t get_current_vector_length();
56-
static VM_MODE get_satp_mode();
57191

58-
public:
192+
#ifdef COMPILER2
193+
static void c2_initialize();
194+
#endif // COMPILER2
195+
196+
public:
59197
// Initialization
60198
static void initialize();
199+
static void initialize_cpu_information();
61200

62201
constexpr static bool supports_stack_watermark_barrier() { return true; }
63202

64203
static bool supports_on_spin_wait() { return UseZihintpause; }
65-
66-
enum Feature_Flag {
67-
#define CPU_FEATURE_FLAGS(decl) \
68-
decl(I, "i", 8) \
69-
decl(M, "m", 12) \
70-
decl(A, "a", 0) \
71-
decl(F, "f", 5) \
72-
decl(D, "d", 3) \
73-
decl(C, "c", 2) \
74-
decl(V, "v", 21)
75-
76-
#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1 << bit),
77-
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
78-
#undef DECLARE_CPU_FEATURE_FLAG
79-
};
80-
81-
static void initialize_cpu_information(void);
82204
};
83205

84206
#endif // CPU_RISCV_VM_VERSION_RISCV_HPP

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