From 5901e91288f471ae82ba38824664d00ac591d9ac Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Tue, 7 Mar 2023 22:57:14 +0100 Subject: [PATCH 1/4] i2c: remove iter methods. --- embedded-hal/src/i2c.rs | 91 ----------------------------------------- 1 file changed, 91 deletions(-) diff --git a/embedded-hal/src/i2c.rs b/embedded-hal/src/i2c.rs index 67097ab2f..54295a644 100644 --- a/embedded-hal/src/i2c.rs +++ b/embedded-hal/src/i2c.rs @@ -37,26 +37,14 @@ //! // ... //! # Ok(()) //! } -//! fn write_iter>(&mut self, addr: u8, bytes: B) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } //! fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } -//! fn write_iter_read>(&mut self, addr: u8, bytes: B, buffer: &mut [u8]) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } //! fn transaction<'a>(&mut self, address: u8, operations: &mut [Operation<'a>]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } -//! fn transaction_iter<'a, O: IntoIterator>>(&mut self, address: u8, operations: O) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } //! } //! //! impl I2c for I2c0 @@ -69,26 +57,14 @@ //! // ... //! # Ok(()) //! } -//! fn write_iter>(&mut self, addr: u16, bytes: B) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } //! fn write_read(&mut self, addr: u16, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } -//! fn write_iter_read>(&mut self, addr: u16, bytes: B, buffer: &mut [u8]) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } //! fn transaction<'a>(&mut self, address: u16, operations: &mut [Operation<'a>]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } -//! fn transaction_iter<'a, O: IntoIterator>>(&mut self, address: u16, operations: O) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } //! } //! ``` //! @@ -307,15 +283,6 @@ pub trait I2c: ErrorType { /// - `SP` = stop condition fn write(&mut self, address: A, bytes: &[u8]) -> Result<(), Self::Error>; - /// Writes bytes to slave with address `address` - /// - /// # I2C Events (contract) - /// - /// Same as the `write` method - fn write_iter(&mut self, address: A, bytes: B) -> Result<(), Self::Error> - where - B: IntoIterator; - /// Writes bytes to slave with address `address` and then reads enough bytes to fill `buffer` *in a /// single transaction* /// @@ -345,21 +312,6 @@ pub trait I2c: ErrorType { buffer: &mut [u8], ) -> Result<(), Self::Error>; - /// Writes bytes to slave with address `address` and then reads enough bytes to fill `buffer` *in a - /// single transaction* - /// - /// # I2C Events (contract) - /// - /// Same as the `write_read` method - fn write_iter_read( - &mut self, - address: A, - bytes: B, - buffer: &mut [u8], - ) -> Result<(), Self::Error> - where - B: IntoIterator; - /// Execute the provided operations on the I2C bus. /// /// Transaction contract: @@ -378,23 +330,6 @@ pub trait I2c: ErrorType { address: A, operations: &mut [Operation<'a>], ) -> Result<(), Self::Error>; - - /// Execute the provided operations on the I2C bus (iterator version). - /// - /// Transaction contract: - /// - Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate. - /// - Data from adjacent operations of the same type are sent after each other without an SP or SR. - /// - Between adjacent operations of a different type an SR and SAD+R/W is sent. - /// - After executing the last operation an SP is sent automatically. - /// - If the last operation is a `Read` the master does not send an acknowledge for the last byte. - /// - /// - `ST` = start condition - /// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing - /// - `SR` = repeated start condition - /// - `SP` = stop condition - fn transaction_iter<'a, O>(&mut self, address: A, operations: O) -> Result<(), Self::Error> - where - O: IntoIterator>; } impl> I2c for &mut T { @@ -406,13 +341,6 @@ impl> I2c for &mut T { T::write(self, address, bytes) } - fn write_iter(&mut self, address: A, bytes: B) -> Result<(), Self::Error> - where - B: IntoIterator, - { - T::write_iter(self, address, bytes) - } - fn write_read( &mut self, address: A, @@ -422,18 +350,6 @@ impl> I2c for &mut T { T::write_read(self, address, bytes, buffer) } - fn write_iter_read( - &mut self, - address: A, - bytes: B, - buffer: &mut [u8], - ) -> Result<(), Self::Error> - where - B: IntoIterator, - { - T::write_iter_read(self, address, bytes, buffer) - } - fn transaction<'a>( &mut self, address: A, @@ -441,11 +357,4 @@ impl> I2c for &mut T { ) -> Result<(), Self::Error> { T::transaction(self, address, operations) } - - fn transaction_iter<'a, O>(&mut self, address: A, operations: O) -> Result<(), Self::Error> - where - O: IntoIterator>, - { - T::transaction_iter(self, address, operations) - } } From 9c9e3373709a8d2b335b7580f7eb544a7ce0ede4 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Wed, 8 Mar 2023 01:29:29 +0100 Subject: [PATCH 2/4] i2c: remove useless lifetimes. --- embedded-hal-async/src/i2c.rs | 36 +++++++++++++++++------------------ embedded-hal/src/i2c.rs | 12 ++++++------ 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/embedded-hal-async/src/i2c.rs b/embedded-hal-async/src/i2c.rs index 4f84beb0d..0e505218c 100644 --- a/embedded-hal-async/src/i2c.rs +++ b/embedded-hal-async/src/i2c.rs @@ -41,7 +41,7 @@ pub trait I2c: ErrorType { /// - `MAK` = master acknowledge /// - `NMAK` = master no acknowledge /// - `SP` = stop condition - async fn read<'a>(&'a mut self, address: A, read: &'a mut [u8]) -> Result<(), Self::Error>; + async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error>; /// Writes bytes to slave with address `address` /// @@ -59,7 +59,7 @@ pub trait I2c: ErrorType { /// - `SAK` = slave acknowledge /// - `Bi` = ith byte of data /// - `SP` = stop condition - async fn write<'a>(&'a mut self, address: A, write: &'a [u8]) -> Result<(), Self::Error>; + async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error>; /// Writes bytes to slave with address `address` and then reads enough bytes to fill `read` *in a /// single transaction*. @@ -83,11 +83,11 @@ pub trait I2c: ErrorType { /// - `MAK` = master acknowledge /// - `NMAK` = master no acknowledge /// - `SP` = stop condition - async fn write_read<'a>( - &'a mut self, + async fn write_read( + &mut self, address: A, - write: &'a [u8], - read: &'a mut [u8], + write: &[u8], + read: &mut [u8], ) -> Result<(), Self::Error>; /// Execute the provided operations on the I2C bus as a single transaction. @@ -103,35 +103,35 @@ pub trait I2c: ErrorType { /// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing /// - `SR` = repeated start condition /// - `SP` = stop condition - async fn transaction<'a, 'b>( - &'a mut self, + async fn transaction( + &mut self, address: A, - operations: &'a mut [Operation<'b>], + operations: &mut [Operation<'_>], ) -> Result<(), Self::Error>; } impl> I2c for &mut T { - async fn read<'a>(&'a mut self, address: A, buffer: &'a mut [u8]) -> Result<(), Self::Error> { + async fn read(&mut self, address: A, buffer: &mut [u8]) -> Result<(), Self::Error> { T::read(self, address, buffer).await } - async fn write<'a>(&'a mut self, address: A, bytes: &'a [u8]) -> Result<(), Self::Error> { + async fn write(&mut self, address: A, bytes: &[u8]) -> Result<(), Self::Error> { T::write(self, address, bytes).await } - async fn write_read<'a>( - &'a mut self, + async fn write_read( + &mut self, address: A, - bytes: &'a [u8], - buffer: &'a mut [u8], + bytes: &[u8], + buffer: &mut [u8], ) -> Result<(), Self::Error> { T::write_read(self, address, bytes, buffer).await } - async fn transaction<'a, 'b>( - &'a mut self, + async fn transaction( + &mut self, address: A, - operations: &'a mut [Operation<'b>], + operations: &mut [Operation<'_>], ) -> Result<(), Self::Error> { T::transaction(self, address, operations).await } diff --git a/embedded-hal/src/i2c.rs b/embedded-hal/src/i2c.rs index 54295a644..2eccc2cfe 100644 --- a/embedded-hal/src/i2c.rs +++ b/embedded-hal/src/i2c.rs @@ -41,7 +41,7 @@ //! // ... //! # Ok(()) //! } -//! fn transaction<'a>(&mut self, address: u8, operations: &mut [Operation<'a>]) -> Result<(), Self::Error> { +//! fn transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } @@ -61,7 +61,7 @@ //! // ... //! # Ok(()) //! } -//! fn transaction<'a>(&mut self, address: u16, operations: &mut [Operation<'a>]) -> Result<(), Self::Error> { +//! fn transaction(&mut self, address: u16, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } @@ -325,10 +325,10 @@ pub trait I2c: ErrorType { /// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing /// - `SR` = repeated start condition /// - `SP` = stop condition - fn transaction<'a>( + fn transaction( &mut self, address: A, - operations: &mut [Operation<'a>], + operations: &mut [Operation<'_>], ) -> Result<(), Self::Error>; } @@ -350,10 +350,10 @@ impl> I2c for &mut T { T::write_read(self, address, bytes, buffer) } - fn transaction<'a>( + fn transaction( &mut self, address: A, - operations: &mut [Operation<'a>], + operations: &mut [Operation<'_>], ) -> Result<(), Self::Error> { T::transaction(self, address, operations) } From 0a72e01188c3f98234648628aca0c98b15614f3c Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Wed, 8 Mar 2023 01:31:18 +0100 Subject: [PATCH 3/4] i2c: rename args to write/read. --- embedded-hal-async/src/i2c.rs | 14 +++++------ embedded-hal/src/i2c.rs | 44 ++++++++++++++--------------------- 2 files changed, 24 insertions(+), 34 deletions(-) diff --git a/embedded-hal-async/src/i2c.rs b/embedded-hal-async/src/i2c.rs index 0e505218c..fdde6d582 100644 --- a/embedded-hal-async/src/i2c.rs +++ b/embedded-hal-async/src/i2c.rs @@ -111,21 +111,21 @@ pub trait I2c: ErrorType { } impl> I2c for &mut T { - async fn read(&mut self, address: A, buffer: &mut [u8]) -> Result<(), Self::Error> { - T::read(self, address, buffer).await + async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> { + T::read(self, address, read).await } - async fn write(&mut self, address: A, bytes: &[u8]) -> Result<(), Self::Error> { - T::write(self, address, bytes).await + async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> { + T::write(self, address, write).await } async fn write_read( &mut self, address: A, - bytes: &[u8], - buffer: &mut [u8], + write: &[u8], + read: &mut [u8], ) -> Result<(), Self::Error> { - T::write_read(self, address, bytes, buffer).await + T::write_read(self, address, write, read).await } async fn transaction( diff --git a/embedded-hal/src/i2c.rs b/embedded-hal/src/i2c.rs index 2eccc2cfe..c52bcdba0 100644 --- a/embedded-hal/src/i2c.rs +++ b/embedded-hal/src/i2c.rs @@ -29,15 +29,15 @@ //! # impl ErrorType for I2c0 { type Error = ErrorKind; } //! impl I2c for I2c0 //! { -//! fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> { +//! fn read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } -//! fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> { +//! fn write(&mut self, addr: u8, write: &[u8]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } -//! fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> { +//! fn write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } @@ -49,15 +49,15 @@ //! //! impl I2c for I2c0 //! { -//! fn read(&mut self, addr: u16, buffer: &mut [u8]) -> Result<(), Self::Error> { +//! fn read(&mut self, addr: u16, write: &mut [u8]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } -//! fn write(&mut self, addr: u16, bytes: &[u8]) -> Result<(), Self::Error> { +//! fn write(&mut self, addr: u16, read: &[u8]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } -//! fn write_read(&mut self, addr: u16, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> { +//! fn write_read(&mut self, addr: u16, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) //! } @@ -245,7 +245,7 @@ pub enum Operation<'a> { /// Blocking I2C pub trait I2c: ErrorType { - /// Reads enough bytes from slave with `address` to fill `buffer` + /// Reads enough bytes from slave with `address` to fill `read` /// /// # I2C Events (contract) /// @@ -263,7 +263,7 @@ pub trait I2c: ErrorType { /// - `MAK` = master acknowledge /// - `NMAK` = master no acknowledge /// - `SP` = stop condition - fn read(&mut self, address: A, buffer: &mut [u8]) -> Result<(), Self::Error>; + fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error>; /// Writes bytes to slave with address `address` /// @@ -281,9 +281,9 @@ pub trait I2c: ErrorType { /// - `SAK` = slave acknowledge /// - `Bi` = ith byte of data /// - `SP` = stop condition - fn write(&mut self, address: A, bytes: &[u8]) -> Result<(), Self::Error>; + fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error>; - /// Writes bytes to slave with address `address` and then reads enough bytes to fill `buffer` *in a + /// Writes bytes to slave with address `address` and then reads enough bytes to fill `read` *in a /// single transaction* /// /// # I2C Events (contract) @@ -305,12 +305,7 @@ pub trait I2c: ErrorType { /// - `MAK` = master acknowledge /// - `NMAK` = master no acknowledge /// - `SP` = stop condition - fn write_read( - &mut self, - address: A, - bytes: &[u8], - buffer: &mut [u8], - ) -> Result<(), Self::Error>; + fn write_read(&mut self, address: A, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error>; /// Execute the provided operations on the I2C bus. /// @@ -333,21 +328,16 @@ pub trait I2c: ErrorType { } impl> I2c for &mut T { - fn read(&mut self, address: A, buffer: &mut [u8]) -> Result<(), Self::Error> { - T::read(self, address, buffer) + fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> { + T::read(self, address, read) } - fn write(&mut self, address: A, bytes: &[u8]) -> Result<(), Self::Error> { - T::write(self, address, bytes) + fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> { + T::write(self, address, write) } - fn write_read( - &mut self, - address: A, - bytes: &[u8], - buffer: &mut [u8], - ) -> Result<(), Self::Error> { - T::write_read(self, address, bytes, buffer) + fn write_read(&mut self, address: A, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> { + T::write_read(self, address, write, read) } fn transaction( From dd74149f79f54cedca14246a21ad0c6ea164540f Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Wed, 8 Mar 2023 01:34:36 +0100 Subject: [PATCH 4/4] i2c: implement all operations in terms of `transaction`. --- embedded-hal-async/src/i2c.rs | 18 ++++++++++++--- embedded-hal/src/i2c.rs | 41 +++++++++++------------------------ 2 files changed, 28 insertions(+), 31 deletions(-) diff --git a/embedded-hal-async/src/i2c.rs b/embedded-hal-async/src/i2c.rs index fdde6d582..67712dd46 100644 --- a/embedded-hal-async/src/i2c.rs +++ b/embedded-hal-async/src/i2c.rs @@ -41,7 +41,10 @@ pub trait I2c: ErrorType { /// - `MAK` = master acknowledge /// - `NMAK` = master no acknowledge /// - `SP` = stop condition - async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error>; + async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> { + self.transaction(address, &mut [Operation::Read(read)]) + .await + } /// Writes bytes to slave with address `address` /// @@ -59,7 +62,10 @@ pub trait I2c: ErrorType { /// - `SAK` = slave acknowledge /// - `Bi` = ith byte of data /// - `SP` = stop condition - async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error>; + async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> { + self.transaction(address, &mut [Operation::Write(write)]) + .await + } /// Writes bytes to slave with address `address` and then reads enough bytes to fill `read` *in a /// single transaction*. @@ -88,7 +94,13 @@ pub trait I2c: ErrorType { address: A, write: &[u8], read: &mut [u8], - ) -> Result<(), Self::Error>; + ) -> Result<(), Self::Error> { + self.transaction( + address, + &mut [Operation::Write(write), Operation::Read(read)], + ) + .await + } /// Execute the provided operations on the I2C bus as a single transaction. /// diff --git a/embedded-hal/src/i2c.rs b/embedded-hal/src/i2c.rs index c52bcdba0..6b102d0af 100644 --- a/embedded-hal/src/i2c.rs +++ b/embedded-hal/src/i2c.rs @@ -29,18 +29,6 @@ //! # impl ErrorType for I2c0 { type Error = ErrorKind; } //! impl I2c for I2c0 //! { -//! fn read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } -//! fn write(&mut self, addr: u8, write: &[u8]) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } -//! fn write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } //! fn transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) @@ -49,18 +37,6 @@ //! //! impl I2c for I2c0 //! { -//! fn read(&mut self, addr: u16, write: &mut [u8]) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } -//! fn write(&mut self, addr: u16, read: &[u8]) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } -//! fn write_read(&mut self, addr: u16, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> { -//! // ... -//! # Ok(()) -//! } //! fn transaction(&mut self, address: u16, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> { //! // ... //! # Ok(()) @@ -232,7 +208,7 @@ impl AddressMode for SevenBitAddress {} impl AddressMode for TenBitAddress {} -/// Transactional I2C operation. +/// I2C operation. /// /// Several operations can be combined as part of a transaction. #[derive(Debug, PartialEq, Eq)] @@ -263,7 +239,9 @@ pub trait I2c: ErrorType { /// - `MAK` = master acknowledge /// - `NMAK` = master no acknowledge /// - `SP` = stop condition - fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error>; + fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> { + self.transaction(address, &mut [Operation::Read(read)]) + } /// Writes bytes to slave with address `address` /// @@ -281,7 +259,9 @@ pub trait I2c: ErrorType { /// - `SAK` = slave acknowledge /// - `Bi` = ith byte of data /// - `SP` = stop condition - fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error>; + fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> { + self.transaction(address, &mut [Operation::Write(write)]) + } /// Writes bytes to slave with address `address` and then reads enough bytes to fill `read` *in a /// single transaction* @@ -305,7 +285,12 @@ pub trait I2c: ErrorType { /// - `MAK` = master acknowledge /// - `NMAK` = master no acknowledge /// - `SP` = stop condition - fn write_read(&mut self, address: A, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error>; + fn write_read(&mut self, address: A, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> { + self.transaction( + address, + &mut [Operation::Write(write), Operation::Read(read)], + ) + } /// Execute the provided operations on the I2C bus. ///