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LLVM 12 regression (GlobalISel): AArch64 backend generates incorrect code for ashr <i8 x 16> #84028

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LLVM 12 regression (GlobalISel): AArch64 backend generates incorrect code for ashr <i8 x 16>#84028
#84051
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A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.A-SIMDArea: SIMD (Single Instruction Multiple Data)C-bugCategory: This is a bug.I-unsoundIssue: A soundness hole (worst kind of bug), see: https://en.wikipedia.org/wiki/SoundnessO-ArmTarget: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state
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@Amanieu
Amanieu
opened on Apr 9, 2021

This is causing test failures in stdarch (rust-lang/stdarch#1111).

Upstream LLVM bug: https://bugs.llvm.org/show_bug.cgi?id=49904

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    A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.A-SIMDArea: SIMD (Single Instruction Multiple Data)C-bugCategory: This is a bug.I-unsoundIssue: A soundness hole (worst kind of bug), see: https://en.wikipedia.org/wiki/SoundnessO-ArmTarget: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state

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